OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [devs/] [serial/] [freescale/] [esci/] [hdr/] [current/] [include/] [ser_esci.h] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
#ifndef CYGONCE_DEVS_SERIAL_FREESCALE_ESCI_H
2
#define CYGONCE_DEVS_SERIAL_FREESCALE_ESCI_H
3
//==========================================================================
4
//
5
//      ser_esci.h
6
//
7
//      Freescale eSCI Serial I/O definitions.
8
//
9
//==========================================================================
10
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
11
// -------------------------------------------                              
12
// This file is part of eCos, the Embedded Configurable Operating System.   
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
14
//
15
// eCos is free software; you can redistribute it and/or modify it under    
16
// the terms of the GNU General Public License as published by the Free     
17
// Software Foundation; either version 2 or (at your option) any later      
18
// version.                                                                 
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT      
21
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
23
// for more details.                                                        
24
//
25
// You should have received a copy of the GNU General Public License        
26
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
27
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
28
//
29
// As a special exception, if other files instantiate templates or use      
30
// macros or inline functions from this file, or you compile this file      
31
// and link it with other works to produce a work based on this file,       
32
// this file does not by itself cause the resulting work to be covered by   
33
// the GNU General Public License. However the source code for this file    
34
// must still be made available in accordance with section (3) of the GNU   
35
// General Public License v2.                                               
36
//
37
// This exception does not invalidate any other reasons why a work based    
38
// on this file might be covered by the GNU General Public License.         
39
// -------------------------------------------                              
40
// ####ECOSGPLCOPYRIGHTEND####                                              
41
//==========================================================================
42
//#####DESCRIPTIONBEGIN####
43
//
44
// Author(s):   Ilija Koco <ilijak@siva.com.mk>
45
// Contributors:
46
// Date:        2006-04-20
47
// Purpose:     eSCI Serial I/O definitions.
48
// Description: 
49
//
50
//   
51
//####DESCRIPTIONEND####
52
//==========================================================================
53
 
54
// Note: Following macros are platform dependent
55
//       and have to be defined in var_io.h or plf_io.h
56
//    Macros referenced by serial driver:
57
//      CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE
58
//      CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE
59
//      CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE
60
//      CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE
61
//      CYGNUM_DEV_SER_FREESCALE_ESCI_SYSTEM_CLOCK
62
//      FREESCALE_ESCI_BAUD(baud_rate)
63
 
64
//    Macros not referenced by serial driver
65
//    but by interrupt controller
66
//      CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_VECTOR
67
//      CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_VECTOR
68
//      CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_VECTOR
69
//      CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_VECTOR
70
//      MAC7100_ESCI_A_IV
71
//      MAC7100_ESCI_B_IV
72
//      MAC7100_ESCI_C_IV
73
//      MAC7100_ESCI_D_IV
74
//
75
 
76
#define FREESCALE_ESCI_A_BASE       (CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE)
77
#define FREESCALE_ESCI_B_BASE       (CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE)
78
#define FREESCALE_ESCI_C_BASE       (CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE)
79
#define FREESCALE_ESCI_D_BASE       (CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE)
80
 
81
#define FREESCALE_ESCI_A_I  0
82
#define FREESCALE_ESCI_B_I  1
83
#define FREESCALE_ESCI_C_I  2
84
#define FREESCALE_ESCI_D_I  3
85
 
86
#define FREESCALE_ESCI_BD(esci_base)                    \
87
  (esci_base + FREESCALE_ESCI_BD_OFFSET)      //short
88
#define FREESCALE_ESCI_CR12(esci_base)                  \
89
  (esci_base + FREESCALE_ESCI_CR12_OFFSET)    //short
90
#define FREESCALE_ESCI_CR34(esci_base)                  \
91
  (esci_base + FREESCALE_ESCI_CR34_OFFSET)    //short
92
#define FREESCALE_ESCI_CR1(esci_base)                   \
93
  (esci_base + FREESCALE_ESCI_CR1_OFFSET)     //char
94
#define FREESCALE_ESCI_CR2(esci_base)                   \
95
  (esci_base + FREESCALE_ESCI_CR2_OFFSET)     //char
96
#define FREESCALE_ESCI_CR3(esci_base)                   \
97
  (esci_base + FREESCALE_ESCI_CR3_OFFSET)     //char
98
#define FREESCALE_ESCI_CR4(esci_base)                   \
99
  (esci_base + FREESCALE_ESCI_CR4_OFFSET)     //short
100
#define FREESCALE_ESCI_LINCTRL(esci_base)               \
101
  (esci_base + FREESCALE_ESCI_LINCTRL_OFFSET) //short
102
#define FREESCALE_ESCI_LINCRCP(esci_base)               \
103
  (esci_base + FREESCALE_ESCI_LINCRCP_OFFSET) //short
104
#define FREESCALE_ESCI_SR(esci_base)                    \
105
  (esci_base + FREESCALE_ESCI_SR_OFFSET)      //short
106
#define FREESCALE_ESCI_DRL(esci_base)                   \
107
  (esci_base + FREESCALE_ESCI_DRL_OFFSET)     //char
108
 
109
#define FREESCALE_ESCI_BD_OFFSET      (0x0000)
110
#define FREESCALE_ESCI_CR12_OFFSET    (0x0002)
111
#define FREESCALE_ESCI_CR34_OFFSET    (0x0002)
112
#define FREESCALE_ESCI_CR1_OFFSET     (0x0002)
113
#define FREESCALE_ESCI_CR2_OFFSET     (0x0003)
114
#define FREESCALE_ESCI_CR3_OFFSET     (0x0004)
115
#define FREESCALE_ESCI_CR4_OFFSET     (0x0005)
116
#define FREESCALE_ESCI_DRL_OFFSET     (0x0007)
117
#define FREESCALE_ESCI_SR_OFFSET      (0x0008)
118
#define FREESCALE_ESCI_LINSTAT_OFFSET (0x000A)
119
#define FREESCALE_ESCI_LINCTRL_OFFSET (0x000C)
120
#define FREESCALE_ESCI_LINRX_OFFSET   (0x0010)
121
#define FREESCALE_ESCI_LINTX_OFFSET   (0x0014)
122
#define FREESCALE_ESCI_LINCRCP_OFFSET (0x0018)
123
 
124
#define FREESCALE_ESCI_CR12_LOOPS     (0x8000)
125
#define FREESCALE_ESCI_CR12_SCISDOZ   (0x4000)
126
#define FREESCALE_ESCI_CR12_RSRC      (0x2000)
127
#define FREESCALE_ESCI_CR12_M         (0x1000)
128
#define FREESCALE_ESCI_CR12_WAKE      (0x0800)
129
#define FREESCALE_ESCI_CR12_ILT       (0x0400)
130
#define FREESCALE_ESCI_CR12_PE        (0x0200)
131
#define FREESCALE_ESCI_CR12_PT        (0x0100)
132
#define FREESCALE_ESCI_CR12_TIE       (0x0080)
133
#define FREESCALE_ESCI_CR12_TCIE      (0x0040)
134
#define FREESCALE_ESCI_CR12_RIE       (0x0020)
135
#define FREESCALE_ESCI_CR12_ILIE      (0x0010)
136
#define FREESCALE_ESCI_CR12_TE        (0x0008)
137
#define FREESCALE_ESCI_CR12_RE        (0x0004)
138
#define FREESCALE_ESCI_CR12_RWU       (0x0002)
139
#define FREESCALE_ESCI_CR12_SBK       (0x0001)
140
 
141
#define FREESCALE_ESCI_CR3_MDIS       (0x80)
142
#define FREESCALE_ESCI_CR3_FBR        (0x40)
143
#define FREESCALE_ESCI_CR3_BSTP       (0x20)
144
#define FREESCALE_ESCI_CR3_IEBERR     (0x10)
145
#define FREESCALE_ESCI_CR3_RXDMA      (0x08)
146
#define FREESCALE_ESCI_CR3_TXDMA      (0x04)
147
#define FREESCALE_ESCI_CR3_BRK13      (0x02)
148
#define FREESCALE_ESCI_CR3_TXDIR      (0x01)
149
 
150
#define FREESCALE_ESCI_SR_TDRE        (0x8000)
151
#define FREESCALE_ESCI_SR_TC          (0x4000)
152
#define FREESCALE_ESCI_SR_RDRF        (0x2000)
153
#define FREESCALE_ESCI_SR_IDLE        (0x1000)
154
#define FREESCALE_ESCI_SR_OR          (0x0800)
155
#define FREESCALE_ESCI_SR_NF          (0x0400)
156
#define FREESCALE_ESCI_SR_FE          (0x0200)
157
#define FREESCALE_ESCI_SR_PF          (0x0100)
158
#define FREESCALE_ESCI_SR_BERR        (0x0010)
159
#define FREESCALE_ESCI_SR_RAF         (0x0001)
160
 
161
#endif // CYGONCE_DEVS_SERIAL_FREESCALE_ESCI_H
162
// EOF ser_esci.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.