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//==========================================================================
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//
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// ser_freescale_uart.inl
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//
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// Freescale UART Serial channel definitions
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2011 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Ilija Kocho
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// Contributors:
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// Date: 2011-02-10
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// Purpose: Freescale UART Serial I/O module (interrupt driven version)
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// Description:
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//
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//
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//####DESCRIPTIONEND####
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//==========================================================================
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#if defined CYGPKG_IO_SERIAL_FREESCALE_UART0
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static const uart_pins_t uart0_pins = {
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rx : CYGHWR_IO_FREESCALE_UART0_PIN_RX,
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tx : CYGHWR_IO_FREESCALE_UART0_PIN_TX,
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rts : CYGHWR_IO_FREESCALE_UART0_PIN_RTS,
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cts : CYGHWR_IO_FREESCALE_UART0_PIN_CTS
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};
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static uart_serial_info uart_serial_info0 = {
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uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE,
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY,
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pins_p : &uart0_pins
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};
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#if CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE > 0
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static unsigned char
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uart_serial_out_buf0[CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE];
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static unsigned char
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uart_serial_in_buf0[CYGNUM_IO_SERIAL_FREESCALE_UART0_BUFSIZE];
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static
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SERIAL_CHANNEL_USING_INTERRUPTS(
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uart_serial_channel0,
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uart_serial_funs,
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uart_serial_info0,
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CYG_SERIAL_BAUD_RATE(
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CYGNUM_IO_SERIAL_FREESCALE_UART0_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT,
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&uart_serial_out_buf0[0],
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sizeof(uart_serial_out_buf0),
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&uart_serial_in_buf0[0],
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sizeof(uart_serial_in_buf0));
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#else
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static
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SERIAL_CHANNEL(uart_serial_channel0,
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uart_serial_funs,
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uart_serial_info0,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART0_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT);
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#endif
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DEVTAB_ENTRY(uart_serial_io0,
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CYGDAT_IO_SERIAL_FREESCALE_UART0_NAME,
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0, // does not depend on a lower level device driver
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&cyg_io_serial_devio,
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uart_serial_init,
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uart_serial_lookup,
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&uart_serial_channel0);
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#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART0
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#if defined CYGPKG_IO_SERIAL_FREESCALE_UART1
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static const uart_pins_t uart1_pins = {
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rx : CYGHWR_IO_FREESCALE_UART1_PIN_RX,
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tx : CYGHWR_IO_FREESCALE_UART1_PIN_TX,
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rts : CYGHWR_IO_FREESCALE_UART1_PIN_RTS,
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cts : CYGHWR_IO_FREESCALE_UART1_PIN_CTS
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};
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static uart_serial_info uart_serial_info1 = {
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uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE,
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY,
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pins_p : &uart1_pins
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};
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#if CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE > 0
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static unsigned char
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uart_serial_out_buf1[CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE];
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static unsigned char
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uart_serial_in_buf1[CYGNUM_IO_SERIAL_FREESCALE_UART1_BUFSIZE];
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static
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SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel1,
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uart_serial_funs,
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uart_serial_info1,
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CYG_SERIAL_BAUD_RATE(
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CYGNUM_IO_SERIAL_FREESCALE_UART1_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT,
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&uart_serial_out_buf1[0],
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sizeof(uart_serial_out_buf1),
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&uart_serial_in_buf1[0],
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sizeof(uart_serial_in_buf1));
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#else
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static
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SERIAL_CHANNEL(uart_serial_channel1,
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uart_serial_funs,
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uart_serial_info1,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART1_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT);
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#endif
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DEVTAB_ENTRY(uart_serial_io1,
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CYGDAT_IO_SERIAL_FREESCALE_UART1_NAME,
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0, // does not depend on a lower level device driver
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&cyg_io_serial_devio,
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uart_serial_init,
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uart_serial_lookup,
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&uart_serial_channel1);
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#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART1
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#if defined CYGPKG_IO_SERIAL_FREESCALE_UART2
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static const uart_pins_t uart2_pins = {
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rx : CYGHWR_IO_FREESCALE_UART2_PIN_RX,
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tx : CYGHWR_IO_FREESCALE_UART2_PIN_TX,
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rts : CYGHWR_IO_FREESCALE_UART2_PIN_RTS,
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cts : CYGHWR_IO_FREESCALE_UART2_PIN_CTS
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};
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static uart_serial_info uart_serial_info2 = {
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uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE,
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY,
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pins_p : &uart2_pins
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};
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#if CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE > 0
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static unsigned char
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uart_serial_out_buf2[CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE];
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static unsigned char
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uart_serial_in_buf2[CYGNUM_IO_SERIAL_FREESCALE_UART2_BUFSIZE];
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static
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SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel2,
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uart_serial_funs,
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uart_serial_info2,
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CYG_SERIAL_BAUD_RATE(
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CYGNUM_IO_SERIAL_FREESCALE_UART2_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT,
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&uart_serial_out_buf2[0],
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sizeof(uart_serial_out_buf2),
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&uart_serial_in_buf2[0],
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sizeof(uart_serial_in_buf2));
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#else
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static
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SERIAL_CHANNEL(uart_serial_channel2,
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uart_serial_funs,
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uart_serial_info2,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART2_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT);
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#endif
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DEVTAB_ENTRY(uart_serial_io2,
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CYGDAT_IO_SERIAL_FREESCALE_UART2_NAME,
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0, // does not depend on a lower level device driver
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&cyg_io_serial_devio,
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uart_serial_init,
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uart_serial_lookup,
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&uart_serial_channel2);
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#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART2
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#if defined CYGPKG_IO_SERIAL_FREESCALE_UART3
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static const uart_pins_t uart3_pins = {
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rx : CYGHWR_IO_FREESCALE_UART3_PIN_RX,
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tx : CYGHWR_IO_FREESCALE_UART3_PIN_TX,
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rts : CYGHWR_IO_FREESCALE_UART3_PIN_RTS,
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cts : CYGHWR_IO_FREESCALE_UART3_PIN_CTS
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};
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static uart_serial_info uart_serial_info3 = {
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uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE,
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY,
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pins_p : &uart3_pins
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};
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#if CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE > 0
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static unsigned char
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uart_serial_out_buf3[CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE];
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static unsigned char
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uart_serial_in_buf3[CYGNUM_IO_SERIAL_FREESCALE_UART3_BUFSIZE];
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static
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SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel3,
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uart_serial_funs,
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uart_serial_info3,
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CYG_SERIAL_BAUD_RATE(
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CYGNUM_IO_SERIAL_FREESCALE_UART3_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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CYG_SERIAL_PARITY_DEFAULT,
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT,
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&uart_serial_out_buf3[0],
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sizeof(uart_serial_out_buf3),
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&uart_serial_in_buf3[0],
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sizeof(uart_serial_in_buf3));
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#else
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247 |
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static
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248 |
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SERIAL_CHANNEL(uart_serial_channel3,
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uart_serial_funs,
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uart_serial_info3,
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART3_BAUD),
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252 |
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CYG_SERIAL_STOP_DEFAULT,
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253 |
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CYG_SERIAL_PARITY_DEFAULT,
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254 |
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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CYG_SERIAL_FLAGS_DEFAULT);
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#endif
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257 |
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DEVTAB_ENTRY(uart_serial_io3,
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258 |
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CYGDAT_IO_SERIAL_FREESCALE_UART3_NAME,
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259 |
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0, // does not depend on a lower level device driver
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260 |
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&cyg_io_serial_devio,
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261 |
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uart_serial_init,
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262 |
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uart_serial_lookup,
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263 |
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&uart_serial_channel3);
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#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART3
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266 |
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267 |
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#if defined CYGPKG_IO_SERIAL_FREESCALE_UART4
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268 |
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static const uart_pins_t uart4_pins = {
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269 |
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rx : CYGHWR_IO_FREESCALE_UART4_PIN_RX,
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270 |
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tx : CYGHWR_IO_FREESCALE_UART4_PIN_TX,
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271 |
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rts : CYGHWR_IO_FREESCALE_UART4_PIN_RTS,
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272 |
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cts : CYGHWR_IO_FREESCALE_UART4_PIN_CTS
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};
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274 |
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static uart_serial_info uart_serial_info4 = {
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275 |
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uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE,
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276 |
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interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR,
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interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY,
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pins_p : &uart4_pins
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};
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280 |
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#if CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE > 0
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static unsigned char
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282 |
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uart_serial_out_buf4[CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE];
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283 |
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static unsigned char
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284 |
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uart_serial_in_buf4[CYGNUM_IO_SERIAL_FREESCALE_UART4_BUFSIZE];
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285 |
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286 |
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static
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287 |
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SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel4,
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uart_serial_funs,
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uart_serial_info4,
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CYG_SERIAL_BAUD_RATE(
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CYGNUM_IO_SERIAL_FREESCALE_UART4_BAUD),
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CYG_SERIAL_STOP_DEFAULT,
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293 |
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CYG_SERIAL_PARITY_DEFAULT,
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294 |
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CYG_SERIAL_WORD_LENGTH_DEFAULT,
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295 |
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CYG_SERIAL_FLAGS_DEFAULT,
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296 |
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&uart_serial_out_buf4[0],
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297 |
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sizeof(uart_serial_out_buf4),
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298 |
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&uart_serial_in_buf4[0],
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299 |
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sizeof(uart_serial_in_buf4));
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300 |
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#else
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301 |
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static
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302 |
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SERIAL_CHANNEL(uart_serial_channel4,
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303 |
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uart_serial_funs,
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304 |
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uart_serial_info4,
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305 |
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CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART4_BAUD),
|
306 |
|
|
CYG_SERIAL_STOP_DEFAULT,
|
307 |
|
|
CYG_SERIAL_PARITY_DEFAULT,
|
308 |
|
|
CYG_SERIAL_WORD_LENGTH_DEFAULT,
|
309 |
|
|
CYG_SERIAL_FLAGS_DEFAULT);
|
310 |
|
|
#endif
|
311 |
|
|
DEVTAB_ENTRY(uart_serial_io4,
|
312 |
|
|
CYGDAT_IO_SERIAL_FREESCALE_UART4_NAME,
|
313 |
|
|
0, // does not depend on a lower level device driver
|
314 |
|
|
&cyg_io_serial_devio,
|
315 |
|
|
uart_serial_init,
|
316 |
|
|
uart_serial_lookup,
|
317 |
|
|
&uart_serial_channel4);
|
318 |
|
|
#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART4
|
319 |
|
|
|
320 |
|
|
|
321 |
|
|
#if defined CYGPKG_IO_SERIAL_FREESCALE_UART5
|
322 |
|
|
static const uart_pins_t uart5_pins = {
|
323 |
|
|
rx : CYGHWR_IO_FREESCALE_UART5_PIN_RX,
|
324 |
|
|
tx : CYGHWR_IO_FREESCALE_UART5_PIN_TX,
|
325 |
|
|
rts : CYGHWR_IO_FREESCALE_UART5_PIN_RTS,
|
326 |
|
|
cts : CYGHWR_IO_FREESCALE_UART5_PIN_CTS
|
327 |
|
|
};
|
328 |
|
|
static uart_serial_info uart_serial_info5 = {
|
329 |
|
|
uart_base : CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE,
|
330 |
|
|
interrupt_num : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR,
|
331 |
|
|
interrupt_priority : CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY,
|
332 |
|
|
pins_p : &uart5_pins
|
333 |
|
|
};
|
334 |
|
|
#if CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE > 0
|
335 |
|
|
static unsigned char
|
336 |
|
|
uart_serial_out_buf5[CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE];
|
337 |
|
|
static unsigned char
|
338 |
|
|
uart_serial_in_buf5[CYGNUM_IO_SERIAL_FREESCALE_UART5_BUFSIZE];
|
339 |
|
|
|
340 |
|
|
static
|
341 |
|
|
SERIAL_CHANNEL_USING_INTERRUPTS(uart_serial_channel5,
|
342 |
|
|
uart_serial_funs,
|
343 |
|
|
uart_serial_info5,
|
344 |
|
|
CYG_SERIAL_BAUD_RATE(
|
345 |
|
|
CYGNUM_IO_SERIAL_FREESCALE_UART5_BAUD),
|
346 |
|
|
CYG_SERIAL_STOP_DEFAULT,
|
347 |
|
|
CYG_SERIAL_PARITY_DEFAULT,
|
348 |
|
|
CYG_SERIAL_WORD_LENGTH_DEFAULT,
|
349 |
|
|
CYG_SERIAL_FLAGS_DEFAULT,
|
350 |
|
|
&uart_serial_out_buf5[0],
|
351 |
|
|
sizeof(uart_serial_out_buf5),
|
352 |
|
|
&uart_serial_in_buf5[0],
|
353 |
|
|
sizeof(uart_serial_in_buf5));
|
354 |
|
|
#else
|
355 |
|
|
static
|
356 |
|
|
SERIAL_CHANNEL(uart_serial_channel5,
|
357 |
|
|
uart_serial_funs,
|
358 |
|
|
uart_serial_info5,
|
359 |
|
|
CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_FREESCALE_UART5_BAUD),
|
360 |
|
|
CYG_SERIAL_STOP_DEFAULT,
|
361 |
|
|
CYG_SERIAL_PARITY_DEFAULT,
|
362 |
|
|
CYG_SERIAL_WORD_LENGTH_DEFAULT,
|
363 |
|
|
CYG_SERIAL_FLAGS_DEFAULT);
|
364 |
|
|
#endif
|
365 |
|
|
DEVTAB_ENTRY(uart_serial_io5,
|
366 |
|
|
CYGDAT_IO_SERIAL_FREESCALE_UART5_NAME,
|
367 |
|
|
0, // does not depend on a lower level device driver
|
368 |
|
|
&cyg_io_serial_devio,
|
369 |
|
|
uart_serial_init,
|
370 |
|
|
uart_serial_lookup,
|
371 |
|
|
&uart_serial_channel5);
|
372 |
|
|
#endif // ifdef CYGPKG_IO_SERIAL_FREESCALE_UART5
|