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skrzyp |
//==========================================================================
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//
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// ser_freescale_uart.c
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//
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// Freescale UART Serial I/O Interface Module (interrupt driven)
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2011 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Ilija Kocho <ilijak@siva.com.mk>
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// Contributors:
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// Date: 2011-02-10
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// Purpose: Freescale UART Serial I/O module (interrupt driven version)
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// Description:
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//
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//
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//####DESCRIPTIONEND####
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//==========================================================================
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#include <pkgconf/io_serial.h>
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#include <pkgconf/io.h>
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#include <cyg/io/io.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/hal_arbiter.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/io/devtab.h>
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#include <cyg/infra/diag.h>
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#include <cyg/io/serial.h>
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#include <cyg/io/ser_freescale_uart.h>
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// Only build this driver for if Freescale UART is needed.
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#ifdef CYGPKG_IO_SERIAL_FREESCALE_UART
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typedef struct uart_pins_s {
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cyg_uint32 rx;
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cyg_uint32 tx;
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cyg_uint32 rts;
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cyg_uint32 cts;
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} uart_pins_t;
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typedef struct uart_serial_info {
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CYG_ADDRWORD uart_base; // Base address of the uart port
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CYG_WORD interrupt_num; // NVIC interrupt vector
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cyg_priority_t interrupt_priority; // NVIC interupt priority
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const uart_pins_t *pins_p;
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cyg_bool tx_active;
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cyg_interrupt interrupt_obj; // Interrupt object
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cyg_handle_t interrupt_handle; // Interrupt handle
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} uart_serial_info;
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static bool uart_serial_init(struct cyg_devtab_entry * tab);
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static bool uart_serial_putc(serial_channel * chan, unsigned char c);
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static Cyg_ErrNo uart_serial_lookup(struct cyg_devtab_entry ** tab,
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struct cyg_devtab_entry * sub_tab,
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const char * name);
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static unsigned char uart_serial_getc(serial_channel *chan);
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static Cyg_ErrNo uart_serial_set_config(serial_channel *chan, cyg_uint32 key,
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const void *xbuf, cyg_uint32 *len);
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static void uart_serial_start_xmit(serial_channel *chan);
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static void uart_serial_stop_xmit(serial_channel *chan);
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// Interrupt servers
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static cyg_uint32 uart_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
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static void uart_serial_DSR(cyg_vector_t vector, cyg_ucount32 count,
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cyg_addrword_t data);
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static SERIAL_FUNS(uart_serial_funs,
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uart_serial_putc,
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uart_serial_getc,
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uart_serial_set_config,
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uart_serial_start_xmit,
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uart_serial_stop_xmit);
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// Available baud rates
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static cyg_int32 select_baud[] = {
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0, // Unused
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50, // 50
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75, // 75
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110, // 110
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0, // 134.5
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150, // 150
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200, // 200
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300, // 300
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600, // 600
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1200, // 1200
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1800, // 1800
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2400, // 2400
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3600, // 3600
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4800, // 4800
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7200, // 7200
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9600, // 9600
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14400, // 14400
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19200, // 19200
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38400, // 38400
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57600, // 57600
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115200, // 115200
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230400, // 230400
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};
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#include <cyg/io/ser_freescale_uart_chan.inl>
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//----------------------------------------------------------------------------
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// Internal function to actually configure the hardware to desired
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// baud rate, etc.
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//----------------------------------------------------------------------------
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static bool
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uart_serial_config_port(serial_channel * chan, cyg_serial_info_t * new_config,
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bool init)
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{
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cyg_uint32 regval;
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uart_serial_info * uart_chan = (uart_serial_info *)(chan->dev_priv);
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cyg_addrword_t uart_base = uart_chan->uart_base;
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cyg_uint32 baud_rate = select_baud[new_config->baud];
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if(!baud_rate) return false; // Invalid baud rate selected
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// Configure PORT pins
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CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->rx);
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CYGHWR_IO_FREESCALE_UART_PIN(uart_chan->pins_p->tx);
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CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_base, baud_rate);
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if(new_config->word_length != 8)
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return false;
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switch(new_config->parity) {
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case CYGNUM_SERIAL_PARITY_NONE:
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regval = 0;
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break;
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case CYGNUM_SERIAL_PARITY_EVEN:
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regval = CYGHWR_DEV_FREESCALE_UART_C1_PE;
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break;
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case CYGNUM_SERIAL_PARITY_ODD:
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regval = CYGHWR_DEV_FREESCALE_UART_C1_PE |
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CYGHWR_DEV_FREESCALE_UART_C1_PT;
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break;
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default: return false;
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}
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HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C1, regval);
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if(init) { // Enable the receiver interrupt
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regval = CYGHWR_DEV_FREESCALE_UART_C2_RIE;
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} else { // Restore the old interrupt state
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HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, regval);
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}
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// Enable the device
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regval |= CYGHWR_DEV_FREESCALE_UART_C2_TE |
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CYGHWR_DEV_FREESCALE_UART_C2_RE;
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HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, regval);
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uart_chan->tx_active = false;
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if(new_config != &chan->config)
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chan->config = *new_config;
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return true;
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}
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//--------------------------------------------------------------
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// Function to initialize the device. Called at bootstrap time.
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//--------------------------------------------------------------
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static bool
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uart_serial_init(struct cyg_devtab_entry * tab)
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{
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serial_channel * chan = (serial_channel *)tab->priv;
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uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
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// Really only required for interrupt driven devices
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(chan->callbacks->serial_init)(chan);
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if(chan->out_cbuf.len != 0) {
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cyg_drv_interrupt_create(uart_chan->interrupt_num,
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uart_chan->interrupt_priority,
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// Data item passed to interrupt handler
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(cyg_addrword_t)chan,
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uart_serial_ISR,
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uart_serial_DSR,
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&uart_chan->interrupt_handle,
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&uart_chan->interrupt_obj);
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cyg_drv_interrupt_attach(uart_chan->interrupt_handle);
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cyg_drv_interrupt_unmask(uart_chan->interrupt_num);
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}
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return uart_serial_config_port(chan, &chan->config, true);
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}
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//----------------------------------------------------------------------
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// This routine is called when the device is "looked" up (i.e. attached)
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//----------------------------------------------------------------------
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static Cyg_ErrNo
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uart_serial_lookup(struct cyg_devtab_entry ** tab,
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struct cyg_devtab_entry * sub_tab, const char * name)
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{
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serial_channel * chan = (serial_channel *)(*tab)->priv;
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// Really only required for interrupt driven devices
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(chan->callbacks->serial_init)(chan);
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return ENOERR;
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}
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//-----------------------------------------------------------------
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// Send a character to Tx
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//-----------------------------------------------------------------
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| 240 |
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static bool
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uart_serial_putc(serial_channel * chan, unsigned char ch_out)
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{
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uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
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cyg_addrword_t uart_base = uart_chan->uart_base;
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cyg_uint32 uart_sr;
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HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr);
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if(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_TDRE) {
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HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, ch_out);
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return true;
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| 251 |
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} else {
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| 252 |
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return false;
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| 253 |
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}
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| 254 |
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}
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| 255 |
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//---------------------------------------------------------------------
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| 258 |
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// Fetch a character Rx (for polled operation only)
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| 259 |
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//---------------------------------------------------------------------
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| 260 |
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static unsigned char
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| 261 |
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uart_serial_getc(serial_channel * chan)
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| 262 |
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{
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| 263 |
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cyg_uint8 ch_in;
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| 264 |
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uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
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| 265 |
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cyg_addrword_t uart_base = uart_chan->uart_base;
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| 266 |
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| 267 |
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cyg_uint32 uart_sr;
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| 268 |
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| 269 |
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do {
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| 270 |
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HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr);
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| 271 |
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} while(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_RDRF);
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| 272 |
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| 273 |
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HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, ch_in);
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| 274 |
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| 275 |
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return ch_in;
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| 276 |
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}
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| 277 |
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| 278 |
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| 279 |
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//---------------------------------------------------
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| 280 |
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// Set up the device characteristics; baud rate, etc.
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| 281 |
|
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//---------------------------------------------------
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| 282 |
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static bool
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| 283 |
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uart_serial_set_config(serial_channel * chan, cyg_uint32 key,
|
| 284 |
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const void *xbuf, cyg_uint32 * len)
|
| 285 |
|
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{
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| 286 |
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switch(key) {
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| 287 |
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case CYG_IO_SET_CONFIG_SERIAL_INFO: {
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| 288 |
|
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cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
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| 289 |
|
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if(*len < sizeof(cyg_serial_info_t)) {
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| 290 |
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return -EINVAL;
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| 291 |
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}
|
| 292 |
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*len = sizeof(cyg_serial_info_t);
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| 293 |
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if(true != uart_serial_config_port(chan, config, false))
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| 294 |
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return -EINVAL;
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| 295 |
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}
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| 296 |
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break;
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| 297 |
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default:
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| 298 |
|
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return -EINVAL;
|
| 299 |
|
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}
|
| 300 |
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return ENOERR;
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| 301 |
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}
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| 302 |
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|
| 303 |
|
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//-------------------------------------
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| 304 |
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// Enable the transmitter on the device
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| 305 |
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//-------------------------------------
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| 306 |
|
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static void uart_serial_start_xmit(serial_channel * chan)
|
| 307 |
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{
|
| 308 |
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uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
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| 309 |
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cyg_addrword_t uart_base = uart_chan->uart_base;
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| 310 |
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cyg_uint32 uart_cr12;
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| 311 |
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| 312 |
|
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if(!uart_chan->tx_active) {
|
| 313 |
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uart_chan->tx_active = true;
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| 314 |
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HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12);
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| 315 |
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uart_cr12 |= CYGHWR_DEV_FREESCALE_UART_C2_TIE;
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| 316 |
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HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12);
|
| 317 |
|
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}
|
| 318 |
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}
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| 319 |
|
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|
| 320 |
|
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//--------------------------------------
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| 321 |
|
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// Disable the transmitter on the device
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| 322 |
|
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//--------------------------------------
|
| 323 |
|
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static void uart_serial_stop_xmit(serial_channel * chan)
|
| 324 |
|
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{
|
| 325 |
|
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uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
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| 326 |
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|
| 327 |
|
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cyg_addrword_t uart_base = uart_chan->uart_base;
|
| 328 |
|
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cyg_uint32 uart_cr12;
|
| 329 |
|
|
|
| 330 |
|
|
if(uart_chan->tx_active) {
|
| 331 |
|
|
uart_chan->tx_active = false;
|
| 332 |
|
|
HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12);
|
| 333 |
|
|
uart_cr12 &= ~CYGHWR_DEV_FREESCALE_UART_C2_TIE;
|
| 334 |
|
|
HAL_WRITE_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_C2, uart_cr12);
|
| 335 |
|
|
}
|
| 336 |
|
|
}
|
| 337 |
|
|
|
| 338 |
|
|
//-----------------------------------------
|
| 339 |
|
|
// The low level interrupt handler
|
| 340 |
|
|
//-----------------------------------------
|
| 341 |
|
|
static
|
| 342 |
|
|
cyg_uint32 uart_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
|
| 343 |
|
|
{
|
| 344 |
|
|
serial_channel * chan = (serial_channel *)data;
|
| 345 |
|
|
uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
|
| 346 |
|
|
|
| 347 |
|
|
cyg_drv_interrupt_mask(uart_chan->interrupt_num);
|
| 348 |
|
|
cyg_drv_interrupt_acknowledge(uart_chan->interrupt_num);
|
| 349 |
|
|
|
| 350 |
|
|
return CYG_ISR_CALL_DSR; // cause the DSR to run
|
| 351 |
|
|
}
|
| 352 |
|
|
|
| 353 |
|
|
|
| 354 |
|
|
//------------------------------------------
|
| 355 |
|
|
// The high level interrupt handler
|
| 356 |
|
|
//------------------------------------------
|
| 357 |
|
|
|
| 358 |
|
|
#define CYGHWR_DEV_FREESCALE_UART_S1_ERRORS \
|
| 359 |
|
|
(CYGHWR_DEV_FREESCALE_UART_S1_OR | \
|
| 360 |
|
|
CYGHWR_DEV_FREESCALE_UART_S1_NF | \
|
| 361 |
|
|
CYGHWR_DEV_FREESCALE_UART_S1_FE | \
|
| 362 |
|
|
CYGHWR_DEV_FREESCALE_UART_S1_PF)
|
| 363 |
|
|
|
| 364 |
|
|
static void
|
| 365 |
|
|
uart_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
|
| 366 |
|
|
{
|
| 367 |
|
|
serial_channel * chan = (serial_channel *)data;
|
| 368 |
|
|
uart_serial_info * uart_chan = (uart_serial_info *)chan->dev_priv;
|
| 369 |
|
|
cyg_addrword_t uart_base = uart_chan->uart_base;
|
| 370 |
|
|
volatile cyg_uint32 uart_sr;
|
| 371 |
|
|
cyg_uint8 uart_dr;
|
| 372 |
|
|
|
| 373 |
|
|
HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_S1, uart_sr);
|
| 374 |
|
|
if(uart_sr & (CYGHWR_DEV_FREESCALE_UART_S1_RDRF |
|
| 375 |
|
|
CYGHWR_DEV_FREESCALE_UART_S1_ERRORS)) {
|
| 376 |
|
|
// Receiver full or errors
|
| 377 |
|
|
HAL_READ_UINT8(uart_base + CYGHWR_DEV_FREESCALE_UART_D, uart_dr);
|
| 378 |
|
|
if(uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_ERRORS) {
|
| 379 |
|
|
// Check for receive error
|
| 380 |
|
|
} else { // No errors, get the character
|
| 381 |
|
|
(chan->callbacks->rcv_char)(chan, (cyg_uint8)uart_dr);
|
| 382 |
|
|
}
|
| 383 |
|
|
}
|
| 384 |
|
|
|
| 385 |
|
|
if(uart_chan->tx_active && (uart_sr & CYGHWR_DEV_FREESCALE_UART_S1_TDRE)){
|
| 386 |
|
|
//Transmitter empty
|
| 387 |
|
|
(chan->callbacks->xmt_char)(chan);
|
| 388 |
|
|
}
|
| 389 |
|
|
|
| 390 |
|
|
cyg_drv_interrupt_unmask(uart_chan->interrupt_num);
|
| 391 |
|
|
}
|
| 392 |
|
|
|
| 393 |
|
|
#endif // CYGPKG_IO_SERIAL_FREESCALE_UART
|
| 394 |
|
|
// EOF ser_freescale_uart.c
|
