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//=============================================================================

//

//      spi_freescale_dspi.c

//

//      SPI driver implementation for Freescale DSPI

//

//=============================================================================

// ####ECOSGPLCOPYRIGHTBEGIN####                                            

// -------------------------------------------                              

// This file is part of eCos, the Embedded Configurable Operating System.   

// Copyright (C) 2011 Free Software Foundation, Inc.

//

// eCos is free software; you can redistribute it and/or modify it under    

// the terms of the GNU General Public License as published by the Free     

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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    

// for more details.                                                        

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// You should have received a copy of the GNU General Public License        

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//

// As a special exception, if other files instantiate templates or use      

// macros or inline functions from this file, or you compile this file      

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// General Public License v2.                                               

//

// This exception does not invalidate any other reasons why a work based    

// on this file might be covered by the GNU General Public License.         

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// ####ECOSGPLCOPYRIGHTEND####                                              

//=============================================================================

//#####DESCRIPTIONBEGIN####

//

// Author(s):   ilijak

// Date:        2011-11-04

// Purpose:     Freescale DSPI SPI driver implementation

//

//####DESCRIPTIONEND####

//

//=============================================================================

#include <string.h>

#include <cyg/hal/hal_io.h>

#include <cyg/hal/hal_if.h>

#include <cyg/hal/hal_intr.h>

#include <cyg/hal/drv_api.h>

#include <cyg/infra/cyg_type.h>

#include <cyg/infra/cyg_ass.h>

#include <cyg/infra/diag.h>

#include <cyg/io/spi.h>

#include <cyg/hal/hal_endian.h>

#include <pkgconf/devs_spi_freescale_dspi.h>

#if defined(CYGHWR_DEVS_SPI_FREESCALE_DSPI0) || \

    defined(CYGHWR_DEVS_SPI_FREESCALE_DSPI1) || \

    defined(CYGHWR_DEVS_SPI_FREESCALE_DSPI2)

#include <cyg/io/spi_freescale_dspi.h>

#define DEBUG_SPI CYGPKG_DEVS_SPI_FREESCALE_DSPI_DEBUG_LEVEL

#if DEBUG_SPI >= 3

# define DEBUG3_PRINTF(args...) diag_printf(args)

#else

# define DEBUG3_PRINTF(args...)

#endif

#if DEBUG_SPI >= 2

# define DEBUG2_PRINTF(args...) diag_printf(args)

#else

# define DEBUG2_PRINTF(args...)

#endif

#if DEBUG_SPI >= 1

# define DEBUG1_PRINTF(args...) diag_printf(args)

#else

# define DEBUG1_PRINTF(args...)

#endif

# define DEBUG0_PRINTF(args...) diag_printf(args)

//-----------------------------------------------------------------------------

// API function call forward references.

static void dspi_transaction_begin    (cyg_spi_device*);

static void dspi_transaction_transfer (cyg_spi_device*, cyg_bool, cyg_uint32,

                                       const cyg_uint8*, cyg_uint8*, cyg_bool);

static void dspi_transaction_tick     (cyg_spi_device*, cyg_bool, cyg_uint32);

static void dspi_transaction_end      (cyg_spi_device*);

static int  dspi_get_config           (cyg_spi_device*, cyg_uint32,

                                       void*, cyg_uint32*);

static int  dspi_set_config           (cyg_spi_device*, cyg_uint32,

                                       const void*, cyg_uint32*);

//-----------------------------------------------------------------------------

// Instantiate the bus state data structures.

#include <cyg/io/spi_freescale_dspi_buses.inl>

// Some hardware manipulation inline functions and macros

static inline void dspi_disable(cyghwr_devs_freescale_dspi_t* dspi_p)

{

    dspi_p->mcr |=  FREESCALE_DSPI_MCR_MDIS_M;

}

static inline void dspi_enable(cyghwr_devs_freescale_dspi_t* dspi_p)

{

    dspi_p->mcr &=  ~FREESCALE_DSPI_MCR_MDIS_M;

}

static inline void dspi_halt(cyghwr_devs_freescale_dspi_t* dspi_p)

{

    dspi_p->mcr |=  FREESCALE_DSPI_MCR_HALT_M;

}

static inline void dspi_tlah(cyghwr_devs_freescale_dspi_t* dspi_p)

{

    dspi_p->mcr &=  ~FREESCALE_DSPI_MCR_HALT_M;

}

static inline void

dspi_irq_enable(cyghwr_devs_freescale_dspi_t* dspi_p, cyg_uint32 irq_mask)

{

    dspi_p->rser |= irq_mask;

}

static inline void

dspi_irq_disable(cyghwr_devs_freescale_dspi_t* dspi_p, cyg_uint32 irq_mask)

{

    dspi_p->rser &= ~irq_mask;

}

static inline void

dspi_status_clear(cyghwr_devs_freescale_dspi_t* dspi_p, cyg_uint32 sr_mask)

{

    dspi_p->sr |= sr_mask;

}

static inline void

dspi_fifo_clear(cyghwr_devs_freescale_dspi_t* dspi_p)

{

    dspi_p->mcr |= FREESCALE_DSPI_MCR_CLR_RXF_M | FREESCALE_DSPI_MCR_CLR_TXF_M;

}

static inline void

dspi_fifo_drain(cyghwr_devs_freescale_dspi_t* dspi_p)

{

    dspi_p->sr |= FREESCALE_DSPI_SR_RFDF_M;

}

#define DSPI_IRQ_ENABLE(__dspi_p) \

        dspi_irq_enable(__dspi_p, FREESCALE_DSPI_RSER_EOQF_RE_M)

#define DSPI_IRQ_DISABLE(__dspi_p) \

        dspi_irq_disable(__dspi_p, FREESCALE_DSPI_RSER_EOQF_RE_M)

#define DSPI_EOQ_CLEAR(__dspi_p) \

        dspi_status_clear(__dspi_p, FREESCALE_DSPI_SR_EOQF_M | \

                                     FREESCALE_DSPI_SR_TCF_M | \

                                        FREESCALE_DSPI_SR_RFDF_M)

#define DSPI_TXRX_ENABLE(__dspi_p) \

        dspi_status_clear(__dspi_p, FREESCALE_DSPI_SR_TXRXS_M)

// Alternate clocking for spi_transaction_end()

// Used to initialize CTAR1.

static const cyg_freescale_dspi_clocking_t aux_clocking =

{

    .frame_size = 4,

    .cl_pol = 0,

    .cl_pha = 0,

    .cl_brate = CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_SPEED,

    .cs_up_udly = CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_CS_DELAY,

    .cs_dw_udly = CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_CS_DELAY,

    .tr_bt_udly =CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_CS_DELAY,

    .dl_unit = CYGNUM_DSPI_DELAY_UNIT(

                   CYGHWR_DEVS_FREESCALE_DSPI_DSPI_CTAR1_AUX_DELAY_UNIT),

    .cl_dbr = CYGHWR_DEVS_FREESCALEDSPI_DSPI_CTAR1_AUX_USE_DBR

};

//-----------------------------------------------------------------------------

// Implement DSPI ISRs.

// ISR for DSPI with DMA

// Disable DSPI IRQ and Tx DMA channel and schedule DSR.

static cyg_uint32 dspi_dma_ISR(cyg_vector_t vector, cyg_addrword_t data)

{

    cyg_spi_freescale_dspi_bus_t* dspi_bus_p =

          (cyg_spi_freescale_dspi_bus_t*) data;

    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus_p->setup_p->dspi_p;

    cyghwr_hal_freescale_dma_set_t *dma_set_p = dspi_bus_p->setup_p->dma_set_p;

    cyghwr_hal_freescale_edma_t *edma_p;

    edma_p = dma_set_p->edma_p;

    cyg_drv_isr_lock();

    // Disable the Tx DMA channel and DSPI IRQ.

    hal_freescale_edma_erq_disable(edma_p, SPI_DMA_CHAN_I(dma_set_p, TX));

    DSPI_IRQ_DISABLE(dspi_p);

    cyg_drv_interrupt_acknowledge(vector);

    cyg_drv_isr_unlock();

    return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);

}

// ISR for DSPI without DMA

// Disable DSPI IRQ and schedule DSR.

static cyg_uint32 dspi_nodma_ISR(cyg_vector_t vector, cyg_addrword_t data)

{

    cyg_spi_freescale_dspi_bus_t* dspi_bus_p =

          (cyg_spi_freescale_dspi_bus_t*) data;

    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus_p->setup_p->dspi_p;

    cyg_drv_isr_lock();

    // Disable the DSPI IRQ.

    DSPI_IRQ_DISABLE(dspi_p);

    cyg_drv_interrupt_acknowledge(vector);

    cyg_drv_isr_unlock();

    return (CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);

}

// DSPI DSR

static void dspi_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)

{

    cyg_spi_freescale_dspi_bus_t* dspi_bus = (cyg_spi_freescale_dspi_bus_t*) data;

    cyg_drv_dsr_lock();

    cyg_drv_cond_signal(&dspi_bus->transfer_done);

    cyg_drv_dsr_unlock();

}

//-----------------------------------------------------------------------------

// Calculate best fit CTAR baud rate setting (using some brute force).

// Best fit is considered the highest frequency that is not highe than set point.

static const cyg_uint16 ctar_br[16] = { 2/2, 4/2, 6/2, 8/2, 16/2, 32/2, 64/2,

    128/2, 256/2, 512/2, 1024/2, 2048/2, 4096/2, 8192/2, 16384/2, 32768/2 };

static const cyg_uint8 ctar_pbr[4] = { 2, 3, 5, 7 };

static const cyg_uint16 ctar_cssck[16] = { 2/2, 4/2, 8/2, 16/2, 32/2, 64/2,

    128/2, 256/2, 512/2, 1024/2, 2048/2, 4096/2, 8192/2, 16384/2, 32768/2,

    65536/2 };

static const cyg_uint8 ctar_pcssck[4] = { 1, 3, 5, 7 };

typedef struct ctar_br_s {

    cyg_uint8 valid;

    cyg_uint8 br;

    cyg_uint8 dbr;

    cyg_uint8 pbr;

} ctar_br_t;

static int dspi_ctar_brbf (const cyg_freescale_dspi_clocking_t* spi_cocking,

                              ctar_br_t* brs_p, const cyg_uint16* br_p,

                              const cyg_uint8* pbr_p, cyg_uint32* alt_brate,

                              cyg_uint32 sys_clk)

{

    cyg_uint32 pbr_i;

    cyg_uint32 br_i;

    cyg_uint32 dbr;

    cyg_uint32 clk;

    cyg_uint32 baud_bf = 0; // Best fit

    cyg_uint32 baud_tmp;

    cyg_uint32 baud_sp = alt_brate ? *alt_brate :

                         spi_cocking->cl_brate; // Set point

    // Calculate the maximal viable bus speed.

    clk = sys_clk;

     // Desired baud rate very high, use DBR if allowed

    dbr = (baud_sp > (clk / 4)) && spi_cocking->cl_dbr && (br_p == ctar_br);

    for(pbr_i = 0; pbr_i < 3; pbr_i++) {

        for(br_i = 0; br_i < 15; br_i++) {

            if((baud_tmp = (clk * (1+dbr)) / (pbr_p[pbr_i] * (2*br_p[br_i])))

               <= baud_sp)

            {

                if(baud_tmp > baud_bf) {

                    DEBUG3_PRINTF("DSPI Baud:"

                                  " SP=%d pbr=0x%x br=0x%x dbr=%d Temp=%d (SysClk=%d)\n",

                                  baud_sp, pbr_i, br_i, dbr, baud_tmp, clk);

                    brs_p->br = br_i;

                    brs_p->pbr = pbr_i;

                    brs_p->valid = 1;

                    baud_bf = baud_tmp;

                    if(baud_tmp == baud_sp)

                        goto baud_found;

                }

            }

        }

    }

    if(!brs_p->valid) {

        pbr_i = 3;

        br_i = 15;

        DEBUG1_PRINTF("DSPI Baud too low:"

                      " SP=%d pbr=0x%x br=0x%x Actual=%d (SysClk=%d)\n",

                      baud_sp, pbr_i, br_i,

                      (clk * (1+dbr)) / (pbr_p[pbr_i] * (2*br_p[br_i])), clk);

        brs_p->br = br_i;

        brs_p->pbr = pbr_i;

        return -1;

    } else {

baud_found:

        brs_p->dbr = dbr;

        DEBUG1_PRINTF("DSPI Baud found:"

                      " SP=%d pbr=0x%x br=0x%x dbr=%d Actual=%dHz (%dns) (SysClk=%d)\n",

                      baud_sp, brs_p->pbr, brs_p->br, dbr, baud_bf, 1000000000/baud_bf, clk);

        return 0;

    }

}

// Set Clock and Transfer Attributes Register

#define CYG_ASSERT_LOW_FREQ \

   CYG_ASSERT (false, "Freescale DSPI: Cannot run bus as slowly as requested.")

cyg_uint32

dspi_calc_ctar(const cyg_freescale_dspi_clocking_t* spi_clocking, cyg_uint32 sys_clk)

{

    cyg_uint32 regval;

    ctar_br_t brs;

    cyg_uint32 delay_brate;

    regval = FREESCALE_DSPI_CTAR_FMSZ(spi_clocking->frame_size - 1);

    if(spi_clocking->cl_pol)

        regval |= FREESCALE_DSPI_CTAR_SLAVE_CPOL_M;

    if(spi_clocking->cl_pha)

        regval |= FREESCALE_DSPI_CTAR_SLAVE_CPHA_M;

    if(spi_clocking->lsb_first)

        regval |= FREESCALE_DSPI_CTAR_LSBFE_M;

    // Get divider bits

    // Baud rate

    brs.dbr = 0;

    if (!dspi_ctar_brbf(spi_clocking, &brs, ctar_br, ctar_pbr, NULL, sys_clk))

    {

        regval |= FREESCALE_DSPI_CTAR_BR(brs.br) |

              FREESCALE_DSPI_CTAR_PBR(brs.pbr) |

              (brs.dbr ? FREESCALE_DSPI_CTAR_DBR_M : 0);

    } else

        CYG_ASSERT_LOW_FREQ;

    delay_brate = 100000000 / (spi_clocking->dl_unit * spi_clocking->cs_up_udly);

    if (!dspi_ctar_brbf(spi_clocking, &brs, ctar_cssck, ctar_pcssck,

                           &delay_brate, sys_clk))

    {

        regval |= FREESCALE_DSPI_CTAR_CSSCK(brs.br) |

              FREESCALE_DSPI_CTAR_PCSSCK(brs.pbr);

    } else

        CYG_ASSERT_LOW_FREQ;

    // Delay between clock and CS negation

    delay_brate = 100000000 / (spi_clocking->dl_unit * spi_clocking->cs_dw_udly);

    if (!dspi_ctar_brbf(spi_clocking, &brs, ctar_cssck, ctar_pcssck,

                           &delay_brate, sys_clk))

    {

        regval |= FREESCALE_DSPI_CTAR_ASC(brs.br) |

              FREESCALE_DSPI_CTAR_PASC(brs.pbr);

    } else

        CYG_ASSERT_LOW_FREQ;

    // Delay between clock and CS negation and assertion

    delay_brate = 100000000 / (spi_clocking->dl_unit * spi_clocking->tr_bt_udly);

    if (!dspi_ctar_brbf(spi_clocking, &brs, ctar_cssck, ctar_pcssck,

                           &delay_brate, sys_clk))

    {

        regval |= FREESCALE_DSPI_CTAR_DT(brs.br) |

              FREESCALE_DSPI_CTAR_PDT(brs.pbr);

    } else

        CYG_ASSERT_LOW_FREQ;

    return regval;

}

//----------------------------------------------------------------------------

//Set up SPI bus pins

static void dspi_pin_setup(const cyg_uint32* spi_pins_p,

                           const cyg_uint32* cs_pins_p, cyg_uint32 cs_pin_n)

{

    const cyg_uint32* pin_p;

    for(pin_p = spi_pins_p;

        pin_p < spi_pins_p + 3;

        CYGHWR_IO_FREESCALE_DSPI_PIN(*pin_p++));

    for(pin_p = cs_pins_p;

        pin_p < cs_pins_p + cs_pin_n;

        CYGHWR_IO_FREESCALE_DSPI_PIN(*pin_p++));

}

//-----------------------------------------------------------------------------

// Set up a new SPI bus on initialisation.

static void dspi_bus_setup(cyg_spi_freescale_dspi_bus_t* spi_bus_p)

{

    cyghwr_devs_freescale_dspi_t* dspi_p = spi_bus_p->setup_p->dspi_p;

    cyghwr_hal_freescale_dma_set_t* dma_set_p;

    cyghwr_hal_freescale_edma_t* edma_p;

    cyg_uint32 dma_chan_i;

    // Get the clock frequency from HAL.

    spi_bus_p->clock_freq = CYGHWR_IO_SPI_FREESCALE_DSPI_CLOCK;

    DEBUG1_PRINTF("DSPI BUS %p: SysClk=%d\n", spi_bus_p, spi_bus_p->clock_freq);

    // Set up the pins.

    dspi_pin_setup(spi_bus_p->setup_p->spi_pin_list_p,

                   spi_bus_p->setup_p->cs_pin_list_p,

                   spi_bus_p->setup_p->cs_pin_num);

    // Set up default SPI configuration.

    dspi_p->mcr = spi_bus_p->setup_p->mcr_opt | FREESCALE_DSPI_MCR_MSTR_M |

          FREESCALE_DSPI_MCR_CLR_RXF_M | FREESCALE_DSPI_MCR_CLR_TXF_M |

          FREESCALE_DSPI_MCR_MDIS_M;

    // Enable DSPI controller.

    dspi_enable(dspi_p);

    if((dma_set_p=spi_bus_p->setup_p->dma_set_p)) {

        // Initialize DMA channels

        hal_freescale_edma_init_chanset(dma_set_p);

#if DEBUG_SPI >= 1

        hal_freescale_edma_diag(dma_set_p, 0xffff);

        cyghwr_devs_freescale_dspi_diag(spi_bus_p);

#endif

        // Set up DMA transfer control descriptors

        edma_p = dma_set_p->edma_p;

        dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_TX_I].dma_chan_i;

        hal_freescale_edma_transfer_init(edma_p, dma_chan_i,

                                         spi_bus_p->tx_dma_tcd_ini_p);

#if DEBUG_SPI >= 1

        hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);

#endif

        dma_chan_i = dma_set_p->chan_p[SPI_DMA_CHAN_RX_I].dma_chan_i;

        hal_freescale_edma_transfer_init(edma_p, dma_chan_i,

                                         spi_bus_p->rx_dma_tcd_ini_p);

#if DEBUG_SPI >= 1

        hal_freescale_edma_transfer_diag(edma_p, dma_chan_i, true);

#endif

        // Enable SPI DMA requests

        dspi_p->rser = FREESCALE_DSPI_RSER_TFFF_DIRS_M |

                       FREESCALE_DSPI_RSER_RFDF_DIRS_M |

                       FREESCALE_DSPI_RSER_TFFF_RE_M |

                       FREESCALE_DSPI_RSER_RFDF_RE_M;

    }

#if DEBUG_SPI >= 1

    cyghwr_devs_freescale_dspi_diag(spi_bus_p);

#endif

    // Initialise the synchronisation primitivies.

    cyg_drv_mutex_init (&spi_bus_p->transfer_mutex);

    cyg_drv_cond_init (&spi_bus_p->transfer_done, &spi_bus_p->transfer_mutex);

    // Hook up the ISR and DSR.

    cyg_drv_interrupt_create (spi_bus_p->setup_p->intr_num,

                              spi_bus_p->setup_p->intr_prio,

                              (cyg_addrword_t) spi_bus_p,

                              dma_set_p ? dspi_dma_ISR : dspi_nodma_ISR,

                              dspi_DSR, &spi_bus_p->intr_handle,

                              &spi_bus_p->intr_data);

    cyg_drv_interrupt_attach (spi_bus_p->intr_handle);

    dspi_p->ctar[1] = dspi_calc_ctar(&aux_clocking, spi_bus_p->clock_freq);

    // Call upper layer bus init.

    CYG_SPI_BUS_COMMON_INIT(&spi_bus_p->spi_bus);

}

//-----------------------------------------------------------------------------

// Set up Rx DMA channel

static void

rx_dma_channel_setup(cyghwr_hal_freescale_dma_set_t *dma_set_p,

                     cyg_uint8* data_buf, cyg_uint32 bus_16bit,

                     volatile cyghwr_hal_freescale_edma_tcd_t *tcd_p)

{

    cyg_uint32 step, sdsize;

    static cyg_uint8 popr_sink;

    // Set the correct transfer size.

    if(bus_16bit) {

        step = 2;

        sdsize = FREESCALE_EDMA_ATTR_SIZE_16;

    } else {

        step = 1;

        sdsize = FREESCALE_EDMA_ATTR_SIZE_8;

    }

    if(data_buf) {

        tcd_p->doff = step;

        tcd_p->daddr = data_buf;

    } else {

        tcd_p->doff = 0;

        tcd_p->daddr = &popr_sink;

    }

    tcd_p->nbytes.mlno = step;

    tcd_p->attr =  FREESCALE_EDMA_ATTR_SSIZE(sdsize) |

          FREESCALE_EDMA_ATTR_DSIZE(sdsize) |

          FREESCALE_EDMA_ATTR_SMOD(0) |

          FREESCALE_EDMA_ATTR_DMOD(0);

#if DEBUG_SPI >= 3

    hal_freescale_edma_tcd_diag(tcd_p, -1, "[DSPI Rx]");

#endif

}

//----------------------------------------------------------------------------

// Set up Tx FIFO queue

// Set up Tx FIFO command queue

//     DSPI requires sending command for every transfer.

// Used for transfers that fit within DSPI FIFO.

#if DEBUG_SPI >= 2

static const char debug_format[] = "BUFF %dbit %s: %p 0x%08x remain %d:\n";

#endif

static inline volatile cyg_uint32

fifo_pushque_fill(cyg_spi_freescale_dspi_bus_t* dspi_bus, cyg_uint8*

                  data_p, cyg_uint32 count, cyg_bool bus_16bit, cyg_uint32 pushr,

                  cyg_bool drop_cs)

{

    cyghwr_devs_freescale_dspi_t* dspi_p = dspi_bus->setup_p->dspi_p;

    cyg_uint32 txfifo_n = dspi_bus->txfifo_n;

    if(data_p) {

        if(!bus_16bit) {

            for(; count > 1; count--) {

                if(!(--txfifo_n)) {

                    dspi_p->pushr = pushr |= *data_p | FREESCALE_DSPI_PUSHR_EOQ_M;

                    count--;

                    DEBUG2_PRINTF(debug_format, 8, "FBK", &dspi_p->pushr,

                                  pushr | *data_p, count);

                    return count;

                }

                dspi_p->pushr = pushr | *data_p++;

                DEBUG3_PRINTF(debug_format, 8, "FAD", &dspi_p->pushr,

                              pushr | data_p[-1], count-1);

            }

            pushr |= *data_p;

        } else {

            cyg_uint16* data16_p = (cyg_uint16 *)data_p;

            cyg_uint16 data_word;

            for(; count > 2; count-=2) {

                if(!(--txfifo_n)) {

                    dspi_p->pushr = pushr |= *data16_p | FREESCALE_DSPI_PUSHR_EOQ_M;

                    count-=2;

                    DEBUG2_PRINTF(debug_format, 16, "FBK", &dspi_p->pushr,

                                  pushr, count);

                    return count;

                }

                data_word = *data16_p++;

                dspi_p->pushr = pushr | data_word;

                DEBUG3_PRINTF(debug_format, 16, "FAD", &dspi_p->pushr,

                              pushr | data_word, (count-1)*2);

            }

            data_word = *data16_p;

            pushr |= data_word;

        }

    } else {

        for(; count > 1; count--) {

            if(!(--txfifo_n)) {

                dspi_p->pushr = pushr |= FREESCALE_DSPI_PUSHR_EOQ_M;

                count--;

                DEBUG2_PRINTF(debug_format, 0, "FBK", &dspi_p->pushr,

                              pushr, count);

                return count;

            }

            dspi_p->pushr = pushr;

            DEBUG3_PRINTF(debug_format, 0, "FAD", &dspi_p->pushr, pushr,

                          count-1);

        }

    }

    if(drop_cs)

        pushr &= ~FREESCALE_DSPI_PUSHR_CONT_M;

    dspi_p->pushr = pushr |= FREESCALE_DSPI_PUSHR_EOQ_M;

    DEBUG3_PRINTF(debug_format, data_p ? (bus_16bit ? 16 :8) : pushr,

                  (drop_cs ? "FEN" : "FSG"), &dspi_p->pushr, pushr, 0);

    return 0;

}

//----------------------------------------------------------------------------

// Set up Tx

// Set up Tx DMA command queue

//     DSPI requires sending command for every transfer.

// Used for transfers larger than DSPI FIFO

static inline volatile cyg_uint32

dma_pushque_fill(cyg_spi_freescale_dspi_bus_t* dspi_bus, cyg_uint8* data_p,

                 cyg_uint32 count, cyg_bool bus_16bit, cyg_uint32 pushr,

                 cyg_bool drop_cs)

{

    volatile cyg_uint32* pushque_p;

    volatile cyg_uint32* pushque_end;

    pushque_p = dspi_bus->pushque_p;

    pushque_end = pushque_p + dspi_bus->pushque_n;

    pushque_p = dspi_bus->pushque_p;

    if(data_p) {

        if(!bus_16bit) {

            do {

                if(pushque_p == pushque_end) {

                    pushque_p[0] = pushr;

                    pushque_p[-1] |= FREESCALE_DSPI_PUSHR_EOQ_M;

                    DEBUG2_PRINTF(debug_format, 8, "BRK", pushque_p-1,

                                  pushque_p[-1], count);

                    return count;

                }

                *pushque_p++ = pushr | *data_p++;

                DEBUG3_PRINTF(debug_format, 8, "ADD", pushque_p-1,

                              pushque_p[-1], count-1);

            } while(--count > 1);

            pushr |= *data_p;

        } else {

            cyg_uint16* data16_p = (cyg_uint16 *)data_p;

            cyg_uint16 data_word;

            do {

                if(pushque_p == pushque_end) {

                    pushque_p[0] = pushr;

                    pushque_p[-1] |= FREESCALE_DSPI_PUSHR_EOQ_M;

                    DEBUG2_PRINTF(debug_format, 16, "BRK", pushque_p-1,

                                  pushque_p[-1], count);

                    return count;

                }

                data_word = *data16_p++;

                *pushque_p++ = pushr | data_word;

                DEBUG3_PRINTF(debug_format, 16, "ADD", pushque_p-1,

                              pushque_p[-1], count-2);

            } while((count -= 2) > 2);

            data_word = *data16_p;

            pushr |= data_word;

        }

    } else {

        do {

            if(pushque_p == pushque_end) {

                pushque_p[0] = pushr;

                pushque_p[-1] |= FREESCALE_DSPI_PUSHR_EOQ_M;

                DEBUG2_PRINTF(debug_format, 0, "BRK", pushque_p-1,

                              pushque_p[-1], count);

                return count;

            }

            *pushque_p++ = pushr;

            DEBUG3_PRINTF(debug_format, 0, "BRK", pushque_p-1, pushque_p[-1],

                          count-1);

        } while(--count > 1);

    }

    if(drop_cs) pushr &= ~FREESCALE_DSPI_PUSHR_CONT_M;

    pushque_p[1] = pushr;

    *pushque_p = pushr |= FREESCALE_DSPI_PUSHR_EOQ_M;

    DEBUG2_PRINTF(debug_format, data_p ? (bus_16bit ? 16 :8) : 0,

                  (drop_cs ? "END" : "SGM"), pushque_p, pushque_p[0], 0);