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//=============================================================================
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//
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// spi_simple_spi.c
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//
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// SPI driver implementation for simple_spi
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2008, 2009 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Piotr Skrzypek
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// Date: 2012-05-14
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/hal_if.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/drv_api.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_ass.h>
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#include <cyg/infra/diag.h>
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#include <cyg/io/spi.h>
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#include <cyg/io/spi_simple_spi.h>
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#include <pkgconf/devs_spi_opencores_simple_spi.h>
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#include <pkgconf/hal.h>
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#include <pkgconf/io_spi.h>
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#define SIMPLE_SPI_BASE 0xB0000000
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#define SIMPLE_SPI_SPACE 0x01000000
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// Register space
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#define SIMPLE_SPI_SPCR 0x00
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#define SIMPLE_SPI_SPSR 0x01
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#define SIMPLE_SPI_SPDR 0x02
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#define SIMPLE_SPI_SPER 0x03
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#define SIMPLE_SPI_SPSS 0x04
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// SIMPLE_SPI_SPCR bits
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#define SIMPLE_SPI_SPCR_SPIE 0x80
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#define SIMPLE_SPI_SPCR_SPE 0x40
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#define SIMPLE_SPI_SPCR_MSTR 0x10
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#define SIMPLE_SPI_SPCR_CPOL 0x08
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#define SIMPLE_SPI_SPCR_CPHA 0x04
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#define SIMPLE_SPI_SPCR_SPR 0x03
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// SIMPLE_SPI_SPSR bits
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#define SIMPLE_SPI_SPSR_SPIF 0x80
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#define SIMPLE_SPI_SPSR_WCOL 0x40
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#define SIMPLE_SPI_SPSR_WFFULL 0x08
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#define SIMPLE_SPI_SPSR_WFEMPTY 0x04
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#define SIMPLE_SPI_SPSR_RFFULL 0x02
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#define SIMPLE_SPI_SPSR_RFEMPTY 0x01
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// SIMPLE_SPI_SPER bits
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#define SIMPLE_SPI_SPER_ICNT(x) ((x-1) << 6)
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// Divider table
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cyg_uint8 simple_spi_divflags[] = {0x0, 0x1, 0x4, 0x2, 0x3, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB};
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cyg_vector_t simple_spi_int_vectors[] = { CYGNUM_DEVS_SPI_OPENCORES_SIMPLE_SPI_INTS };
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static cyg_uint32 simple_spi_isr(cyg_vector_t vector, cyg_addrword_t data) {
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cyg_drv_interrupt_mask(vector);
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cyg_drv_interrupt_acknowledge(vector);
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return(CYG_ISR_CALL_DSR | CYG_ISR_HANDLED);
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}
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static void simple_spi_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
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cyg_spi_opencores_simple_spi_bus_t *bus = (cyg_spi_opencores_simple_spi_bus_t *) data;
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// Clear interrupt
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPSR, SIMPLE_SPI_SPSR_SPIF);
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cyg_drv_interrupt_unmask(vector);
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// Unlock waiting thread
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cyg_drv_cond_signal(&bus->condvar);
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}
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static void simple_spi_transaction_begin(cyg_spi_device* device) {
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cyg_spi_opencores_simple_spi_bus_t* bus = (cyg_spi_opencores_simple_spi_bus_t*) device->spi_bus;
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cyg_spi_opencores_simple_spi_device_t* dev = (cyg_spi_opencores_simple_spi_device_t*) device;
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// Temporarily disable peripheral and clean up fifos.
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPCR, 0);
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// Determine divider flags to meet required SCK speed. Find highest speed that is
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// lower or equal the provided threshold.
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cyg_uint32 freq = CYGNUM_DEVS_SPI_OPENCORES_SIMPLE_SPI_BUS_SPEED * 1000000;
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int i = 0;
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while((freq / (1 << (i + 1))) > (dev->freq) && (i) < (sizeof(simple_spi_divflags)-1)) {
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i++;
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}
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cyg_uint8 reg;
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// Configure extensions register with speed and interrupt granularity
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reg = SIMPLE_SPI_SPER_ICNT(1) |
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(simple_spi_divflags[i] >> 2);
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPER, reg);
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// Configure control register with speed, phase and polarity
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reg = SIMPLE_SPI_SPCR_SPE |
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SIMPLE_SPI_SPCR_MSTR |
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(dev->polarity ? SIMPLE_SPI_SPCR_CPOL : 0) |
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(dev->phase ? SIMPLE_SPI_SPCR_CPHA : 0) |
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(simple_spi_divflags[i] & SIMPLE_SPI_SPCR_SPR);
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPCR, reg);
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}
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static void simple_spi_transaction_transfer_tick(cyg_spi_device* device,
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cyg_bool polled,
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cyg_uint32 count,
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const cyg_uint8* tx_data,
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cyg_uint8* rx_data,
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cyg_bool drop_cs,
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cyg_bool is_tick) {
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cyg_spi_opencores_simple_spi_bus_t* bus = (cyg_spi_opencores_simple_spi_bus_t*) device->spi_bus;
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cyg_spi_opencores_simple_spi_device_t* dev = (cyg_spi_opencores_simple_spi_device_t*) device;
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// Enable interrupts if using interrupt mode
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cyg_uint8 reg;
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if(!polled) {
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HAL_READ_UINT8(bus->base_addr + SIMPLE_SPI_SPCR, reg);
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reg |= SIMPLE_SPI_SPCR_SPIE;
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPCR, reg);
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}
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// Assert CS if it is not asserted yet. Note that tick command is not supposed
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// to use CS
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if(!bus->cs_asserted && !is_tick) {
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPSS, (1 << dev->cs));
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CYGACC_CALL_IF_DELAY_US(dev->cs_to_tran);
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bus->cs_asserted = true;
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}
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// Transfer the data
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int i;
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for(i = 0; i < count; i++) {
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// If multiple bytes are transfered, then wait tran_to_tran
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if(i > 0) {
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CYGACC_CALL_IF_DELAY_US(dev->tran_to_tran);
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}
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// Send data or NULL (tick uses NULL)
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reg = tx_data ? tx_data[i] : 0;
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPDR, reg);
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// Wait for transmission
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if(polled) {
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do {
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HAL_READ_UINT8(bus->base_addr + SIMPLE_SPI_SPSR, reg);
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} while(!(reg & SIMPLE_SPI_SPSR_SPIF));
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPSR, SIMPLE_SPI_SPSR_SPIF);
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}
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else {
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//FIXME at high SCK speeds the interrupt happens so quickly that
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//this thread can't make to cond_wait. Signal from DSR is posted
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//to nowhere and the thread hangs.
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cyg_drv_mutex_lock(&bus->mutex);
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cyg_drv_cond_wait(&bus->condvar);
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cyg_drv_mutex_unlock(&bus->mutex);
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}
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// Read received byte and store if required
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HAL_READ_UINT8(bus->base_addr + SIMPLE_SPI_SPDR, reg);
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if(rx_data) {
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rx_data[i] = reg;
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}
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}
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// Drop CS if required
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if(drop_cs && !is_tick) {
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bus->cs_asserted = false;
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CYGACC_CALL_IF_DELAY_US(dev->tran_to_cs);
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPSS, 0);
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}
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// Disable interrupts if using interrupt mode
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if(!polled) {
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HAL_READ_UINT8(bus->base_addr + SIMPLE_SPI_SPCR, reg);
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reg &= ~SIMPLE_SPI_SPCR_SPIE;
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPCR, reg);
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}
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}
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static void simple_spi_transaction_transfer(cyg_spi_device* device,
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cyg_bool polled,
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cyg_uint32 count,
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const cyg_uint8* tx_data,
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cyg_uint8* rx_data,
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cyg_bool drop_cs) {
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simple_spi_transaction_transfer_tick(device, polled, count, tx_data, rx_data, drop_cs, false);
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}
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static void simple_spi_transaction_tick(cyg_spi_device* device,
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cyg_bool polled,
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cyg_uint32 count) {
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simple_spi_transaction_transfer_tick(device, polled, count, NULL, NULL, true, true);
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}
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static void simple_spi_transaction_end(cyg_spi_device* device) {
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cyg_spi_opencores_simple_spi_bus_t* bus = (cyg_spi_opencores_simple_spi_bus_t*) device->spi_bus;
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// Disable the peripheral and clean up buffers.
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HAL_WRITE_UINT8(bus->base_addr + SIMPLE_SPI_SPCR, 0);
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}
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static int simple_spi_get_config(cyg_spi_device* device,
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cyg_uint32 key,
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void* buf,
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cyg_uint32* len) {
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cyg_spi_opencores_simple_spi_device_t* dev = (cyg_spi_opencores_simple_spi_device_t*) device;
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if(key == CYG_IO_GET_CONFIG_SPI_CLOCKRATE) {
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cyg_uint32 *freq = (cyg_uint32*) buf;
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*freq = dev->freq;
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return 0;
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}
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else {
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return -1;
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}
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}
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static int simple_spi_set_config(cyg_spi_device* device,
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cyg_uint32 key,
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const void* buf,
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cyg_uint32* len) {
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283 |
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cyg_spi_opencores_simple_spi_device_t* dev = (cyg_spi_opencores_simple_spi_device_t*) device;
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if(key == CYG_IO_SET_CONFIG_SPI_CLOCKRATE) {
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dev->freq = *((cyg_uint32*)buf);
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return 0;
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}
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else {
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return -1;
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}
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}
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// Declare number of SPI buses
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cyg_spi_opencores_simple_spi_bus_t cyg_spi_simple_spi_bus[CYGNUM_DEVS_SPI_OPENCORES_SIMPLE_SPI_COUNT];
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// This is a low level constructor of the driver. It is called very early
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static void CYGBLD_ATTRIB_C_INIT_PRI(CYG_INIT_BUS_SPI) simple_spi_init(void) {
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int i;
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cyg_uint32 base = SIMPLE_SPI_BASE;
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for(i = 0; i < CYGNUM_DEVS_SPI_OPENCORES_SIMPLE_SPI_COUNT; i++) {
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// Connect functions
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cyg_spi_simple_spi_bus[i].spi_bus.spi_transaction_begin = simple_spi_transaction_begin;
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cyg_spi_simple_spi_bus[i].spi_bus.spi_transaction_transfer = simple_spi_transaction_transfer;
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cyg_spi_simple_spi_bus[i].spi_bus.spi_transaction_tick = simple_spi_transaction_tick;
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cyg_spi_simple_spi_bus[i].spi_bus.spi_transaction_end = simple_spi_transaction_end;
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cyg_spi_simple_spi_bus[i].spi_bus.spi_get_config = simple_spi_get_config;
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cyg_spi_simple_spi_bus[i].spi_bus.spi_set_config = simple_spi_set_config;
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// Fill the base address
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cyg_spi_simple_spi_bus[i].base_addr = base;
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base += SIMPLE_SPI_SPACE;
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// Initialize interrupts
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319 |
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cyg_drv_interrupt_create(simple_spi_int_vectors[i],
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CYGNUM_DEVS_SPI_OPENCORES_SIMPLE_SPI_INT_PRI,
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321 |
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(cyg_addrword_t) &cyg_spi_simple_spi_bus[i],
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simple_spi_isr,
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simple_spi_dsr,
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324 |
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&cyg_spi_simple_spi_bus[i].int_handle,
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325 |
|
|
&cyg_spi_simple_spi_bus[i].int_data);
|
326 |
|
|
cyg_drv_interrupt_attach(cyg_spi_simple_spi_bus[i].int_handle);
|
327 |
|
|
cyg_drv_interrupt_unmask(simple_spi_int_vectors[i]);
|
328 |
|
|
|
329 |
|
|
// Initialize synchronization
|
330 |
|
|
cyg_drv_mutex_init(&cyg_spi_simple_spi_bus[i].mutex);
|
331 |
|
|
cyg_drv_cond_init(&cyg_spi_simple_spi_bus[i].condvar,
|
332 |
|
|
&cyg_spi_simple_spi_bus[i].mutex);
|
333 |
|
|
|
334 |
|
|
// Private status
|
335 |
|
|
cyg_spi_simple_spi_bus[i].cs_asserted = false;
|
336 |
|
|
|
337 |
|
|
// Initialize upper layer
|
338 |
|
|
CYG_SPI_BUS_COMMON_INIT(&cyg_spi_simple_spi_bus[i].spi_bus);
|
339 |
|
|
}
|
340 |
|
|
}
|
341 |
|
|
|
342 |
|
|
|