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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [devs/] [usb/] [at91/] [current/] [src/] [usbs_at91.c] - Blame information for rev 786

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1 786 skrzyp
//==========================================================================
2
//
3
//      usbs_at91.c
4
//
5
//      Driver for the AT91 USB device
6
//
7
//==========================================================================
8
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
9
// -------------------------------------------                              
10
// This file is part of eCos, the Embedded Configurable Operating System.   
11
// Copyright (C) 2006, 2010 Free Software Foundation, Inc.                        
12
//
13
// eCos is free software; you can redistribute it and/or modify it under    
14
// the terms of the GNU General Public License as published by the Free     
15
// Software Foundation; either version 2 or (at your option) any later      
16
// version.                                                                 
17
//
18
// eCos is distributed in the hope that it will be useful, but WITHOUT      
19
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
20
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
21
// for more details.                                                        
22
//
23
// You should have received a copy of the GNU General Public License        
24
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
25
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
26
//
27
// As a special exception, if other files instantiate templates or use      
28
// macros or inline functions from this file, or you compile this file      
29
// and link it with other works to produce a work based on this file,       
30
// this file does not by itself cause the resulting work to be covered by   
31
// the GNU General Public License. However the source code for this file    
32
// must still be made available in accordance with section (3) of the GNU   
33
// General Public License v2.                                               
34
//
35
// This exception does not invalidate any other reasons why a work based    
36
// on this file might be covered by the GNU General Public License.         
37
// -------------------------------------------                              
38
// ####ECOSGPLCOPYRIGHTEND####                                              
39
//==========================================================================
40
//#####DESCRIPTIONBEGIN####
41
//
42
// Author(s):    Oliver Munz,
43
// Contributors: Andrew Lunn, bartv, ccoutand
44
// Date:         2006-02-22
45
//
46
// This code implements support for the on-chip USB port on the AT91
47
// family of processors. The code has been developed on the AT91SAM7S
48
// and may or may not work on other members of the AT91 family.
49
//
50
//####DESCRIPTIONEND####
51
//==========================================================================
52
 
53
#include <pkgconf/system.h>
54
#include <pkgconf/devs_usb_at91.h>
55
#include <cyg/io/usb/usb.h>
56
#include <cyg/io/usb/usbs.h>
57
#include <cyg/io/usb/usbs_at91.h>
58
 
59
#include CYGBLD_HAL_PLATFORM_H
60
#include <cyg/hal/hal_io.h>
61
#include <cyg/hal/drv_api.h>
62
#include <cyg/hal/hal_io.h>
63
#include <cyg/hal/hal_platform_ints.h>
64
#include <cyg/infra/cyg_ass.h>
65
#include <cyg/infra/diag.h>
66
 
67
#include "bitops.h"
68
 
69
#ifndef MIN
70
#define MIN(a,b) (((a) < (b)) ? (a) : (b))
71
#endif
72
 
73
#define AT91_UDP_CSR0 (AT91_UDP_CSR)
74
#define AT91_UDP_FDR0 (AT91_UDP_FDR)
75
 
76
#define pIER (AT91_UDP + AT91_UDP_IER)
77
#define pIDR (AT91_UDP + AT91_UDP_IDR)
78
#define pISR (AT91_UDP + AT91_UDP_ISR)
79
#define pIMR (AT91_UDP + AT91_UDP_IMR)
80
#define pICR (AT91_UDP + AT91_UDP_ICR)
81
 
82
#define pCSR0 (AT91_UDP + AT91_UDP_CSR0)
83
#define pFDR0 (AT91_UDP + AT91_UDP_FDR0)
84
 
85
#define pCSRn(N) (pCSR0 + (N * 4))
86
#define pFDRn(N) (pFDR0 + (N * 4))
87
 
88
#if (AT91_USB_ENDPOINTS == 8)
89
#define AT91_UDP_ALLOWED_IRQs \
90
    (AT91_UDP_WAKEUP | AT91_UDP_ENDBUSRES | AT91_UDP_EXTRSM | \
91
     AT91_UDP_RXRSM  | AT91_UDP_RXSUSP    | AT91_UDP_EPINT0 | \
92
     AT91_UDP_EPINT1 | AT91_UDP_EPINT2    | AT91_UDP_EPINT3 | \
93
     AT91_UDP_EPINT4 | AT91_UDP_EPINT5 | \
94
     AT91_UDP_EPINT6 | AT91_UDP_EPINT7 )
95
#elif (AT91_USB_ENDPOINTS == 6)
96
#define AT91_UDP_ALLOWED_IRQs \
97
    (AT91_UDP_WAKEUP | AT91_UDP_ENDBUSRES | AT91_UDP_EXTRSM | \
98
     AT91_UDP_RXRSM  | AT91_UDP_RXSUSP    | AT91_UDP_EPINT0 | \
99
     AT91_UDP_EPINT1 | AT91_UDP_EPINT2    | AT91_UDP_EPINT3 | \
100
     AT91_UDP_EPINT4 | AT91_UDP_EPINT5 )
101
#elif (AT91_USB_ENDPOINTS == 4)
102
#define AT91_UDP_ALLOWED_IRQs \
103
    (AT91_UDP_WAKEUP | AT91_UDP_ENDBUSRES | AT91_UDP_EXTRSM | \
104
     AT91_UDP_RXRSM  | AT91_UDP_RXSUSP    | AT91_UDP_EPINT0 | \
105
     AT91_UDP_EPINT1 | AT91_UDP_EPINT2    | AT91_UDP_EPINT3)
106
#endif
107
 
108
#define THERE_IS_A_NEW_PACKET_IN_THE_UDP 0xffff
109
 
110
// Fifo size for each end point.
111
#if defined(CYGHWR_HAL_ARM_AT91SAM7SE)
112
static const cyg_uint16 usbs_at91_endpoint_fifo_size[AT91_USB_ENDPOINTS] = {
113
  8,
114
  64,
115
  64,
116
  64,
117
  512,
118
  512,
119
  64,
120
  64
121
};
122
#elif defined(CYGHWR_HAL_ARM_AT91SAM7X)
123
static const cyg_uint16 usbs_at91_endpoint_fifo_size[AT91_USB_ENDPOINTS] = {
124
  8,
125
  64,
126
  64,
127
  64,
128
  256,
129
  256
130
};
131
#else
132
static const cyg_uint16 usbs_at91_endpoint_fifo_size[AT91_USB_ENDPOINTS] = {
133
  8,
134
  64,
135
  64,
136
  64,
137
};
138
#endif
139
 
140
// Does an endpoint support ping pong buffering?
141
#if defined(CYGHWR_HAL_ARM_AT91SAM7SE)
142
static const bool usbs_at91_endpoint_pingpong[AT91_USB_ENDPOINTS] = {
143
  false,
144
  true,
145
  true,
146
  false,
147
  true,
148
  true,
149
  true,
150
  true
151
};
152
#elif defined(CYGHWR_HAL_ARM_AT91SAM7X)
153
static const bool usbs_at91_endpoint_pingpong[AT91_USB_ENDPOINTS] = {
154
  false,
155
  true,
156
  true,
157
  false,
158
  true,
159
  true
160
};
161
#else
162
static const bool usbs_at91_endpoint_pingpong[AT91_USB_ENDPOINTS] = {
163
  false,
164
  true,
165
  true,
166
  false
167
};
168
#endif
169
 
170
static cyg_uint8 *usbs_at91_endpoint_pbegin[AT91_USB_ENDPOINTS] =
171
#if (AT91_USB_ENDPOINTS == 8)
172
  { 0, 0, 0, 0, 0, 0, 0, 0 };
173
#elif (AT91_USB_ENDPOINTS == 6)
174
  { 0, 0, 0, 0, 0, 0 };
175
#else
176
  { 0, 0, 0, 0 };
177
#endif
178
 
179
static cyg_uint8 *usbs_at91_endpoint_pend[AT91_USB_ENDPOINTS] =
180
#if (AT91_USB_ENDPOINTS == 8)
181
  { 0, 0, 0, 0, 0, 0, 0, 0 };
182
#elif (AT91_USB_ENDPOINTS == 6)
183
  { 0, 0, 0, 0, 0, 0 };
184
#else
185
  { 0, 0 ,0, 0 };
186
#endif
187
 
188
static bool usbs_at91_endpoint_bank1[AT91_USB_ENDPOINTS] =
189
#if (AT91_USB_ENDPOINTS == 8)
190
  { false, false, false, false, false, false, false, false };
191
#elif (AT91_USB_ENDPOINTS == 6)
192
  { false, false, false, false, false, false };
193
#else
194
  { false, false, false, false };
195
#endif
196
 
197
static cyg_uint16 usbs_at91_endpoint_bytes_in_fifo[AT91_USB_ENDPOINTS] =
198
#if (AT91_USB_ENDPOINTS == 8)
199
  { 0, 0, 0, 0, 0, 0, 0, 0 };
200
#elif (AT91_USB_ENDPOINTS == 6)
201
  { 0, 0, 0, 0, 0, 0 };
202
#else
203
  { 0, 0, 0, 0 };
204
#endif
205
 
206
static cyg_uint16 usbs_at91_endpoint_bytes_received[AT91_USB_ENDPOINTS] =
207
  { THERE_IS_A_NEW_PACKET_IN_THE_UDP, THERE_IS_A_NEW_PACKET_IN_THE_UDP,
208
#if (AT91_USB_ENDPOINTS > 4)
209
        THERE_IS_A_NEW_PACKET_IN_THE_UDP, THERE_IS_A_NEW_PACKET_IN_THE_UDP,
210
#if (AT91_USB_ENDPOINTS > 6)
211
        THERE_IS_A_NEW_PACKET_IN_THE_UDP, THERE_IS_A_NEW_PACKET_IN_THE_UDP,
212
#endif
213
#endif
214
    THERE_IS_A_NEW_PACKET_IN_THE_UDP, THERE_IS_A_NEW_PACKET_IN_THE_UDP};
215
 
216
static cyg_interrupt usbs_at91_intr_data;
217
static cyg_handle_t usbs_at91_intr_handle;
218
 
219
static void usbs_at91_ep0_start(usbs_control_endpoint *);
220
static void usbs_at91_poll(usbs_control_endpoint *);
221
 
222
static void usbs_at91_endpoint_start(usbs_rx_endpoint * pep);
223
static void usbs_at91_endpoint_set_halted(usbs_rx_endpoint * pep,
224
                                          cyg_bool new_value);
225
void usbs_at91_endpoint_init(usbs_rx_endpoint * pep,
226
                             cyg_uint8 endpoint_type,
227
                             cyg_bool enable);
228
 
229
// Endpoint 0, the control endpoint, structure. 
230
usbs_control_endpoint usbs_at91_ep0 = {
231
  // The hardware does not distinguish  between detached, attached and powered.
232
  state:                  USBS_STATE_POWERED,
233
  enumeration_data:       (usbs_enumeration_data *) 0,
234
  start_fn:               usbs_at91_ep0_start,
235
  poll_fn:                usbs_at91_poll,
236
  interrupt_vector:       CYGNUM_HAL_INTERRUPT_UDP,
237
  control_buffer:         {0, 0, 0, 0, 0, 0, 0, 0},
238
  state_change_fn:        (void (*) (usbs_control_endpoint *,
239
                                     void *, usbs_state_change, int)) 0,
240
  state_change_data:      (void *) 0,
241
  standard_control_fn:    (usbs_control_return (*)
242
                          (usbs_control_endpoint *, void *)) 0,
243
  standard_control_data:  (void *) 0,
244
  class_control_fn:       (usbs_control_return (*)
245
                           (usbs_control_endpoint *, void *)) 0,
246
  class_control_data:     (void *) 0,
247
  vendor_control_fn:      (usbs_control_return (*)
248
                           (usbs_control_endpoint *, void *)) 0,
249
  vendor_control_data:    (void *) 0,
250
  reserved_control_fn:    (usbs_control_return (*)
251
                           (usbs_control_endpoint *, void *)) 0,
252
  reserved_control_data:  (void *) 0,
253
  buffer:                 (unsigned char *) 0,
254
  buffer_size:            0,
255
  fill_buffer_fn:         (void (*)(usbs_control_endpoint *)) 0,
256
  fill_data:              (void *) 0,
257
  fill_index:             0,
258
  complete_fn:            (usbs_control_return (*)(usbs_control_endpoint *,
259
                                                   int)) 0
260
};
261
 
262
// Endpoint 1 receive control structure
263
usbs_rx_endpoint usbs_at91_ep1 = {
264
  start_rx_fn:    usbs_at91_endpoint_start,
265
  set_halted_fn:  usbs_at91_endpoint_set_halted,
266
  complete_fn:    (void (*)(void *, int)) 0,
267
  complete_data:  (void *) 0,
268
  buffer:         (unsigned char *) 0,
269
  buffer_size:    0,
270
  halted:         0,
271
};
272
 
273
// Endpoint 2 Receive control structure
274
usbs_rx_endpoint usbs_at91_ep2 = {
275
  start_rx_fn:    usbs_at91_endpoint_start,
276
  set_halted_fn:  usbs_at91_endpoint_set_halted,
277
  complete_fn:    (void (*)(void *, int)) 0,
278
  complete_data:  (void *) 0,
279
  buffer:         (unsigned char *) 0,
280
  buffer_size:    0,
281
  halted:         0,
282
};
283
 
284
// Endpoint 3 Receive control structure
285
usbs_rx_endpoint usbs_at91_ep3 = {
286
  start_rx_fn:    usbs_at91_endpoint_start,
287
  set_halted_fn:  usbs_at91_endpoint_set_halted,
288
  complete_fn:    (void (*)(void *, int)) 0,
289
  complete_data:  (void *) 0,
290
  buffer:         (unsigned char *) 0,
291
  buffer_size:    0,
292
  halted:         0,
293
};
294
 
295
#if (AT91_USB_ENDPOINTS > 4)
296
// Endpoint 4 Receive control structure
297
usbs_rx_endpoint usbs_at91_ep4 = {
298
  start_rx_fn:    usbs_at91_endpoint_start,
299
  set_halted_fn:  usbs_at91_endpoint_set_halted,
300
  complete_fn:    (void (*)(void *, int)) 0,
301
  complete_data:  (void *) 0,
302
  buffer:         (unsigned char *) 0,
303
  buffer_size:    0,
304
  halted:         0,
305
};
306
#endif
307
 
308
#if (AT91_USB_ENDPOINTS > 5)
309
// Endpoint 5 Receive control structure
310
usbs_rx_endpoint usbs_at91_ep5 = {
311
  start_rx_fn:    usbs_at91_endpoint_start,
312
  set_halted_fn:  usbs_at91_endpoint_set_halted,
313
  complete_fn:    (void (*)(void *, int)) 0,
314
  complete_data:  (void *) 0,
315
  buffer:         (unsigned char *) 0,
316
  buffer_size:    0,
317
  halted:         0,
318
};
319
#endif
320
 
321
#if (AT91_USB_ENDPOINTS > 6)
322
// Endpoint 6 Receive control structure
323
usbs_rx_endpoint usbs_at91_ep6 = {
324
  start_rx_fn:    usbs_at91_endpoint_start,
325
  set_halted_fn:  usbs_at91_endpoint_set_halted,
326
  complete_fn:    (void (*)(void *, int)) 0,
327
  complete_data:  (void *) 0,
328
  buffer:         (unsigned char *) 0,
329
  buffer_size:    0,
330
  halted:         0,
331
};
332
#endif
333
 
334
#if (AT91_USB_ENDPOINTS > 7)
335
// Endpoint 7 Receive control structure
336
usbs_rx_endpoint usbs_at91_ep7 = {
337
  start_rx_fn:    usbs_at91_endpoint_start,
338
  set_halted_fn:  usbs_at91_endpoint_set_halted,
339
  complete_fn:    (void (*)(void *, int)) 0,
340
  complete_data:  (void *) 0,
341
  buffer:         (unsigned char *) 0,
342
  buffer_size:    0,
343
  halted:         0,
344
};
345
#endif
346
 
347
// Array of end points. Used for translating end point pointer to an
348
// end point number
349
static const void *usbs_at91_endpoints[AT91_USB_ENDPOINTS] = {
350
  (void *) &usbs_at91_ep0,
351
  (void *) &usbs_at91_ep1,
352
  (void *) &usbs_at91_ep2,
353
  (void *) &usbs_at91_ep3
354
#if (AT91_USB_ENDPOINTS > 4)
355
  ,(void *) &usbs_at91_ep4, (void *) &usbs_at91_ep5
356
#if (AT91_USB_ENDPOINTS > 6)
357
  ,(void *) &usbs_at91_ep6, (void *) &usbs_at91_ep7
358
#endif
359
#endif
360
};
361
 
362
// Convert an endpoint pointer to an endpoint number, using the array
363
// of endpoint structures
364
static int
365
usbs_at91_pep_to_number(const usbs_rx_endpoint * pep)
366
{
367
  int epn;
368
 
369
  for(epn=0; epn < AT91_USB_ENDPOINTS; epn++) {
370
    if (pep == usbs_at91_endpoints[epn])
371
      return epn;
372
  }
373
  CYG_FAIL("Unknown endpoint");
374
  return 0;
375
}
376
 
377
typedef enum ep0_low_level_status_t {
378
  EP0_LL_IDLE = 0,
379
  EP0_LL_REQUEST,
380
  EP0_LL_SEND_READY,
381
  EP0_LL_ACK,
382
  EP0_LL_RECEIVE_READY,
383
  EP0_LL_ISOERROR,
384
  EP0_LL_STALL,
385
  EP0_LL_SET_ADDRESS,
386
} ep0_low_level_status_t;
387
 
388
// Enable/Disable interrupts for a specific endpoint.
389
static void
390
usbs_at91_endpoint_interrupt_enable (cyg_uint8 epn, bool enable)
391
{
392
  CYG_ASSERT (epn < AT91_USB_ENDPOINTS, "Invalid endpoint");
393
 
394
  if (enable) {
395
    HAL_WRITE_UINT32 (pIER, 1 << epn);
396
  } else {
397
    HAL_WRITE_UINT32 (pIDR, 1 << epn);
398
  }
399
}
400
 
401
static cyg_uint8 *
402
read_fifo_uint8 (cyg_uint8 * pdest, cyg_addrword_t psource, cyg_uint32 size)
403
{
404
  cyg_uint8 *preqbyte = pdest;
405
  cyg_uint8 reqbyte;
406
 
407
  while (size--) {
408
    HAL_READ_UINT8 (psource, reqbyte);
409
    *preqbyte = reqbyte;
410
    preqbyte++;
411
  }
412
 
413
  return preqbyte;
414
}
415
 
416
static cyg_uint8 *
417
write_fifo_uint8 (cyg_addrword_t pdest, cyg_uint8 * psource,
418
                      cyg_uint8 * psource_end)
419
{
420
  cyg_uint8 *preqbyte;
421
 
422
  for (preqbyte = psource; preqbyte < psource_end; preqbyte++) {
423
    HAL_WRITE_UINT8 (pdest, (*preqbyte));
424
  }
425
 
426
  return preqbyte;
427
}
428
 
429
/* Tell the host that the device is ready to start communication */
430
static void
431
usbs_at91_set_pullup (bool set)
432
{
433
#ifdef CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_INTERNAL
434
  cyg_uint32 txvc;
435
  HAL_READ_UINT32(AT91_UDP + AT91_UDP_TXVC, txvc);
436
  if (set) {
437
    txvc |= AT91_UDP_TXVC_PUON;
438
  } else {
439
    txvc &= ~AT91_UDP_TXVC_PUON;
440
  }
441
  HAL_WRITE_UINT32(AT91_UDP + AT91_UDP_TXVC, txvc);
442
#endif // CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_INTERNAL
443
 
444
#ifndef CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN_NONE
445
  if (
446
#ifdef CYGNUM_DEVS_USB_AT91_GPIO_SET_PULLUP_INVERTED
447
      !set
448
#else
449
      set
450
#endif
451
      ) {
452
     HAL_ARM_AT91_GPIO_SET(CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN);
453
  } else {
454
     HAL_ARM_AT91_GPIO_RESET(CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN);
455
  }
456
#endif
457
}
458
 
459
/* Is the USB powered? */
460
bool
461
usbs_at91_read_power (void)
462
{
463
#ifndef CYGDAT_DEVS_USB_AT91_GPIO_READ_POWER_PIN_NONE
464
  cyg_bool state;
465
 
466
  HAL_ARM_AT91_GPIO_GET(CYGDAT_DEVS_USB_AT91_GPIO_READ_POWER_PIN, state);
467
#ifdef CYGNUM_DEVS_USB_AT91_GPIO_READ_POWER_INVERTED
468
  return !state;
469
#else
470
  return state;
471
#endif
472
#endif
473
  return true;
474
}
475
 
476
// Stop all transfers that are currently active.
477
static void
478
usbs_end_all_transfers (usbs_control_return returncode)
479
{
480
  cyg_uint32 epn;
481
  usbs_rx_endpoint *pep;
482
 
483
  for (epn = 1; epn < AT91_USB_ENDPOINTS; epn++) {
484
    if (BITS_ARE_SET (pIMR, 1 << epn)) {
485
      // If the end point is transmitting, call the complete function
486
      // to terminate to transfer
487
      pep = (usbs_rx_endpoint *) usbs_at91_endpoints[epn];
488
 
489
      if (pep->complete_fn) {
490
        (*pep->complete_fn) (pep->complete_data, returncode);
491
      }
492
      // Disable interrupts from the endpoint
493
      usbs_at91_endpoint_interrupt_enable (epn, false);
494
    }
495
  }
496
}
497
 
498
// There has been a change in state. Update the end point.
499
static void
500
usbs_state_notify (usbs_control_endpoint * pcep)
501
{
502
  static int old_state = USBS_STATE_CHANGE_POWERED;
503
  int state = pcep->state & USBS_STATE_MASK;
504
 
505
  if (pcep->state != old_state) {
506
    usbs_end_all_transfers (-EPIPE);
507
    switch (state) {
508
      case USBS_STATE_DETACHED:
509
      case USBS_STATE_ATTACHED:
510
      case USBS_STATE_POWERED:
511
        // Nothing to do
512
        break;
513
      case USBS_STATE_DEFAULT:
514
        HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, 0);
515
        break;
516
      case USBS_STATE_ADDRESSED:
517
        HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, AT91_UDP_GLB_FADDEN);
518
        break;
519
      case USBS_STATE_CONFIGURED:
520
        HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, AT91_UDP_GLB_CONFG);
521
        break;
522
      default:
523
        CYG_FAIL("Unknown endpoint state");
524
    }
525
 
526
    if (pcep->state_change_fn) {
527
      (*pcep->state_change_fn) (pcep, pcep->state_change_data, pcep->state, old_state);
528
    }
529
 
530
    old_state = pcep->state;
531
  }
532
}
533
 
534
static usbs_control_return
535
usbs_parse_host_get_command (usbs_control_endpoint * pcep)
536
{
537
  usbs_control_return retcode;
538
  cyg_uint8 dev_req_type =
539
    (((usb_devreq *) pcep->control_buffer)->type) & USB_DEVREQ_TYPE_MASK;
540
 
541
  switch (dev_req_type) {
542
    case USB_DEVREQ_TYPE_STANDARD:
543
      if (!pcep->standard_control_fn) {
544
        return usbs_handle_standard_control (pcep);
545
      }
546
 
547
      retcode =
548
        (*pcep->standard_control_fn) (pcep, pcep->standard_control_data);
549
 
550
      if (retcode == USBS_CONTROL_RETURN_UNKNOWN) {
551
        return usbs_handle_standard_control (pcep);
552
      }
553
      return retcode;
554
 
555
    case USB_DEVREQ_TYPE_CLASS:
556
      if (!pcep->class_control_fn) {
557
        return USBS_CONTROL_RETURN_STALL;
558
      }
559
      return (*pcep->class_control_fn) (pcep, pcep->class_control_data);
560
 
561
    case USB_DEVREQ_TYPE_VENDOR:
562
      if (!pcep->class_control_fn) {
563
        return USBS_CONTROL_RETURN_STALL;
564
      }
565
      return (*pcep->class_control_fn) (pcep, pcep->vendor_control_data);
566
 
567
    case USB_DEVREQ_TYPE_RESERVED:
568
      if (!pcep->reserved_control_fn) {
569
        return USBS_CONTROL_RETURN_STALL;
570
      }
571
      return (*pcep->reserved_control_fn) (pcep, pcep->reserved_control_data);
572
    default:
573
      return USBS_CONTROL_RETURN_STALL;
574
  }
575
}
576
 
577
static void
578
usbs_at91_endpoint_set_halted (usbs_rx_endpoint * pep, cyg_bool new_value)
579
{
580
  int epn = usbs_at91_pep_to_number(pep);
581
  cyg_addrword_t pCSR = pCSRn(epn);
582
  cyg_uint32 reg;
583
 
584
  cyg_drv_dsr_lock ();
585
 
586
  if (pep->halted != new_value) {
587
    /* There is something is to do */
588
    pep->halted = new_value;
589
 
590
    if ( new_value ) {
591
 
592
      /* Halt endpoint */
593
      SET_BITS (pCSR, AT91_UDP_CSR_FORCESTALL);
594
 
595
    } else {
596
      /* Restart endpoint */
597
      CLEAR_BITS (pCSR, AT91_UDP_CSR_FORCESTALL);
598
 
599
      // Reset Fifo
600
      HAL_READ_UINT32 (AT91_UDP + AT91_UDP_RST_EP, reg);
601
      reg |= (1 << epn);
602
      HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, reg);
603
      reg &= ~(1 << epn);
604
      HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, reg);
605
 
606
      // Ready to use
607
      if (pep->complete_fn) {
608
        (*pep->complete_fn) (pep->complete_data, ENOERR);
609
      }
610
 
611
    }
612
  }
613
  cyg_drv_dsr_unlock ();
614
}
615
 
616
void
617
usbs_at91_endpoint_init (usbs_rx_endpoint * pep, cyg_uint8 endpoint_type,
618
                         cyg_bool enable)
619
{
620
  int epn = usbs_at91_pep_to_number(pep);
621
  cyg_addrword_t pCSR = pCSRn(epn);
622
 
623
  CYG_ASSERT (AT91_USB_ENDPOINTS > epn, "Invalid end point");
624
 
625
  usbs_at91_endpoint_interrupt_enable (epn, false);
626
  /* Reset endpoint */
627
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, 1 << epn);
628
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, 0);
629
 
630
  pep->halted = false;
631
 
632
  /* Type | In */
633
  HAL_WRITE_UINT32 (pCSR, (((((cyg_uint32) endpoint_type) & 0x03) << 8) |
634
                           ((((cyg_uint32) endpoint_type) & 0x80) << 3)));
635
 
636
  usbs_at91_endpoint_bytes_in_fifo[epn] = 0;
637
  usbs_at91_endpoint_bytes_received[epn] = THERE_IS_A_NEW_PACKET_IN_THE_UDP;
638
  usbs_at91_endpoint_bank1[epn] = false;
639
 
640
  if (enable) {
641
    SET_BITS (pCSR, AT91_UDP_CSR_EPEDS);
642
  }
643
}
644
 
645
static void
646
usbs_at91_reset_device (void)
647
{
648
  int epn;
649
 
650
  usbs_end_all_transfers (-EPIPE);
651
 
652
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_IDR, 0xffffffff);
653
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_ICR, 0xffffffff);
654
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, 0xffffffff);
655
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, 0x00000000);
656
 
657
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_FADDR, AT91_UDP_FADDR_FEN);
658
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_CSR0,
659
                    AT91_UDP_CSR_EPEDS | AT91_UDP_CSR_EPTYPE_CTRL);
660
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_IER, AT91_UDP_ALLOWED_IRQs);
661
 
662
  for (epn=1; epn < AT91_USB_ENDPOINTS; epn++) {
663
    usbs_at91_endpoint_init ((usbs_rx_endpoint *)usbs_at91_endpoints[epn],
664
                             0, false);
665
  }
666
}
667
 
668
static void
669
usbs_at91_handle_reset (void)
670
{
671
  int epn;
672
  const usb_endpoint_descriptor *usb_endpoints;
673
  cyg_uint8 endpoint_type;
674
 
675
  cyg_uint8 endpoint_number;
676
 
677
  usbs_at91_reset_device ();
678
 
679
  // Now walk the endpoints configuring them correctly. This only
680
  // works if there is one interface.
681
  usb_endpoints = usbs_at91_ep0.enumeration_data->endpoints;
682
 
683
  for (epn = 1;
684
       epn <= usbs_at91_ep0.enumeration_data->total_number_endpoints;
685
       epn++) {
686
 
687
    endpoint_type = (usb_endpoints[epn-1].attributes |
688
                     (usb_endpoints[epn-1].endpoint &
689
                      USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN ?
690
                      USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN :
691
                      USB_ENDPOINT_DESCRIPTOR_ENDPOINT_OUT));
692
    endpoint_number = usb_endpoints[epn-1].endpoint & ~(USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN);
693
 
694
    if ( endpoint_number < AT91_USB_ENDPOINTS ) {
695
      usbs_at91_endpoint_init((usbs_rx_endpoint *)usbs_at91_endpoints[endpoint_number],
696
                              endpoint_type,
697
                              true);
698
    }
699
  }
700
}
701
 
702
static void
703
usbs_at91_ep0_start (usbs_control_endpoint * endpoint)
704
{
705
  usbs_at91_handle_reset ();
706
 
707
  // If there is additional platform-specific initialization to
708
  // perform, do it now. This macro can come from the platform HAL,
709
  // but may not be available on all platforms.
710
#ifdef AT91_USB_PLATFORM_INIT
711
  AT91_USB_PLATFORM_INIT ();
712
#endif
713
 
714
  usbs_at91_set_pullup (true);
715
  CLEAR_BITS(AT91_UDP + AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
716
}
717
 
718
static void
719
usbs_at91_endpoint_start (usbs_rx_endpoint * pep)
720
{
721
  int epn = usbs_at91_pep_to_number(pep);
722
  cyg_addrword_t pCSR = pCSRn(epn);
723
  cyg_addrword_t pFDR = pFDRn(epn);
724
  cyg_uint16 space = 0;
725
  cyg_uint16 endpoint_size = usbs_at91_endpoint_fifo_size[epn];
726
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[epn];
727
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[epn];
728
 
729
  CYG_ASSERT (pep->complete_fn, "No complete_fn()");
730
 
731
  cyg_drv_dsr_lock ();
732
  if (usbs_at91_ep0.state != USBS_STATE_CONFIGURED) {
733
    /* If not configured it means there is nothing to do */
734
    cyg_drv_dsr_unlock ();
735
 
736
    if (pep->complete_fn) {
737
      (*pep->complete_fn) (pep->complete_data, -EPIPE);
738
    }
739
    return;
740
  }
741
 
742
  // Is this endpoint currently stalled? If so then a size of 0 can
743
  // be used to block until the stall condition is clear, anything
744
  // else should result in an immediate callback.
745
  if (pep->halted) {
746
    /* Halted means nothing to do */
747
    cyg_drv_dsr_unlock ();
748
 
749
    if (pep->complete_fn && pep->buffer_size != 0) {
750
      (*pep->complete_fn) (pep->complete_data, -EAGAIN);
751
    }
752
    return;
753
  }
754
 
755
  if (BITS_ARE_SET (pIMR, 1 << epn)) {
756
    cyg_drv_dsr_unlock ();
757
 
758
    if (pep->complete_fn) {
759
      (*pep->complete_fn) (pep->complete_data, -EIO);
760
    }
761
 
762
    return;
763
  }
764
 
765
  CYG_ASSERT (BITS_ARE_SET (pCSR, 1 << 9), "Wrong endpoint type");
766
 
767
  *ppbegin = pep->buffer;       /* Set the working pointers */
768
  *ppend = (cyg_uint8 *) ((cyg_uint32) pep->buffer + pep->buffer_size);
769
 
770
  if (BITS_ARE_SET (pCSR, 0x400)) {     /* IN: tx_endpoint */
771
    space = (cyg_uint32) * ppend - (cyg_uint32) * ppbegin;
772
 
773
#ifdef CYGSEM_DEVS_USB_AT91_ZERO_LENGTH_PACKET_TERMINATION
774
    if (space == endpoint_size) {
775
      *ppend = *ppbegin;        /* Send zero-packet */
776
    }
777
#endif
778
 
779
    *ppbegin =
780
      write_fifo_uint8 (pFDR, *ppbegin,
781
                        (cyg_uint8 *) ((cyg_uint32) * ppbegin +
782
                                       MIN (space, endpoint_size)));
783
    SET_BITS (pCSR, AT91_UDP_CSR_TXPKTRDY);
784
 
785
    if (*ppend == *ppbegin) {   /* Last packet ? */
786
      *ppend = *ppbegin - 1;    /* The packet hasn't been sent yet */
787
    }
788
  }
789
 
790
  usbs_at91_endpoint_interrupt_enable (epn, true);
791
 
792
  cyg_drv_dsr_unlock ();
793
}
794
 
795
// Perform transmit handling on an endpoint
796
static bool
797
usbs_at91_endpoint_isr_tx(cyg_uint8 epn)
798
{
799
  cyg_addrword_t pCSR = pCSRn(epn);
800
  cyg_addrword_t pFDR = pFDRn(epn);
801
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[epn];
802
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[epn];
803
  cyg_uint32 space = 0;
804
  cyg_uint16 endpoint_size = usbs_at91_endpoint_fifo_size[epn];
805
 
806
  CLEAR_BITS (pCSR, AT91_UDP_CSR_TXCOMP);
807
 
808
  if (BITS_ARE_CLEARED (pCSR, AT91_UDP_CSR_TXPKTRDY)) {
809
    /* Ready to transmit ? */
810
    if (*ppend > *ppbegin) {
811
      /* Something to send */
812
 
813
      space = (cyg_uint32) * ppend - (cyg_uint32) * ppbegin;
814
 
815
#ifdef CYGSEM_DEVS_USB_AT91_ZERO_LENGTH_PACKET_TERMINATION
816
      if (space == endpoint_size) {
817
        *ppend = *ppbegin;            /* Send zero-packet */
818
      }
819
#endif
820
 
821
      *ppbegin =
822
        write_fifo_uint8 (pFDR, *ppbegin,
823
                          (cyg_uint8 *) ((cyg_uint32) * ppbegin +
824
                                         MIN (space, endpoint_size)));
825
      SET_BITS (pCSR, AT91_UDP_CSR_TXPKTRDY);
826
 
827
      if (*ppend == *ppbegin) {       /* Last packet ? */
828
        *ppend = *ppbegin - 1;        /* The packet isn't sent yet */
829
      }
830
 
831
    } else {
832
 
833
#ifdef CYGSEM_DEVS_USB_AT91_ZERO_LENGTH_PACKET_TERMINATION
834
      if (*ppend + 1 == *ppbegin) {
835
        *ppend = *ppbegin;    /* Flag for DSR */
836
        return true;
837
      } else {
838
        *ppend = *ppbegin - 1;        /* Flag for zero-packet */
839
        SET_BITS (pCSR, AT91_UDP_CSR_TXPKTRDY);       /* Send no data */
840
      }
841
#else
842
      *ppend = *ppbegin;    /* Flag for DSR */
843
      return true;
844
#endif
845
 
846
    }
847
  }
848
 
849
  CLEAR_BITS (pCSR,
850
              AT91_UDP_CSR_RX_DATA_BK0 | AT91_UDP_CSR_RX_DATA_BK1 |
851
              AT91_UDP_CSR_RXSETUP | AT91_UDP_CSR_ISOERROR);
852
  return false;
853
}
854
 
855
static bool
856
usbs_at91_endpoint_isr_rx(cyg_uint8 epn)
857
{
858
  cyg_addrword_t pCSR = pCSRn(epn);
859
  cyg_addrword_t pFDR = pFDRn(epn);
860
  cyg_uint16 *pinfifo = &usbs_at91_endpoint_bytes_in_fifo[epn];
861
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[epn];
862
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[epn];
863
  cyg_uint16 *preceived = &usbs_at91_endpoint_bytes_received[epn];
864
  cyg_uint16 endpoint_size = usbs_at91_endpoint_fifo_size[epn];
865
 
866
  if (*preceived == THERE_IS_A_NEW_PACKET_IN_THE_UDP) {
867
    /* There is a new packet */
868
    *preceived = ((*(cyg_uint32 *)pCSR) >> 16) & 0x7ff;
869
    *pinfifo = *preceived;
870
  }
871
 
872
  while ((*ppbegin < *ppend) && *pinfifo) {
873
    /* If we have buffer-space AND data in the FIFO */
874
    HAL_READ_UINT8(pFDR, **ppbegin);
875
    (*ppbegin)++;
876
    (*pinfifo)--;
877
  }
878
 
879
  if (*ppbegin == *ppend) {
880
    /* The buffer is full... call the DSR */
881
    return true;
882
  }
883
 
884
  if (*pinfifo == 0) {
885
    /* If the FIFO is empty, then we can release it */
886
    if (usbs_at91_endpoint_pingpong[epn]) {
887
      /* Time to clear the interrupt flag */
888
 
889
      if (usbs_at91_endpoint_bank1[epn]) {
890
        CLEAR_BITS (pCSR, AT91_UDP_CSR_RX_DATA_BK1);
891
      } else {
892
        CLEAR_BITS (pCSR, AT91_UDP_CSR_RX_DATA_BK0);
893
      }
894
      usbs_at91_endpoint_bank1[epn] = !usbs_at91_endpoint_bank1[epn];
895
    } else {
896
      CLEAR_BITS (pCSR, AT91_UDP_CSR_RX_DATA_BK0);
897
    }
898
 
899
    if (*preceived < endpoint_size) {
900
      /* If the last packet was smaller then the endpoint-size... */
901
      *ppend = *ppbegin;
902
      *preceived = THERE_IS_A_NEW_PACKET_IN_THE_UDP; /* Set flag */
903
 
904
      return true;     /* We can call the completion-function in the DSR */
905
    }
906
 
907
    *preceived = THERE_IS_A_NEW_PACKET_IN_THE_UDP;   /* Set flag */
908
  }
909
  return false;
910
}
911
 
912
// ISR for an endpoint. Handle receive and transmit interrupts.
913
static bool
914
usbs_at91_endpoint_isr (cyg_uint8 epn)
915
{
916
  cyg_addrword_t pCSR = pCSRn(epn);
917
 
918
  CYG_ASSERT (AT91_USB_ENDPOINTS > epn && epn, "Invalid end point");
919
 
920
  // Host has acknowledged the endpoint being stall 
921
  if (BITS_ARE_SET (pCSR, AT91_UDP_CSR_ISOERROR)) {
922
     CLEAR_BITS (pCSR, AT91_UDP_CSR_ISOERROR);
923
  }
924
 
925
  if (BITS_ARE_SET (pCSR, 0x400)) {      /* IN: tx_endpoint */
926
    if (usbs_at91_endpoint_isr_tx(epn))
927
      return true;  // Call the DSR
928
  } else {                               /* OUT: rx_endpoint */
929
    if (!BITS_ARE_CLEARED (pCSR, AT91_UDP_CSR_RX_DATA_BK0) ||
930
        !BITS_ARE_CLEARED (pCSR, AT91_UDP_CSR_RX_DATA_BK1)) {
931
      /* Sometime something received ? */
932
      if(usbs_at91_endpoint_isr_rx(epn))
933
        return true; // Call the DSR;
934
    }
935
 
936
        CLEAR_BITS (pCSR,
937
                AT91_UDP_CSR_TXCOMP | AT91_UDP_CSR_RXSETUP |
938
                AT91_UDP_CSR_ISOERROR);
939
  }
940
 
941
  return false;
942
}
943
 
944
// Handle a DSR for an endpoint
945
static void
946
usbs_at91_endpoint_dsr (cyg_uint8 epn)
947
{
948
  usbs_rx_endpoint *pep = (usbs_rx_endpoint *) usbs_at91_endpoints[epn];
949
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[epn];
950
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[epn];
951
 
952
  CYG_ASSERT (AT91_USB_ENDPOINTS > epn && epn, "Invalid end point");
953
  CYG_ASSERT (pep->complete_fn, "No complete_fn()");
954
 
955
  if (*ppend == *ppbegin) {     /* Transmitted/Received ? */
956
 
957
    pep->buffer_size = (cyg_uint32) * ppbegin - (cyg_uint32) pep->buffer;
958
    if (pep->complete_fn)
959
    {
960
       /* Do not check on pep->buffer_size != 0, user should
961
        * be allowed to send empty packet */
962
       if (!pep->halted) {
963
          (*pep->complete_fn) (pep->complete_data, pep->buffer_size);
964
       } else {
965
          (*pep->complete_fn) (pep->complete_data, -EAGAIN);
966
       }
967
    }
968
    usbs_at91_endpoint_interrupt_enable (epn, false);
969
  }
970
}
971
 
972
// Handle an error condition on the control endpoint
973
static ep0_low_level_status_t
974
usbs_at91_control_error(ep0_low_level_status_t status)
975
{
976
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[0];
977
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[0];
978
 
979
  usbs_at91_ep0.buffer_size = 0;
980
  usbs_at91_ep0.fill_buffer_fn = 0;
981
  usbs_at91_ep0.complete_fn = 0;
982
 
983
  *ppbegin = usbs_at91_ep0.buffer;
984
  *ppend = *ppbegin;
985
 
986
  if (status == EP0_LL_IDLE) {
987
    if (usbs_at91_ep0.complete_fn) {
988
      (*usbs_at91_ep0.complete_fn) (&usbs_at91_ep0,
989
                                    USBS_CONTROL_RETURN_STALL);
990
    }
991
  }
992
 
993
  status = EP0_LL_IDLE;
994
 
995
  CLEAR_BITS (pCSR0, AT91_UDP_CSR_ISOERROR | AT91_UDP_CSR_FORCESTALL);
996
 
997
  return status;
998
}
999
 
1000
// Handle a get status setup message on the control end point
1001
static ep0_low_level_status_t
1002
usbs_at91_control_setup_get_status(void)
1003
{
1004
  ep0_low_level_status_t status;
1005
  usb_devreq *req = (usb_devreq *)usbs_at91_ep0.control_buffer;
1006
  cyg_uint8 recipient = req->type & USB_DEVREQ_RECIPIENT_MASK;
1007
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[0];
1008
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[0];
1009
  cyg_uint16 word = 0;
1010
 
1011
  status = EP0_LL_SEND_READY;
1012
 
1013
  switch (recipient) {
1014
    case USB_DEVREQ_RECIPIENT_DEVICE:
1015
    case USB_DEVREQ_RECIPIENT_INTERFACE:
1016
      // Nothing to do
1017
      break;
1018
    case USB_DEVREQ_RECIPIENT_ENDPOINT:
1019
      if ((usbs_at91_ep0.state == USBS_STATE_CONFIGURED) &&
1020
          (req->index_lo > 0) &&
1021
          (req->index_lo < AT91_USB_ENDPOINTS)) {
1022
        cyg_uint32 CSR;
1023
 
1024
        HAL_READ_UINT32(pCSRn(req->index_lo), CSR);
1025
        if (CSR & AT91_UDP_CSR_EPEDS) {
1026
          word = 1;
1027
        }
1028
      } else {
1029
        status = EP0_LL_STALL;
1030
      }
1031
      break;
1032
    default:
1033
      status = EP0_LL_STALL;
1034
  }
1035
 
1036
  *ppbegin = (cyg_uint8 *)&word;
1037
  *ppend = *ppbegin + sizeof (word);
1038
  return status;
1039
}
1040
 
1041
// Setup the begin and end pointers such that an ACK is sent
1042
static void
1043
usbs_at91_control_setup_send_ack(void)
1044
{
1045
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[0];
1046
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[0];
1047
 
1048
  *ppbegin = usbs_at91_ep0.buffer;
1049
  *ppend = *ppbegin;
1050
}
1051
 
1052
// Handle a get status set feature message on the control endpoint
1053
static ep0_low_level_status_t
1054
usbs_at91_control_setup_set_feature(void)
1055
{
1056
  ep0_low_level_status_t status;
1057
  usb_devreq *req = (usb_devreq *)usbs_at91_ep0.control_buffer;
1058
  cyg_uint8 recipient = req->type & USB_DEVREQ_RECIPIENT_MASK;
1059
  usbs_rx_endpoint * pep;
1060
  cyg_uint8 ep_num = req->index_lo & 0x0F;
1061
 
1062
  usbs_at91_control_setup_send_ack();
1063
  status = EP0_LL_SEND_READY;
1064
 
1065
  switch(recipient) {
1066
    case USB_DEVREQ_RECIPIENT_DEVICE:
1067
      status = EP0_LL_STALL;
1068
      break;
1069
    case USB_DEVREQ_RECIPIENT_INTERFACE:
1070
      // Nothing to do
1071
      break;
1072
    case USB_DEVREQ_RECIPIENT_ENDPOINT:
1073
      if ((usbs_at91_ep0.state == USBS_STATE_CONFIGURED) &&
1074
            (ep_num > 0) &&
1075
            (ep_num < AT91_USB_ENDPOINTS)) {
1076
        cyg_uint32 CSR;
1077
 
1078
        HAL_READ_UINT32(pCSRn(ep_num), CSR);
1079
        pep = (usbs_rx_endpoint *) usbs_at91_endpoints[ep_num];
1080
        if ( (CSR & AT91_UDP_CSR_EPEDS) ) {
1081
          usbs_at91_endpoint_set_halted ( pep , true );
1082
        }
1083
        else
1084
          status = EP0_LL_STALL;
1085
 
1086
      }
1087
      else {
1088
        status = EP0_LL_STALL;
1089
      }
1090
      break;
1091
    default:
1092
      status = EP0_LL_STALL;
1093
  }
1094
  return status;
1095
}
1096
 
1097
// Handle a get status clear feature message on the control endpoint
1098
static ep0_low_level_status_t
1099
usbs_at91_control_setup_clear_feature(void)
1100
{
1101
  ep0_low_level_status_t status;
1102
  usb_devreq *req = (usb_devreq *)usbs_at91_ep0.control_buffer;
1103
  cyg_uint8 recipient = req->type & USB_DEVREQ_RECIPIENT_MASK;
1104
  usbs_rx_endpoint * pep;
1105
  cyg_uint8 ep_num = req->index_lo & 0x0F;
1106
 
1107
  usbs_at91_control_setup_send_ack();
1108
  status = EP0_LL_SEND_READY;
1109
 
1110
  switch (recipient) {
1111
    case USB_DEVREQ_RECIPIENT_DEVICE:
1112
      status = EP0_LL_STALL;
1113
      break;
1114
    case USB_DEVREQ_RECIPIENT_INTERFACE:
1115
      // Nothing to do
1116
      break;
1117
    case USB_DEVREQ_RECIPIENT_ENDPOINT:
1118
      if ((usbs_at91_ep0.state == USBS_STATE_CONFIGURED) &&
1119
          (ep_num > 0) &&
1120
          (ep_num < AT91_USB_ENDPOINTS)) {
1121
        cyg_uint32 CSR;
1122
 
1123
        HAL_READ_UINT32(pCSRn(ep_num), CSR);
1124
        pep = (usbs_rx_endpoint *) usbs_at91_endpoints[ep_num];
1125
        if ( (CSR & AT91_UDP_CSR_EPEDS) && pep->halted ) {
1126
          usbs_at91_endpoint_set_halted ( pep , false );
1127
        }
1128
        else
1129
          status = EP0_LL_STALL;
1130
 
1131
      }
1132
      else {
1133
        status = EP0_LL_STALL;
1134
      }
1135
      break;
1136
    default:
1137
      status = EP0_LL_STALL;
1138
  }
1139
  return status;
1140
}
1141
 
1142
// Handle a setup message from the host
1143
static ep0_low_level_status_t
1144
usbs_at91_control_setup(ep0_low_level_status_t status)
1145
{
1146
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[0];
1147
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[0];
1148
  usb_devreq *req = (usb_devreq *) usbs_at91_ep0.control_buffer;
1149
  cyg_uint8   protocol;
1150
  cyg_uint16 length;
1151
  bool dev_to_host;
1152
  usbs_control_return usbcode;
1153
  bool handled = false;
1154
 
1155
  usbs_at91_ep0.buffer_size = 0;
1156
  usbs_at91_ep0.fill_buffer_fn = 0;
1157
  usbs_at91_ep0.complete_fn = 0;
1158
 
1159
  read_fifo_uint8 ((cyg_uint8 *)req, pFDR0, sizeof (usb_devreq));
1160
 
1161
  length = (req->length_hi << 8) | req->length_lo;;
1162
  dev_to_host = req->type & USB_DEVREQ_DIRECTION_IN;
1163
 
1164
  CLEAR_BITS (pCSR0, AT91_UDP_CSR_DTGLE);
1165
 
1166
  status = EP0_LL_REQUEST;
1167
 
1168
  protocol = req->type & (USB_DEVREQ_TYPE_MASK);
1169
 
1170
  // Set the next transfer direction
1171
  if (dev_to_host) {
1172
    SET_BITS (pCSR0, AT91_UDP_CSR_DIR);     /* Set IN direction */
1173
  } else {
1174
    CLEAR_BITS (pCSR0, AT91_UDP_CSR_DIR);   /* Set OUT direction */
1175
  }
1176
 
1177
  if (protocol == USB_DEVREQ_TYPE_STANDARD) {
1178
    handled = true;
1179
    switch (req->request) {
1180
      case USB_DEVREQ_GET_STATUS:
1181
        status = usbs_at91_control_setup_get_status();
1182
        break;
1183
      case USB_DEVREQ_SET_ADDRESS:
1184
        // Most of the hard work is done by the hardware. We just need
1185
        // to send an ACK.
1186
        usbs_at91_control_setup_send_ack();
1187
        status = EP0_LL_SEND_READY;
1188
        break;
1189
      case USB_DEVREQ_SET_FEATURE:
1190
        status = usbs_at91_control_setup_set_feature();
1191
        break;
1192
      case USB_DEVREQ_CLEAR_FEATURE:
1193
        status = usbs_at91_control_setup_clear_feature();
1194
        break;
1195
      default:
1196
        handled = false;
1197
    }
1198
  }
1199
  if ((protocol != USB_DEVREQ_TYPE_STANDARD) || !handled) {
1200
    // Ask the layer above to process the message
1201
    usbcode = usbs_parse_host_get_command (&usbs_at91_ep0);
1202
    usbs_at91_ep0.buffer_size = MIN (usbs_at91_ep0.buffer_size, length);
1203
 
1204
    *ppbegin = usbs_at91_ep0.buffer;
1205
    *ppend = *ppbegin + usbs_at91_ep0.buffer_size; /* Ready to send... */
1206
 
1207
    if (usbcode == USBS_CONTROL_RETURN_HANDLED) { /* OK */
1208
      if (dev_to_host) {
1209
        status = EP0_LL_SEND_READY;
1210
      } else {
1211
        status = EP0_LL_RECEIVE_READY;
1212
      }
1213
    } else {
1214
      status = EP0_LL_STALL;
1215
    }
1216
  }
1217
  // Clear the setup bit so indicating we have processed the message
1218
  CLEAR_BITS (pCSR0, AT91_UDP_CSR_RXSETUP);
1219
 
1220
  return status;
1221
}
1222
 
1223
static ep0_low_level_status_t
1224
usbs_at91_control_data_recv(ep0_low_level_status_t status)
1225
{
1226
  cyg_uint32 received = 0;
1227
  cyg_uint32 length;
1228
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[0];
1229
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[0];
1230
  usbs_control_return usbcode;
1231
 
1232
  if (status == EP0_LL_RECEIVE_READY) {
1233
    received = ((*(cyg_uint32 *) pCSR0) >> 16) & 0x7ff;
1234
    length = MIN (received, (cyg_uint32) *ppend - (cyg_uint32) *ppbegin);
1235
    *ppbegin = read_fifo_uint8 (*ppbegin, pFDR0, length);
1236
 
1237
    if (received < usbs_at91_endpoint_fifo_size[0]) {        /* Last packet ? */
1238
      *ppend = *ppbegin;
1239
    }
1240
 
1241
    if (*ppbegin == *ppend) {   /* All received ? */
1242
      usbs_at91_ep0.buffer_size =
1243
        (cyg_uint32) *ppend - (cyg_uint32) usbs_at91_ep0.buffer;
1244
      usbcode = USBS_CONTROL_RETURN_STALL;
1245
 
1246
      if (usbs_at91_ep0.complete_fn) {
1247
        usbcode = (*usbs_at91_ep0.complete_fn) (&usbs_at91_ep0, 0);
1248
      }
1249
 
1250
      if (usbcode == USBS_CONTROL_RETURN_HANDLED) {
1251
        status = EP0_LL_SEND_READY;
1252
      } else {
1253
        status = EP0_LL_STALL;
1254
      }
1255
    }
1256
  }
1257
 
1258
  CLEAR_BITS (pCSR0, AT91_UDP_CSR_RX_DATA_BK0);
1259
 
1260
  return status;
1261
}
1262
 
1263
static ep0_low_level_status_t
1264
usbs_at91_control_data_sent(ep0_low_level_status_t status)
1265
{
1266
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[0];
1267
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[0];
1268
  cyg_uint32 bytes_to_write = 0;
1269
  usb_devreq *req = (usb_devreq *)usbs_at91_ep0.control_buffer;
1270
  cyg_uint16 value;
1271
 
1272
  switch (status) {
1273
    case EP0_LL_SEND_READY:
1274
      if (*ppbegin == *ppend &&
1275
          usbs_at91_ep0.fill_buffer_fn == NULL) {
1276
        // All bytes are sent, send ACK
1277
        status = EP0_LL_ACK;
1278
        SET_BITS (pCSR0, AT91_UDP_CSR_TXPKTRDY);      // Signal FIFO loaded 
1279
      } else {
1280
        // We have more bytes to send
1281
        bytes_to_write =
1282
          MIN (*ppend - *ppbegin, usbs_at91_endpoint_fifo_size[0]);
1283
        *ppbegin = write_fifo_uint8 (pFDR0, *ppbegin, (cyg_uint8 *)
1284
                                     ((cyg_uint32) *ppbegin + bytes_to_write));
1285
        // Send next few bytes 
1286
        if (*ppbegin == *ppend) { /* Control-Endoints don't need ACK's */
1287
          if (usbs_at91_ep0.fill_buffer_fn) { // More Records ?
1288
            (*usbs_at91_ep0.fill_buffer_fn) (&usbs_at91_ep0);
1289
 
1290
            *ppbegin = usbs_at91_ep0.buffer;
1291
            *ppend = *ppbegin + usbs_at91_ep0.buffer_size;
1292
 
1293
            /* Ready to send... */
1294
            bytes_to_write =
1295
              MIN (*ppend - *ppbegin,
1296
                   usbs_at91_endpoint_fifo_size[0] - bytes_to_write);
1297
 
1298
            *ppbegin = write_fifo_uint8 (pFDR0, *ppbegin, (cyg_uint8 *)
1299
                                         ((cyg_uint32) *ppbegin + bytes_to_write));
1300
            // Send next few bytes 
1301
          } else {
1302
            if (bytes_to_write == usbs_at91_endpoint_fifo_size[0]) {
1303
              // Last packet is full, so we need to send a zero bytes
1304
              // packet next time
1305
              status = EP0_LL_SEND_READY;
1306
            } else {
1307
              status = EP0_LL_IDLE;
1308
            }
1309
 
1310
          }
1311
        }
1312
        SET_BITS (pCSR0, AT91_UDP_CSR_TXPKTRDY);      // Signal FIFO loaded 
1313
      }
1314
      break;
1315
    case EP0_LL_RECEIVE_READY:
1316
      /* Maybe we have to send an ACK */
1317
      if (*ppbegin == *ppend) {   // All bytes are received, send ACK
1318
        status = EP0_LL_ACK;
1319
        SET_BITS (pCSR0, AT91_UDP_CSR_TXPKTRDY);      // Signal FIFO loaded 
1320
      }
1321
      break;
1322
    case EP0_LL_ACK:
1323
      if (req->request == USB_DEVREQ_SET_ADDRESS) {   // Special-processing 
1324
        HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_FADDR,
1325
                          req->value_lo | AT91_UDP_FADDR_FEN);
1326
        value = (req->value_hi << 8) | req->value_lo;
1327
        if (value) {
1328
          usbs_at91_ep0.state = USBS_STATE_ADDRESSED;
1329
        }
1330
      }
1331
 
1332
      if (usbs_at91_ep0.complete_fn) {
1333
        (*usbs_at91_ep0.complete_fn) (&usbs_at91_ep0,
1334
                                      USBS_CONTROL_RETURN_HANDLED);
1335
      }
1336
      status = EP0_LL_IDLE;
1337
      usbs_state_notify (&usbs_at91_ep0);
1338
      break;
1339
    default:
1340
      break;
1341
  }
1342
  return status;
1343
}
1344
 
1345
static void
1346
usbs_at91_control_dsr (void)
1347
{
1348
  static ep0_low_level_status_t status = EP0_LL_IDLE;
1349
 
1350
  while (!BITS_ARE_CLEARED(pCSR0,
1351
                           AT91_UDP_CSR_TXCOMP | AT91_UDP_CSR_RX_DATA_BK0 |
1352
                           AT91_UDP_CSR_RXSETUP | AT91_UDP_CSR_ISOERROR |
1353
                           AT91_UDP_CSR_RX_DATA_BK1)) {
1354
 
1355
    // Check and handle any error conditions
1356
    if (BITS_ARE_SET (pCSR0, AT91_UDP_CSR_ISOERROR)) {
1357
      status = usbs_at91_control_error(status);
1358
    }
1359
 
1360
    // Check for a setup message and handle it
1361
    if (BITS_ARE_SET (pCSR0, AT91_UDP_CSR_RXSETUP)) {
1362
      status = usbs_at91_control_setup(status);
1363
    }
1364
 
1365
    // Check for received data on the control endpoint
1366
    if (BITS_ARE_SET (pCSR0, AT91_UDP_CSR_RX_DATA_BK0)) {
1367
      status = usbs_at91_control_data_recv(status);
1368
    }
1369
 
1370
    // Check if the last packet has been sent
1371
    if (BITS_ARE_CLEARED (pCSR0, AT91_UDP_CSR_TXPKTRDY)) {
1372
      status = usbs_at91_control_data_sent(status);
1373
    }
1374
 
1375
    // Received an ACK packet
1376
    if (BITS_ARE_SET (pCSR0, AT91_UDP_CSR_TXCOMP)) {
1377
      CLEAR_BITS (pCSR0, AT91_UDP_CSR_TXCOMP);
1378
    }
1379
 
1380
    if (status == EP0_LL_STALL) {
1381
      CLEAR_BITS (pCSR0, 0x7f);
1382
      SET_BITS (pCSR0, AT91_UDP_CSR_FORCESTALL);
1383
    }
1384
  }
1385
}
1386
 
1387
static void
1388
usbs_at91_dsr (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
1389
{
1390
  cyg_uint8 n;
1391
 
1392
  CYG_ASSERT (CYGNUM_HAL_INTERRUPT_UDP == vector, "Wrong interrupts");
1393
  CYG_ASSERT (0 == data, "DSR needs no data");
1394
 
1395
  CLEAR_BITS (AT91_UDP + AT91_UDP_GLB_STATE, 0x10);
1396
 
1397
  if (BITS_ARE_SET (pISR, AT91_UDP_WAKEUP)) {
1398
    usbs_at91_ep0.state = USBS_STATE_DEFAULT;
1399
    usbs_state_notify (&usbs_at91_ep0);
1400
 
1401
    HAL_WRITE_UINT32 (pICR, AT91_UDP_WAKEUP);
1402
  }
1403
 
1404
  if (BITS_ARE_SET (pISR, AT91_UDP_ENDBUSRES)) {        // RESET UDP 
1405
    usbs_at91_ep0.state = USBS_STATE_POWERED;
1406
    usbs_state_notify (&usbs_at91_ep0);
1407
    usbs_at91_handle_reset ();
1408
 
1409
    HAL_WRITE_UINT32 (pCSR0, AT91_UDP_CSR_EPEDS | AT91_UDP_CSR_EPTYPE_CTRL);
1410
    HAL_WRITE_UINT32 (pIER, AT91_UDP_EPINT0);
1411
 
1412
    usbs_at91_ep0.state = USBS_STATE_DEFAULT;
1413
    usbs_state_notify (&usbs_at91_ep0);
1414
 
1415
    HAL_WRITE_UINT32 (pICR, AT91_UDP_ENDBUSRES);
1416
  }
1417
 
1418
  if (BITS_ARE_SET (pISR, AT91_UDP_SOFINT)) {
1419
    HAL_WRITE_UINT32 (pICR, AT91_UDP_SOFINT);
1420
  }
1421
 
1422
  if (BITS_ARE_SET (pISR, AT91_UDP_EXTRSM)) {
1423
    usbs_at91_ep0.state = usbs_at91_ep0.state & ~USBS_STATE_SUSPENDED;
1424
    usbs_state_notify (&usbs_at91_ep0);
1425
    HAL_WRITE_UINT32 (pICR, AT91_UDP_EXTRSM);
1426
  }
1427
 
1428
  if (BITS_ARE_SET (pISR, AT91_UDP_RXRSM)) {
1429
    usbs_at91_ep0.state = usbs_at91_ep0.state & ~USBS_STATE_SUSPENDED;
1430
    usbs_state_notify (&usbs_at91_ep0);
1431
    HAL_WRITE_UINT32 (pICR, AT91_UDP_RXRSM);
1432
  }
1433
 
1434
  if (BITS_ARE_SET (pISR, AT91_UDP_RXSUSP)) {
1435
    usbs_at91_ep0.state = usbs_at91_ep0.state | USBS_STATE_SUSPENDED;
1436
    usbs_state_notify (&usbs_at91_ep0);
1437
    HAL_WRITE_UINT32 (pICR, AT91_UDP_RXSUSP);
1438
  }
1439
 
1440
  if (BITS_ARE_SET (pISR, AT91_UDP_EPINT0)) {
1441
    usbs_at91_control_dsr ();
1442
  }
1443
 
1444
  for (n = 1; n < AT91_USB_ENDPOINTS; n++) {
1445
    if (*(cyg_uint32 *) pIMR & (1 << n)) {
1446
      usbs_at91_endpoint_dsr (n);
1447
    }
1448
  }
1449
 
1450
  cyg_drv_interrupt_unmask (vector);
1451
}
1452
 
1453
static cyg_uint32
1454
usbs_at91_isr (cyg_vector_t vector, cyg_addrword_t data)
1455
{
1456
  cyg_uint8 n;
1457
  bool need_dsr = false;
1458
  cyg_uint32 IMR;
1459
  cyg_uint32 ISR;
1460
 
1461
  CYG_ASSERT (CYGNUM_HAL_INTERRUPT_UDP == vector, "Wrong interrupts");
1462
  CYG_ASSERT (0 == data, "ISR needs no data");
1463
 
1464
  HAL_READ_UINT32(pIMR, IMR);
1465
  HAL_READ_UINT32(pISR, ISR);
1466
 
1467
  for (n = 1; n < AT91_USB_ENDPOINTS; n++) {
1468
    /* Do any data endpoint need a data transfer ? */
1469
    if (IMR & ISR & (1 << n)) {
1470
      need_dsr = usbs_at91_endpoint_isr (n) || need_dsr;
1471
    }
1472
  }
1473
  /* If we don't need any DSR re-enable interrupts and finish */
1474
  if (BITS_ARE_CLEARED (pISR, AT91_UDP_ALLOWED_IRQs & 0xffffff01)
1475
      && !need_dsr) {
1476
    cyg_drv_interrupt_acknowledge (vector);
1477
    return CYG_ISR_HANDLED;
1478
  }
1479
 
1480
  /* Call the DSR */
1481
  cyg_drv_interrupt_mask (vector);
1482
  cyg_drv_interrupt_acknowledge (vector);
1483
 
1484
  return CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
1485
}
1486
 
1487
 
1488
 
1489
// ----------------------------------------------------------------------------
1490
// Polling support. It is not clear that this is going to work particularly
1491
// well since according to the documentation the hardware does not generate
1492
// NAKs automatically - instead the ISR has to set the appropriate bits
1493
// sufficiently quickly to avoid confusing the host.
1494
//
1495
// Calling the isr directly avoids duplicating code, but means that
1496
// cyg_drv_interrupt_acknowledge() will get called when not inside a
1497
// real interrupt handler. This should be harmless.
1498
 
1499
static void
1500
usbs_at91_poll (usbs_control_endpoint * endpoint)
1501
{
1502
  CYG_ASSERT (endpoint == &usbs_at91_ep0, "Wrong endpoint");
1503
  if (CYG_ISR_CALL_DSR == usbs_at91_isr (CYGNUM_HAL_INTERRUPT_UDP, 0)) {
1504
    usbs_at91_dsr (CYGNUM_HAL_INTERRUPT_UDP, 0, 0);
1505
  }
1506
}
1507
 
1508
// ----------------------------------------------------------------------------
1509
// Initialization
1510
//
1511
// This routine gets called from a prioritized static constructor during
1512
// eCos startup.
1513
 
1514
void
1515
usbs_at91_init (void)
1516
{
1517
 
1518
  cyg_uint32 reg;
1519
 
1520
  HAL_READ_UINT32 (AT91_PMC + AT91_PMC_PLLR, reg);
1521
 
1522
  /* Set USB divider so we have a 48MHz clock */
1523
#if   ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED <  48120000) && \
1524
       (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED >  47880000))
1525
 
1526
  // 48MHz clock, divider set to 1
1527
  HAL_WRITE_UINT32 (AT91_PMC + AT91_PMC_PLLR,
1528
                    (reg & 0x0fffffff) | AT91_PMC_PLLR_USBDIV_1);
1529
 
1530
#elif ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED <  96240000) && \
1531
       (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED >  95760000))
1532
 
1533
  // 96MHz clock, divider set to 2
1534
  HAL_WRITE_UINT32 (AT91_PMC + AT91_PMC_PLLR,
1535
                    (reg & 0x0fffffff) | AT91_PMC_PLLR_USBDIV_2);
1536
#else
1537
#error CYGNUM_HAL_ARM_AT91_CLOCK_SPEED is not 48, 96 or 192MHz plusminus 0.25% ...
1538
#endif
1539
 
1540
  /* Enable USB clock */
1541
  HAL_WRITE_UINT32 (AT91_PMC + AT91_PMC_SCER, AT91_PMC_SCER_UDP);
1542
  HAL_WRITE_UINT32 (AT91_PMC + AT91_PMC_PCER, AT91_PMC_PCER_UDP);
1543
 
1544
  usbs_at91_set_pullup (false);
1545
#ifndef CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN_NONE
1546
  HAL_ARM_AT91_GPIO_CFG_DIRECTION(CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN,
1547
                                  AT91_PIN_OUT);
1548
#endif
1549
#ifndef CYGDAT_DEVS_USB_AT91_GPIO_READ_POWER_PIN_NONE
1550
  HAL_ARM_AT91_GPIO_CFG_DIRECTION(CYGDAT_DEVS_USB_AT91_GPIO_READ_POWER_PIN,
1551
                                  AT91_PIN_IN);
1552
#endif
1553
  usbs_at91_reset_device ();
1554
 
1555
  cyg_drv_interrupt_create (CYGNUM_HAL_INTERRUPT_UDP,
1556
                            6,  // priority
1557
                            0,  // data
1558
                            &usbs_at91_isr,
1559
                            &usbs_at91_dsr,
1560
                            &usbs_at91_intr_handle, &usbs_at91_intr_data);
1561
 
1562
  cyg_drv_interrupt_attach (usbs_at91_intr_handle);
1563
  cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_UDP);
1564
 
1565
  usbs_at91_ep0.state = USBS_STATE_POWERED;
1566
  usbs_state_notify (&usbs_at91_ep0);
1567
}
1568
 
1569
// ----------------------------------------------------------------------------
1570
// Testing support.
1571
usbs_testing_endpoint usbs_testing_endpoints[] = {
1572
    {
1573
        endpoint_type       : USB_ENDPOINT_DESCRIPTOR_ATTR_CONTROL,
1574
        endpoint_number     : 0,
1575
        endpoint_direction  : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
1576
        endpoint            : (void*) &usbs_at91_ep0,
1577
#ifdef CYGVAR_DEVS_USB_AT91_EP0_DEVTAB_ENTRY
1578
        devtab_entry        : CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "0c",
1579
#else        
1580
        devtab_entry        : (const char*) 0,
1581
#endif        
1582
        min_size            : 1,            // zero-byte control transfers are meaningless
1583
        max_size            : 0x0FFFF,      // limit imposed by protocol
1584
        max_in_padding      : 0,
1585
        alignment           : 0
1586
    },
1587
    {
1588
        endpoint_type       : USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
1589
        endpoint_number     : 1,
1590
        endpoint_direction  : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_OUT,
1591
        endpoint            : (void*) &usbs_at91_ep1,
1592
#ifdef CYGVAR_DEVS_USB_AT91_EP1_DEVTAB_ENTRY
1593
        devtab_entry        : CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "1r",
1594
#else        
1595
        devtab_entry        : (const char*) 0,
1596
#endif        
1597
        min_size            : 1,
1598
        max_size            : -1,           // No hardware or driver limitation
1599
        max_in_padding      : 0,
1600
        alignment           : 0
1601
    },
1602
    {
1603
        endpoint_type       : USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
1604
        endpoint_number     : 2,
1605
        endpoint_direction  : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
1606
        endpoint            : (void*) &usbs_at91_ep2,
1607
#ifdef CYGVAR_DEVS_USB_AT91_EP2_DEVTAB_ENTRY
1608
        devtab_entry        : CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "2w",
1609
#else        
1610
        devtab_entry        : (const char*) 0,
1611
#endif        
1612
        min_size            : 1,
1613
        max_size            : -1,           // No hardware or driver limitation
1614
        max_in_padding      : 1,            // hardware limitation
1615
        alignment           : 0
1616
    },
1617
    {
1618
        endpoint_type       : USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
1619
        endpoint_number     : 3,
1620
        endpoint_direction  : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
1621
        endpoint            : (void*) &usbs_at91_ep3,
1622
#ifdef CYGVAR_DEVS_USB_AT91_EP3_DEVTAB_ENTRY
1623
        devtab_entry        : CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "3w",
1624
#else        
1625
        devtab_entry        : (const char*) 0,
1626
#endif        
1627
        min_size            : 1,
1628
        max_size            : -1,           // No hardware or driver limitation
1629
        max_in_padding      : 1,            // hardware limitation
1630
        alignment           : 0
1631
    },
1632
    USBS_TESTING_ENDPOINTS_TERMINATOR
1633
};

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