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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [aeb/] [current/] [include/] [hal_platform_setup.h] - Blame information for rev 786

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1 786 skrzyp
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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#define CYGONCE_HAL_PLATFORM_SETUP_H
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/*=============================================================================
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//
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//      hal_platform_setup.h
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//
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//      Platform specific support for HAL (assembly code)
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    gthomas
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// Contributors: gthomas
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// Date:        1999-04-13
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// Purpose:     ARM/AEB-1 platform specific support routines
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// Description:
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// Usage:       #include <cyg/hal/hal_platform_setup.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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// From <cyg/hal/hal_cache.h> Need to make that file assembly safe.
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#define CYG_DEVICE_CCR          0xFFFFA400
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#define CCR_I                   0x08      // Invalidate mode
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#if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096
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// Override default to a more sensible value
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#undef  CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
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#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
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#endif
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#ifdef CYGHWR_HAL_ARM_AEB_REVISION_C
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// AEB rev C has 256kB of memory. Cache is working (set cachable)
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#define AEB_SRAM .long  0xFFFFA008,0x00008000,0x00048000,0x00007c04
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#define AEB_BAD  .long  0xFFFFA00C,0x00048000,0x01000000,0x00000000
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#define AEB_CACHE .long 0xFFFFA010,0x60000000,0x61000000,0x00007801
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#else
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// AEB rev B has 128kB of memory. Cache is broken (clear cachable)
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#define AEB_SRAM .long  0xFFFFA008,0x00008000,0x00028000,0x00007804
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#define AEB_BAD  .long  0xFFFFA00C,0x00028000,0x01000000,0x00000000
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#define AEB_CACHE .long 0xFFFFA010,0x60000000,0x61000000,0x00007801
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#endif
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#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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#define PLATFORM_SETUP1                                                       \
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        ldr     r1,=CYG_DEVICE_CCR                                           ;\
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        mov     r2,#CCR_I                                                    ;\
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        strb    r2,[r1,#0]      /* invalidate... */                          ;\
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        mov     r2,#0                                                        ;\
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        strb    r2,[r1,#0]      /* and disable the cache. */                 ;\
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        ldr     r1,=segment_register_setups                                  ;\
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10:     ldr     r2,[r1,#0]      /* segment address */                        ;\
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        cmp     r2,#0                                                        ;\
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        beq     20f                                                          ;\
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        ldr     r3,[r1,#4]      /* segment start */                          ;\
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        str     r3,[r2,#0x00]                                                ;\
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        ldr     r3,[r1,#8]      /* segment end */                            ;\
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        str     r3,[r2,#0x20]                                                ;\
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        ldr     r3,[r1,#12]     /* segment flags */                          ;\
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        str     r3,[r2,#0x40]                                                ;\
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        add     r1,r1,#16       /* next segment  */                          ;\
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        b       10b                                                          ;\
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segment_register_setups:                                                     ;\
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        AEB_SRAM  /* segment 2 */                                            ;\
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        AEB_BAD   /* segment 3 */                                            ;\
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        AEB_CACHE /* segment 1 */                                            ;\
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        .long 0                                                              ;\
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20:
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#else
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#define PLATFORM_SETUP1
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#endif
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/*---------------------------------------------------------------------------*/
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/* end of hal_platform_setup.h                                               */
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#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */

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