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skrzyp |
#ifndef CYGONCE_HAL_PLF_IO_H
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#define CYGONCE_HAL_PLF_IO_H
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//=============================================================================
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//
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// plf_io.h
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//
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// Platform specific registers
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors:jskov
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// Date: 2001-03-16
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// Purpose: ARM/KS32C platform specific registers
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// Description:
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// Usage: #include <cyg/hal/plf_io.h>
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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// Platform doesn't need address munging even if configures as big-endian
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#define HAL_IO_MACROS_NO_ADDRESS_MUNGING
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// non-caching by accessing addr|0x04000000
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#define KS32C_REG_BASE 0x07ff0000
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// -----------------------------------------------------------------------------
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// System config (register bases and caching)
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#define KS32C_SYSCFG (KS32C_REG_BASE + 0x0000)
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#define KS32C_SYSCFG_SDM 0x80000000
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#define KS32C_SYSCFG_PD_ID_MASK 0x3c000000
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#define KS32C_SYSCFG_SRBBP_MASK 0x03ff0000 // address/64k
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#define KS32C_SYSCFG_ISBBP_MASK 0x0000ffc0 // a25-a16
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#define KS32C_SYSCFG_CM_MASK 0x00000030
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#define KS32C_SYSCFG_CM_4R_4C 0x00000000
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#define KS32C_SYSCFG_CM_0R_8C 0x00000010
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#define KS32C_SYSCFG_CM_8R_0C 0x00000020
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#define KS32C_SYSCFG_WE 0x00000004 // only KS32C50100?
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#define KS32C_SYSCFG_CE 0x00000002
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#define KS32C_SYSCFG_SE 0x00000001
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#define KS32C_CLKCON (KS32C_REG_BASE + 0x3000)
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#define KS32C_EXTACON0 (KS32C_REG_BASE + 0x3008)
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#define KS32C_EXTACON1 (KS32C_REG_BASE + 0x300c)
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#define KS32C_EXTACON0_EXT0_shift 0
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#define KS32C_EXTACON0_EXT1_shift 16
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#define KS32C_EXTACON1_EXT2_shift 0
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#define KS32C_EXTACON1_EXT3_shift 16
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#define KS32C_EXTACON_TCOS_shift 0
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#define KS32C_EXTACON_TACS_shift 3
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#define KS32C_EXTACON_TCOH_shift 6
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#define KS32C_EXTACON_TACC_shift 9
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#define KS32C_EXTACON_INIT(_tacs_,_tcos_,_tacc_,_tcoh_) \
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( ((_tacs_)<<KS32C_EXTACON_TACS_shift) \
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| ((_tcos_)<<KS32C_EXTACON_TCOS_shift) \
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| ((_tacc_)<<KS32C_EXTACON_TACC_shift) \
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| ((_tcoh_)<<KS32C_EXTACON_TCOH_shift) )
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// Memory banks data width
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#define KS32C_EXTDBWTH (KS32C_REG_BASE + 0x3010)
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#define KS32C_EXTDBWTH_MASK 3
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#define KS32C_EXTDBWTH_8BIT 1
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#define KS32C_EXTDBWTH_16BIT 2
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#define KS32C_EXTDBWTH_32BIT 3
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#define KS32C_EXTDBWTH_DSR0_shift 0
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#define KS32C_EXTDBWTH_DSR1_shift 2
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#define KS32C_EXTDBWTH_DSR2_shift 4
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#define KS32C_EXTDBWTH_DSR3_shift 6
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#define KS32C_EXTDBWTH_DSR4_shift 8
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#define KS32C_EXTDBWTH_DSR5_shift 10
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#define KS32C_EXTDBWTH_DSD0_shift 12
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#define KS32C_EXTDBWTH_DSD1_shift 14
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#define KS32C_EXTDBWTH_DSD2_shift 16
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#define KS32C_EXTDBWTH_DSD3_shift 18
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#define KS32C_EXTDBWTH_DSX0_shift 20
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#define KS32C_EXTDBWTH_DSX1_shift 22
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#define KS32C_EXTDBWTH_DSX2_shift 24
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#define KS32C_EXTDBWTH_DSX3_shift 26
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// -----------------------------------------------------------------------------
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// Bank locations and timing
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#define KS32C_ROMCON0 (KS32C_REG_BASE + 0x3014)
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#define KS32C_ROMCON1 (KS32C_REG_BASE + 0x3018)
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#define KS32C_ROMCON2 (KS32C_REG_BASE + 0x301c)
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#define KS32C_ROMCON3 (KS32C_REG_BASE + 0x3020)
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#define KS32C_ROMCON4 (KS32C_REG_BASE + 0x3024)
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#define KS32C_ROMCON5 (KS32C_REG_BASE + 0x3028)
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#define KS32C_ROMCON_PMC_MASK 0x00000003
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#define KS32C_ROMCON_PMC_ROM 0x00000000
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#define KS32C_ROMCON_PMC_4W_PAGE 0x00000001
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#define KS32C_ROMCON_PMC_8W_PAGE 0x00000002
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#define KS32C_ROMCON_PMC_16W_PAGE 0x00000003
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#define KS32C_ROMCON_TPA_MASK 0x0000000c
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#define KS32C_ROMCON_TPA_5C 0x00000000
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#define KS32C_ROMCON_TPA_2C 0x00000004
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#define KS32C_ROMCON_TPA_3C 0x00000008
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#define KS32C_ROMCON_TPA_4C 0x0000000c
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#define KS32C_ROMCON_TACC_MASK 0x00000070
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#define KS32C_ROMCON_TACC_DISABLE 0x00000000
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#define KS32C_ROMCON_TACC_2C 0x00000010
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#define KS32C_ROMCON_TACC_3C 0x00000020
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#define KS32C_ROMCON_TACC_4C 0x00000030
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#define KS32C_ROMCON_TACC_5C 0x00000040
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#define KS32C_ROMCON_TACC_6C 0x00000050
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#define KS32C_ROMCON_TACC_7C 0x00000060
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#define KS32C_ROMCON_BASE_MASK 0x000ffc00
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#define KS32C_ROMCON_BASE_shift 10
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#define KS32C_ROMCON_NEXT_MASK 0x3ff00000
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#define KS32C_ROMCON_NEXT_shift 20
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#define KS32C_DRAMCON0 (KS32C_REG_BASE + 0x302c)
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#define KS32C_DRAMCON1 (KS32C_REG_BASE + 0x3030)
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#define KS32C_DRAMCON2 (KS32C_REG_BASE + 0x3034)
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#define KS32C_DRAMCON3 (KS32C_REG_BASE + 0x3038)
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#define KS32C_DRAMCON_CAN_8 0x00000000
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#define KS32C_DRAMCON_CAN_9 0x40000000
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#define KS32C_DRAMCON_CAN_10 0x80000000
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#define KS32C_DRAMCON_CAN_11 0xc0000000
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#define KS32C_DRAMCON_TRP_1C 0x00000000
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#define KS32C_DRAMCON_TRP_2C 0x00000100
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#define KS32C_DRAMCON_TRP_3C 0x00000200
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#define KS32C_DRAMCON_TRP_4C 0x00000300
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#define KS32C_DRAMCON_TRC_1C 0x00000000
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#define KS32C_DRAMCON_TRC_2C 0x00000080
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#define KS32C_DRAMCON_RESERVED 0x00000010
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#define KS32C_DRAMCON_TCP_1C 0x00000000
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#define KS32C_DRAMCON_TCP_2C 0x00000008
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#define KS32C_DRAMCON_TCS_1C 0x00000000
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#define KS32C_DRAMCON_TCS_2C 0x00000002
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#define KS32C_DRAMCON_TCS_3C 0x00000004
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#define KS32C_DRAMCON_TCS_4C 0x00000006
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#define KS32C_DRAMCON_EDO 0x00000001
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#define KS32C_DRAMCON_BASE_MASK 0x000ffc00
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#define KS32C_DRAMCON_BASE_shift 10
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#define KS32C_DRAMCON_NEXT_MASK 0x3ff00000
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#define KS32C_DRAMCON_NEXT_shift 20
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#define KS32C_REFEXTCON (KS32C_REG_BASE + 0x303c)
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// DRAM
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#define KS32C_REFEXTCON_TCSR_1C 0x00000000
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#define KS32C_REFEXTCON_TCHR_1C 0x00000000
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// SDRAM
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#define KS32C_REFEXTCON_TRC_4C 0x00060000
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// DRAM+SDRAM
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#define KS32C_REFEXTCON_REN 0x00010000
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#define KS32C_REFEXTCON_VSF 0x00008000
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#define KS32C_REFEXTCON_BASE 0x00000360
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#define KS32C_REFEXTCON_RCV_shift 21
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//-----------------------------------------------------------------------------
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// INTC
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#define KS32C_INTMOD (KS32C_REG_BASE + 0x4000)
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#define KS32C_INTPND (KS32C_REG_BASE + 0x4004)
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#define KS32C_INTMSK (KS32C_REG_BASE + 0x4008)
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#define KS32C_INTPRI0 (KS32C_REG_BASE + 0x400c)
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#define KS32C_INTPRI1 (KS32C_REG_BASE + 0x4010)
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#define KS32C_INTPRI2 (KS32C_REG_BASE + 0x4014)
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#define KS32C_INTPRI3 (KS32C_REG_BASE + 0x4018)
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#define KS32C_INTPRI4 (KS32C_REG_BASE + 0x401c)
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#define KS32C_INTPRI5 (KS32C_REG_BASE + 0x4020)
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#define KS32C_INTOFFSET (KS32C_REG_BASE + 0x4024)
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#define KS32C_PNDPRI (KS32C_REG_BASE + 0x4028)
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#define KS32C_PNDTEST (KS32C_REG_BASE + 0x402c)
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#define KS32C_INTOFFSET_FIQ (KS32C_REG_BASE + 0x4030)
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#define KS32C_INTOFFSET_IRQ (KS32C_REG_BASE + 0x4034)
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#define KS32C_INTMSK_GLOBAL (1<<21)
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//-----------------------------------------------------------------------------
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// PIO
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#define KS32C_IOPMOD (KS32C_REG_BASE + 0x5000)
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#define KS32C_IOPCON (KS32C_REG_BASE + 0x5004)
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#define KS32C_IOPCON_XIRQ_MASK 0x1f
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#define KS32C_IOPCON_XIRQ_LEVEL 0x00
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#define KS32C_IOPCON_XIRQ_RISING 0x01
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#define KS32C_IOPCON_XIRQ_FALLING 0x02
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#define KS32C_IOPCON_XIRQ_BOTH_EDGE 0x03
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#define KS32C_IOPCON_XIRQ_FILTERING 0x04
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#define KS32C_IOPCON_XIRQ_AKTIV_LOW 0x00
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#define KS32C_IOPCON_XIRQ_AKTIV_HI 0x08
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#define KS32C_IOPCON_XIRQ_ENABLE 0x10
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#define KS32C_IOPCON_XIRQ0_shift 0
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#define KS32C_IOPCON_XIRQ1_shift 5
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#define KS32C_IOPCON_XIRQ2_shift 10
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#define KS32C_IOPCON_XIRQ3_shift 15
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#define KS32C_IOPCON_DRQ_MASK 0x07
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#define KS32C_IOPCON_DRQ_AKTIV_LOW 0x00
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#define KS32C_IOPCON_DRQ_AKTIV_HI 0x01
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#define KS32C_IOPCON_DRQ_FILTERING 0x02
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#define KS32C_IOPCON_DRQ_ENABLE 0x04
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#define KS32C_IOPCON_DRQ0_shift 20
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#define KS32C_IOPCON_DRQ1_shift 23
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#define KS32C_IOPCON_DAK_MASK 0x03
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#define KS32C_IOPCON_DAK_AKTIV_LOW 0x00
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#define KS32C_IOPCON_DAK_AKTIV_HI 0x01
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#define KS32C_IOPCON_DAK_ENABLE 0x02
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#define KS32C_IOPCON_DAK0_shift 26
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#define KS32C_IOPCON_DAK1_shift 28
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#define KS32C_IOPCON_TOEN_ENABLE 0x01
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#define KS32C_IOPCON_TO0_shift 30
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#define KS32C_IOPCON_TO1_shift 31
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#define KS32C_IOPDATA (KS32C_REG_BASE + 0x5008)
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#define KS32C_IOPDATA_P0 (1<<0)
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#define KS32C_IOPDATA_P1 (1<<1)
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#define KS32C_IOPDATA_P2 (1<<2)
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#define KS32C_IOPDATA_P3 (1<<3)
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#define KS32C_IOPDATA_P4 (1<<4)
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#define KS32C_IOPDATA_P5 (1<<5)
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#define KS32C_IOPDATA_P6 (1<<6)
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#define KS32C_IOPDATA_P7 (1<<7)
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#define KS32C_IOPDATA_P8_XIRQ0 (1<<8)
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#define KS32C_IOPDATA_P9_XIRQ1 (1<<9)
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#define KS32C_IOPDATA_P10_XIRQ2 (1<<10)
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#define KS32C_IOPDATA_P11_XIRQ3 (1<<11)
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#define KS32C_IOPDATA_P12_DRQ0 (1<<12)
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#define KS32C_IOPDATA_P13_DRQ1 (1<<13)
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#define KS32C_IOPDATA_P14_DAK0 (1<<14)
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#define KS32C_IOPDATA_P15_DAK1 (1<<15)
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#define KS32C_IOPDATA_P16_TO0 (1<<16)
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#define KS32C_IOPDATA_P17_TO1 (1<<17)
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//-----------------------------------------------------------------------------
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// Timers
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#define KS32C_TMOD (KS32C_REG_BASE + 0x6000)
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294 |
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#define KS32C_TDATA0 (KS32C_REG_BASE + 0x6004)
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295 |
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#define KS32C_TDATA1 (KS32C_REG_BASE + 0x6008)
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296 |
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#define KS32C_TCNT0 (KS32C_REG_BASE + 0x600c)
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297 |
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#define KS32C_TCNT1 (KS32C_REG_BASE + 0x6010)
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298 |
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|
299 |
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#define KS32C_TMOD_TE0 0x00000001
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300 |
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#define KS32C_TMOD_TMD0 0x00000002
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301 |
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#define KS32C_TMOD_TCLR0 0x00000004
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302 |
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#define KS32C_TMOD_TE1 0x00000008
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303 |
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#define KS32C_TMOD_TMD1 0x00000010
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304 |
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#define KS32C_TMOD_TCLR1 0x00000020
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305 |
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306 |
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307 |
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//-----------------------------------------------------------------------------
|
308 |
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// UART
|
309 |
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|
310 |
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#define KS32C_UART0_BASE (KS32C_REG_BASE + 0xd000)
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311 |
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#define KS32C_UART1_BASE (KS32C_REG_BASE + 0xe000)
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312 |
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313 |
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#define KS32C_UART_LCON 0x0000
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314 |
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#define KS32C_UART_CON 0x0004
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315 |
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#define KS32C_UART_STAT 0x0008
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316 |
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#define KS32C_UART_TXBUF 0x000c
|
317 |
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#define KS32C_UART_RXBUF 0x0010
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318 |
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#define KS32C_UART_BRDIV 0x0014
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319 |
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#define KS32C_UART_BRDCNT 0x0018
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320 |
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#define KS32C_UART_BRDCLK 0x001c
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321 |
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322 |
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#define KS32C_UART_LCON_5_DBITS 0x00
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323 |
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#define KS32C_UART_LCON_6_DBITS 0x01
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324 |
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#define KS32C_UART_LCON_7_DBITS 0x02
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325 |
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#define KS32C_UART_LCON_8_DBITS 0x03
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326 |
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#define KS32C_UART_LCON_1_SBITS 0x00
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#define KS32C_UART_LCON_2_SBITS 0x04
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328 |
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#define KS32C_UART_LCON_NO_PARITY 0x00
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#define KS32C_UART_LCON_EVEN_PARITY 0x00
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330 |
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#define KS32C_UART_LCON_ODD_PARITY 0x28
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331 |
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#define KS32C_UART_LCON_1_PARITY 0x30
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332 |
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#define KS32C_UART_LCON_0_PARITY 0x38
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333 |
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#define KS32C_UART_LCON_SCS 0x40
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334 |
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#define KS32C_UART_LCON_IR 0x80
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335 |
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336 |
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#define KS32C_UART_CON_RXM_MASK 0x03
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337 |
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#define KS32C_UART_CON_RXM_INT 0x01
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338 |
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#define KS32C_UART_CON_TXM_MASK 0x0c
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339 |
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#define KS32C_UART_CON_TXM_INT 0x08
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340 |
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#define KS32C_UART_CON_RX_ERR_INT 0x04
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341 |
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342 |
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343 |
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#define KS32C_UART_STAT_DTR 0x10
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344 |
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#define KS32C_UART_STAT_RDR 0x20
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345 |
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#define KS32C_UART_STAT_TXE 0x40 // tx empty
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346 |
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#define KS32C_UART_STAT_TC 0x80 // tx complete
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347 |
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|
348 |
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//-----------------------------------------------------------------------------
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349 |
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// Cache
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350 |
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#define KS32C_CACHE_SET0_ADDR 0x10000000
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351 |
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#define KS32C_CACHE_SET1_ADDR 0x10800000
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352 |
|
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#define KS32C_CACHE_TAG_ADDR 0x11000000
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353 |
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|
354 |
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//-----------------------------------------------------------------------------
|
355 |
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// GDMA
|
356 |
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#define KS32C_GDMA_CON0 (KS32C_REG_BASE + 0xb000)
|
357 |
|
|
#define KS32C_GDMA_SRC0 (KS32C_REG_BASE + 0xb004)
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358 |
|
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#define KS32C_GDMA_DST0 (KS32C_REG_BASE + 0xb008)
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359 |
|
|
#define KS32C_GDMA_CNT0 (KS32C_REG_BASE + 0xb00c)
|
360 |
|
|
#define KS32C_GDMA_CON1 (KS32C_REG_BASE + 0xc000)
|
361 |
|
|
#define KS32C_GDMA_SRC1 (KS32C_REG_BASE + 0xc004)
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362 |
|
|
#define KS32C_GDMA_DST1 (KS32C_REG_BASE + 0xc008)
|
363 |
|
|
#define KS32C_GDMA_CNT1 (KS32C_REG_BASE + 0xc00c)
|
364 |
|
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|
365 |
|
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//-----------------------------------------------------------------------------
|
366 |
|
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// I2C
|
367 |
|
|
#define KS32C_I2CCON (KS32C_REG_BASE + 0xf000)
|
368 |
|
|
#define KS32C_I2C_CON_BF (1<<0)
|
369 |
|
|
#define KS32C_I2C_CON_IEN (1<<1)
|
370 |
|
|
#define KS32C_I2C_CON_LRB (1<<2)
|
371 |
|
|
#define KS32C_I2C_CON_ACK (1<<3)
|
372 |
|
|
#define KS32C_I2C_CON_START (1<<4)
|
373 |
|
|
#define KS32C_I2C_CON_STOP (2<<4)
|
374 |
|
|
#define KS32C_I2C_CON_RESTART (3<<4)
|
375 |
|
|
#define KS32C_I2C_CON_BUSY (1<<6)
|
376 |
|
|
#define KS32C_I2C_CON_RESET (1<<7)
|
377 |
|
|
#define KS32C_I2CBUF (KS32C_REG_BASE +0xf004)
|
378 |
|
|
#define KS32C_I2CPS (KS32C_REG_BASE +0xf008)
|
379 |
|
|
|
380 |
|
|
#define KS32C_I2C_FREQ(freq) ((CYGNUM_HAL_CPUCLOCK/(freq) - 3)/16)
|
381 |
|
|
#define KS32C_I2C_RD (0x01)
|
382 |
|
|
#define KS32C_I2C_WR (0x00)
|
383 |
|
|
|
384 |
|
|
#ifndef __ASSEMBLER__
|
385 |
|
|
typedef struct hal_ks32c_i2c_msg_s
|
386 |
|
|
{
|
387 |
|
|
cyg_uint8 devaddr;
|
388 |
|
|
cyg_int8 status;
|
389 |
|
|
cyg_uint8* pbuf;
|
390 |
|
|
cyg_uint32 bufsize;
|
391 |
|
|
} hal_ks32c_i2c_msg_t;
|
392 |
|
|
|
393 |
|
|
// Transfer the I2C messages.
|
394 |
|
|
externC int
|
395 |
|
|
hal_ks32c_i2c_transfer(cyg_uint32 nmsg, hal_ks32c_i2c_msg_t* pmsgs);
|
396 |
|
|
#endif
|
397 |
|
|
|
398 |
|
|
//-----------------------------------------------------------------------------
|
399 |
|
|
// Memory map is 1-1
|
400 |
|
|
|
401 |
|
|
#define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_)
|
402 |
|
|
|
403 |
|
|
//-----------------------------------------------------------------------------
|
404 |
|
|
// AIM 711 specific
|
405 |
|
|
|
406 |
|
|
// Mamory maping
|
407 |
|
|
#define AIM711_ROM0_LA_START 0x02000000
|
408 |
|
|
#define AIM711_ROM0_LA_END 0x02200000
|
409 |
|
|
#define AIM711_DRAM_LA_START 0x00000000
|
410 |
|
|
#define AIM711_DRAM_LA_END 0x00800000
|
411 |
|
|
#define AIM711_EXT0_LA_START 0x03fd0000
|
412 |
|
|
#define AIM711_EXT0_LA_END 0x03fd4000
|
413 |
|
|
#define AIM711_EXT1_LA_START 0x03fd4000
|
414 |
|
|
#define AIM711_EXT1_LA_END 0x03fd8000
|
415 |
|
|
#define AIM711_EXT2_LA_START 0x03fd8000
|
416 |
|
|
#define AIM711_EXT2_LA_END 0x03fdc000
|
417 |
|
|
#define AIM711_EXT3_LA_START 0x03fdc000
|
418 |
|
|
#define AIM711_EXT3_LA_END 0x03fc0000
|
419 |
|
|
|
420 |
|
|
#define AIM711_COM0_DEBUG_BASE KS32C_UART0_BASE
|
421 |
|
|
#define AIM711_COM1_BASE (AIM711_EXT0_LA_START|0x04000000 + 8)
|
422 |
|
|
#define AIM711_COM2_BASE KS32C_UART1_BASE
|
423 |
|
|
#define AIM711_EXTBUS_BASE (AIM711_EXT2_LA_START|0x04000000)
|
424 |
|
|
|
425 |
|
|
// I2C address of RTC (wallclock)
|
426 |
|
|
#define AIM711_RTC_ADDR 0xd0
|
427 |
|
|
|
428 |
|
|
// I2C address and size of EEPROM
|
429 |
|
|
#define AIM711_EEPROM_ADDR 0xa0
|
430 |
|
|
#define AIM711_EEPROM_SIZE 256
|
431 |
|
|
#define AIM711_EEPROM_PAGESIZE 8
|
432 |
|
|
|
433 |
|
|
// Interrupt vectors with AIM 711 naming
|
434 |
|
|
#define AIM711_INTERRUPT_COM1 CYGNUM_HAL_INTERRUPT_EXT0
|
435 |
|
|
#define AIM711_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_EXT1
|
436 |
|
|
#define AIM711_INTERRUPT_IRQ0 CYGNUM_HAL_INTERRUPT_EXT2
|
437 |
|
|
#define AIM711_INTERRUPT_IRQ1 CYGNUM_HAL_INTERRUPT_EXT3
|
438 |
|
|
|
439 |
|
|
// GPIO bits with AIM 711 naming
|
440 |
|
|
#define AIM711_GPIO_LED0 KS32C_IOPDATA_P0
|
441 |
|
|
#define AIM711_GPIO_LED1 KS32C_IOPDATA_P1
|
442 |
|
|
#define AIM711_GPIO_LED2 KS32C_IOPDATA_P2
|
443 |
|
|
#define AIM711_GPIO_RESET KS32C_IOPDATA_P3
|
444 |
|
|
#define AIM711_GPIO_POWERLED KS32C_IOPDATA_P4
|
445 |
|
|
#define AIM711_GPIO_UARTIRQ KS32C_IOPDATA_P8_XIRQ0
|
446 |
|
|
#define AIM711_GPIO_RTCIRQ KS32C_IOPDATA_P9_XIRQ1
|
447 |
|
|
#define AIM711_GPIO_DIN0_DRQ0 KS32C_IOPDATA_P12_DRQ0
|
448 |
|
|
#define AIM711_GPIO_DIN1_DRQ1 KS32C_IOPDATA_P13_DRQ1
|
449 |
|
|
#define AIM711_GPIO_DIN2_IRQ0 KS32C_IOPDATA_P10_XIRQ2
|
450 |
|
|
#define AIM711_GPIO_DIN3_IRQ1 KS32C_IOPDATA_P11_XIRQ3
|
451 |
|
|
#define AIM711_GPIO_DOUT0_DAK0 KS32C_IOPDATA_P14_DAK0
|
452 |
|
|
#define AIM711_GPIO_DOUT1_DAK1 KS32C_IOPDATA_P15_DAK1
|
453 |
|
|
#define AIM711_GPIO_DOUT2_TO0 KS32C_IOPDATA_P16_TO0
|
454 |
|
|
#define AIM711_GPIO_DOUT3_TO1 KS32C_IOPDATA_P17_TO1
|
455 |
|
|
|
456 |
|
|
// Macros for usage of GPIO
|
457 |
|
|
#define AIM711_GPIO(_which_,_value_) \
|
458 |
|
|
do { \
|
459 |
|
|
cyg_uint32 val; \
|
460 |
|
|
HAL_READ_UINT32(KS32C_IOPDATA, val); \
|
461 |
|
|
val &= ~(_which_); \
|
462 |
|
|
val |= (_which_)&(_value_); \
|
463 |
|
|
HAL_WRITE_UINT32(KS32C_IOPDATA, val); \
|
464 |
|
|
} while (0)
|
465 |
|
|
|
466 |
|
|
#define AIM711_GPIO_SET(_x_) \
|
467 |
|
|
do { \
|
468 |
|
|
cyg_uint32 val; \
|
469 |
|
|
HAL_READ_UINT32(KS32C_IOPDATA, val); \
|
470 |
|
|
val |= (_x_); \
|
471 |
|
|
HAL_WRITE_UINT32(KS32C_IOPDATA, val); \
|
472 |
|
|
} while (0)
|
473 |
|
|
|
474 |
|
|
#define AIM711_GPIO_CLR(_x_) \
|
475 |
|
|
do { \
|
476 |
|
|
cyg_uint32 val; \
|
477 |
|
|
HAL_READ_UINT32(KS32C_IOPDATA, val); \
|
478 |
|
|
val &= ~(_x_); \
|
479 |
|
|
HAL_WRITE_UINT32(KS32C_IOPDATA, val); \
|
480 |
|
|
} while (0)
|
481 |
|
|
|
482 |
|
|
#define AIM711_GPIO_GET(_x_) \
|
483 |
|
|
do { \
|
484 |
|
|
cyg_uint32 _val; \
|
485 |
|
|
HAL_READ_UINT32(KS32C_IOPDATA, _val); \
|
486 |
|
|
(_x_) = _val; \
|
487 |
|
|
} while (0)
|
488 |
|
|
|
489 |
|
|
//-----------------------------------------------------------------------------
|
490 |
|
|
// AIM 711 specific EEPROM support
|
491 |
|
|
|
492 |
|
|
#ifndef __ASSEMBLER__
|
493 |
|
|
externC int
|
494 |
|
|
hal_aim711_eeprom_read(cyg_uint8 *buf, int offset, int len);
|
495 |
|
|
|
496 |
|
|
externC int
|
497 |
|
|
hal_aim711_eeprom_write(cyg_uint8 *buf, int offset, int len);
|
498 |
|
|
#endif
|
499 |
|
|
|
500 |
|
|
//-----------------------------------------------------------------------------
|
501 |
|
|
// end of plf_io.h
|
502 |
|
|
#endif // CYGONCE_HAL_PLF_IO_H
|