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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [arm9/] [excalibur/] [current/] [src/] [hal_diag.c] - Blame information for rev 786

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1 786 skrzyp
//=============================================================================
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//
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//      hal_diag.c
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//
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//      HAL diagnostic output code
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####                                            
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// -------------------------------------------                              
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// This file is part of eCos, the Embedded Configurable Operating System.   
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under    
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// the terms of the GNU General Public License as published by the Free     
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// Software Foundation; either version 2 or (at your option) any later      
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// version.                                                                 
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT      
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
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// for more details.                                                        
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//
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// You should have received a copy of the GNU General Public License        
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// along with eCos; if not, write to the Free Software Foundation, Inc.,    
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
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//
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// As a special exception, if other files instantiate templates or use      
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// macros or inline functions from this file, or you compile this file      
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// and link it with other works to produce a work based on this file,       
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// this file does not by itself cause the resulting work to be covered by   
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// the GNU General Public License. However the source code for this file    
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// must still be made available in accordance with section (3) of the GNU   
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// General Public License v2.                                               
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//
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// This exception does not invalidate any other reasons why a work based    
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// on this file might be covered by the GNU General Public License.         
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// -------------------------------------------                              
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// ####ECOSGPLCOPYRIGHTEND####                                              
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):   jskov
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// Contributors:jskov
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// Date:        2001-08-06
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// Purpose:     HAL diagnostic output
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// Description: Implementations of HAL diagnostic output support.
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal.h>
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#include CYGBLD_HAL_VARIANT_H           // Variant specific configuration
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#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
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56
#include <cyg/infra/cyg_type.h>         // base types
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#include <cyg/infra/cyg_trac.h>         // tracing macros
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#include <cyg/infra/cyg_ass.h>          // assertion macros
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60
#include <cyg/hal/hal_arch.h>           // basic machine info
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#include <cyg/hal/hal_intr.h>           // interrupt macros
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#include <cyg/hal/hal_io.h>             // IO macros
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/drv_api.h>
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#include <cyg/hal/hal_if.h>             // interface API
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#include <cyg/hal/hal_misc.h>           // Helper functions
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#include <cyg/hal/excalibur.h>          // platform definitions
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//-----------------------------------------------------------------------------
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#define CYG_DEVICE_SERIAL_BAUD_DIV (CYGNUM_HAL_ARM_EXCALIBUR_PERIPHERAL_CLOCK/CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD/16)
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#define CYG_DEVICE_SERIAL_BAUD_LSB (CYG_DEVICE_SERIAL_BAUD_DIV&0xff)
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#define CYG_DEVICE_SERIAL_BAUD_MSB ((CYG_DEVICE_SERIAL_BAUD_DIV>>8)&0xff)
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75
//-----------------------------------------------------------------------------
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typedef struct {
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    cyg_uint32 base;
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    cyg_int32 msec_timeout;
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    int isr_vector;
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} channel_data_t;
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82
//-----------------------------------------------------------------------------
83
 
84
static void
85
cyg_hal_plf_serial_init_channel(void* __ch_data)
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{
87
    cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
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89
    // 8-1-no parity.
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    HAL_WRITE_UINT32(base+_UART_MC, _UART_MC_8BIT | _UART_MC_1STOP | _UART_MC_PARITY_NONE);
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92
    HAL_WRITE_UINT32(base+_UART_DIV_LO, CYG_DEVICE_SERIAL_BAUD_LSB);
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    HAL_WRITE_UINT32(base+_UART_DIV_HI, CYG_DEVICE_SERIAL_BAUD_MSB);
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    HAL_WRITE_UINT32(base+_UART_FCR, (_UART_FCR_TC | _UART_FCR_RC |
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                                      _UART_FCR_TX_THR_15 | _UART_FCR_RX_THR_1));  // clear & enableFIFO
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    // enable RX interrupts - otherwise ISR cannot be polled. Actual
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    // interrupt control of serial happens via INT_MASK
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    HAL_WRITE_UINT32(base+_UART_IES, _UART_INTS_RE);
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}
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102
void
103
cyg_hal_plf_serial_putc(void *__ch_data, char c)
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{
105
    cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
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    cyg_uint32 tsr;
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    CYGARC_HAL_SAVE_GP();
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109
    do {
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        HAL_READ_UINT32(base+_UART_TSR, tsr);
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        // Wait for TXI flag to be set - or for the register to be
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        // zero (works around a HW bug it seems).
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    } while (tsr && (tsr & _UART_TSR_TXI) == 0);
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    HAL_WRITE_UINT32(base+_UART_TD, (cyg_uint32)(unsigned char)c);
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117
    CYGARC_HAL_RESTORE_GP();
118
}
119
 
120
static cyg_bool
121
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
122
{
123
    cyg_uint32 base = ((channel_data_t*)__ch_data)->base;
124
    cyg_uint32 rsr, isr, data;
125
 
126
    HAL_READ_UINT32(base+_UART_ISR, isr);
127
    if (0 == (isr & _UART_INTS_RI)) {
128
        HAL_READ_UINT32(base+_UART_RSR, rsr);
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        if (0 == rsr)
130
            return false;
131
    }
132
 
133
    HAL_READ_UINT32(base+_UART_RD, data);
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    *ch = (cyg_uint8)(data & 0xff);
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136
    // Read RSR to clear interrupt, and RDS to clear errors
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    HAL_READ_UINT32(base+_UART_RSR, data);
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    HAL_READ_UINT32(base+_UART_RDS, data);
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140
    return true;
141
}
142
 
143
cyg_uint8
144
cyg_hal_plf_serial_getc(void* __ch_data)
145
{
146
    cyg_uint8 ch;
147
    CYGARC_HAL_SAVE_GP();
148
 
149
    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
150
 
151
    CYGARC_HAL_RESTORE_GP();
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    return ch;
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}
154
 
155
static channel_data_t excalibur_ser_channels[1] = {
156
    { (cyg_uint32)EXCALIBUR_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART }
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};
158
 
159
static void
160
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
161
                         cyg_uint32 __len)
162
{
163
    CYGARC_HAL_SAVE_GP();
164
 
165
    while(__len-- > 0)
166
        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
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168
    CYGARC_HAL_RESTORE_GP();
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}
170
 
171
static void
172
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
173
{
174
    CYGARC_HAL_SAVE_GP();
175
 
176
    while(__len-- > 0)
177
        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
178
 
179
    CYGARC_HAL_RESTORE_GP();
180
}
181
 
182
cyg_bool
183
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
184
{
185
    int delay_count;
186
    channel_data_t* chan = (channel_data_t*)__ch_data;
187
    cyg_bool res;
188
    CYGARC_HAL_SAVE_GP();
189
 
190
    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
191
 
192
    for(;;) {
193
        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
194
        if (res || 0 == delay_count--)
195
            break;
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197
        CYGACC_CALL_IF_DELAY_US(100);
198
    }
199
 
200
    CYGARC_HAL_RESTORE_GP();
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    return res;
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}
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204
static int
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cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
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{
207
    static int irq_state = 0;
208
    channel_data_t* chan = (channel_data_t*)__ch_data;
209
    int ret = 0;
210
    CYGARC_HAL_SAVE_GP();
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212
    switch (__func) {
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    case __COMMCTL_IRQ_ENABLE:
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        irq_state = 1;
215
 
216
        // Need to keep it enabled to allow polling using ISR
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        //HAL_WRITE_UINT32(chan->base+_UART_IES, _UART_INTS_RE);
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219
        HAL_INTERRUPT_UNMASK(chan->isr_vector);
220
        break;
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    case __COMMCTL_IRQ_DISABLE:
222
        ret = irq_state;
223
        irq_state = 0;
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225
        // Need to keep it enabled to allow polling using ISR
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        // HAL_WRITE_UINT32(chan->base+_UART_IEC, _UART_INTS_RE);
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        HAL_INTERRUPT_MASK(chan->isr_vector);
229
        break;
230
    case __COMMCTL_DBG_ISR_VECTOR:
231
        ret = chan->isr_vector;
232
        break;
233
    case __COMMCTL_SET_TIMEOUT:
234
    {
235
        va_list ap;
236
 
237
        va_start(ap, __func);
238
 
239
        ret = chan->msec_timeout;
240
        chan->msec_timeout = va_arg(ap, cyg_uint32);
241
 
242
        va_end(ap);
243
    }
244
    default:
245
        break;
246
    }
247
    CYGARC_HAL_RESTORE_GP();
248
    return ret;
249
}
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251
static int
252
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
253
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
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{
255
    int res = 0;
256
    channel_data_t* chan = (channel_data_t*)__ch_data;
257
    cyg_uint32 isr, ch, rsr;
258
    char c;
259
    CYGARC_HAL_SAVE_GP();
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261
    cyg_drv_interrupt_acknowledge(chan->isr_vector);
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263
    *__ctrlc = 0;
264
    HAL_READ_UINT32(chan->base+_UART_ISR, isr);
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    HAL_READ_UINT32(chan->base+_UART_RSR, rsr);
266
 
267
    // Again, check both RI and the RX FIFO count.
268
    if ( ((isr & _UART_INTS_RI) != 0 ) || (rsr) ) {
269
 
270
        HAL_READ_UINT32(chan->base+_UART_RD, ch);
271
 
272
        c = (char)ch;
273
        if( cyg_hal_is_break( &c , 1 ) )
274
            *__ctrlc = 1;
275
 
276
        res = CYG_ISR_HANDLED;
277
    }
278
 
279
    CYGARC_HAL_RESTORE_GP();
280
    return res;
281
}
282
 
283
static void
284
cyg_hal_plf_serial_init(void)
285
{
286
    hal_virtual_comm_table_t* comm;
287
    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
288
 
289
    // Disable interrupts.
290
    HAL_INTERRUPT_MASK(excalibur_ser_channels[0].isr_vector);
291
 
292
    // Init channels
293
    cyg_hal_plf_serial_init_channel(&excalibur_ser_channels[0]);
294
 
295
    // Setup procs in the vector table
296
 
297
    // Set channel 0
298
    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
299
    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
300
    CYGACC_COMM_IF_CH_DATA_SET(*comm, &excalibur_ser_channels[0]);
301
    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
302
    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
303
    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
304
    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
305
    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
306
    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
307
    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
308
 
309
    // Restore original console
310
    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
311
}
312
 
313
void
314
cyg_hal_plf_comms_init(void)
315
{
316
    static int initialized = 0;
317
 
318
    if (initialized)
319
        return;
320
 
321
    initialized = 1;
322
 
323
    cyg_hal_plf_serial_init();
324
}
325
 
326
//-----------------------------------------------------------------------------
327
// LEDs
328
void
329
hal_diag_led(int n)
330
{
331
}
332
 
333
//-----------------------------------------------------------------------------
334
// End of hal_diag.c

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