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#ifndef CYGONCE_HAL_VAR_IO_H
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#define CYGONCE_HAL_VAR_IO_H
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//=============================================================================
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//
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// var_io.h
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//
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// Variant specific registers
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2009 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors:jskov, gthomas, tkoeller, tdrury, nickg, asl, John Eigelaar
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// Date: 2001-07-12
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// Purpose: AT91 variant specific registers
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// Description:
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// Usage: #include <cyg/hal/var_io.h>
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/hal/plf_io.h>
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//=============================================================================
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// USART
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#ifndef AT91_USART0
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#define AT91_USART0 0xFFFD0000
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#endif
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#ifndef AT91_USART1
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#define AT91_USART1 0xFFFCC000
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#endif
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#define AT91_US_CR 0x00 // Control register
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#define AT91_US_CR_RxRESET (1<<2)
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#define AT91_US_CR_TxRESET (1<<3)
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#define AT91_US_CR_RxENAB (1<<4)
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#define AT91_US_CR_RxDISAB (1<<5)
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#define AT91_US_CR_TxENAB (1<<6)
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#define AT91_US_CR_TxDISAB (1<<7)
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#define AT91_US_CR_RSTATUS (1<<8)
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#define AT91_US_CR_STTTO (1<<11)
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#define AT91_US_MR 0x04 // Mode register
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#define AT91_US_MR_CLOCK 4
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#define AT91_US_MR_CLOCK_MCK (0<<AT91_US_MR_CLOCK)
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#define AT91_US_MR_CLOCK_MCK8 (1<<AT91_US_MR_CLOCK)
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#define AT91_US_MR_CLOCK_SCK (2<<AT91_US_MR_CLOCK)
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#define AT91_US_MR_LENGTH 6
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#define AT91_US_MR_LENGTH_5 (0<<AT91_US_MR_LENGTH)
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#define AT91_US_MR_LENGTH_6 (1<<AT91_US_MR_LENGTH)
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#define AT91_US_MR_LENGTH_7 (2<<AT91_US_MR_LENGTH)
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#define AT91_US_MR_LENGTH_8 (3<<AT91_US_MR_LENGTH)
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#define AT91_US_MR_SYNC 8
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#define AT91_US_MR_SYNC_ASYNC (0<<AT91_US_MR_SYNC)
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#define AT91_US_MR_SYNC_SYNC (1<<AT91_US_MR_SYNC)
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#define AT91_US_MR_PARITY 9
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#define AT91_US_MR_PARITY_EVEN (0<<AT91_US_MR_PARITY)
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#define AT91_US_MR_PARITY_ODD (1<<AT91_US_MR_PARITY)
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#define AT91_US_MR_PARITY_SPACE (2<<AT91_US_MR_PARITY)
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#define AT91_US_MR_PARITY_MARK (3<<AT91_US_MR_PARITY)
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#define AT91_US_MR_PARITY_NONE (4<<AT91_US_MR_PARITY)
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#define AT91_US_MR_PARITY_MULTI (6<<AT91_US_MR_PARITY)
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#define AT91_US_MR_STOP 12
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#define AT91_US_MR_STOP_1 (0<<AT91_US_MR_STOP)
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#define AT91_US_MR_STOP_1_5 (1<<AT91_US_MR_STOP)
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#define AT91_US_MR_STOP_2 (2<<AT91_US_MR_STOP)
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#define AT91_US_MR_MODE 14
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#define AT91_US_MR_MODE_NORMAL (0<<AT91_US_MR_MODE)
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#define AT91_US_MR_MODE_ECHO (1<<AT91_US_MR_MODE)
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#define AT91_US_MR_MODE_LOCAL (2<<AT91_US_MR_MODE)
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#define AT91_US_MR_MODE_REMOTE (3<<AT91_US_MR_MODE)
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#define AT91_US_MR_MODE9 17
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#define AT91_US_MR_CLKO 18
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#define AT91_US_IER 0x08 // Interrupt enable register
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#define AT91_US_IER_RxRDY (1<<0) // Receive data ready
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#define AT91_US_IER_TxRDY (1<<1) // Transmitter ready
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#define AT91_US_IER_RxBRK (1<<2) // Break received
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#define AT91_US_IER_ENDRX (1<<3) // Rx end
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#define AT91_US_IER_ENDTX (1<<4) // Tx end
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#define AT91_US_IER_OVRE (1<<5) // Rx overflow
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#define AT91_US_IER_FRAME (1<<6) // Rx framing error
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#define AT91_US_IER_PARITY (1<<7) // Rx parity
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#define AT91_US_IER_TIMEOUT (1<<8) // Rx timeout
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#define AT91_US_IER_TxEMPTY (1<<9) // Tx empty
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#define AT91_US_IDR 0x0C // Interrupt disable register
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#define AT91_US_IMR 0x10 // Interrupt mask register
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#define AT91_US_CSR 0x14 // Channel status register
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#define AT91_US_CSR_RxRDY 0x01 // Receive data ready
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#define AT91_US_CSR_TxRDY 0x02 // Transmit ready
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#define AT91_US_CSR_RXBRK 0x04 // Transmit ready
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#define AT91_US_CSR_ENDRX 0x08 // Transmit ready
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#define AT91_US_CSR_ENDTX 0x10 // Transmit ready
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#define AT91_US_CSR_OVRE 0x20 // Overrun error
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#define AT91_US_CSR_FRAME 0x40 // Framing error
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#define AT91_US_CSR_TIMEOUT 0x80 // Timeout
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#define AT91_US_RHR 0x18 // Receive holding register
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#define AT91_US_THR 0x1C // Transmit holding register
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#define AT91_US_BRG 0x20 // Baud rate generator
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#define AT91_US_RTO 0x24 // Receive time out
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#define AT91_US_TTG 0x28 // Transmit timer guard
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// PDC US registers may have different addresses in at91 targets (i.e jtst)
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#ifndef AT91_US_RPR
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#define AT91_US_RPR 0x30 // Receive pointer register
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#endif
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#ifndef AT91_US_RCR
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#define AT91_US_RCR 0x34 // Receive counter register
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#endif
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#ifndef AT91_US_TPR
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#define AT91_US_TPR 0x38 // Transmit pointer register
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#endif
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#ifndef AT91_US_TCR
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#define AT91_US_TCR 0x3c // Transmit counter register
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#endif
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// PDC Control register bits
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#define AT91_US_PTCR_RXTEN (1 << 0)
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#define AT91_US_PTCR_RXTDIS (1 << 1)
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#define AT91_US_PTCR_TXTEN (1 << 8)
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#define AT91_US_PTCR_TXTDIS (1 << 9)
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// macro could be different from target to target (i.e jtst)
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#ifndef AT91_US_BAUD
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#define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2)
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#endif
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//=============================================================================
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// PIO
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#ifndef AT91_PIO
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#define AT91_PIO 0xFFFF0000
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#endif
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#define AT91_PIN(_ctrl_, _periph_, _pin_) \
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((_ctrl_ << 16) | (_periph_ << 8) | (_pin_))
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#define AT91_PIO_PER 0x00 // PIO enable
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#define AT91_PIO_PDR 0x04 // PIO disable
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#define AT91_PIO_PSR 0x08 // PIO status
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// GPIO pins on PIO A.
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#define AT91_GPIO_PA0 AT91_PIN(0,0, 0)
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#define AT91_GPIO_PA1 AT91_PIN(0,0, 1)
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#define AT91_GPIO_PA2 AT91_PIN(0,0, 2)
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#define AT91_GPIO_PA3 AT91_PIN(0,0, 3)
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#define AT91_GPIO_PA4 AT91_PIN(0,0, 4)
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#define AT91_GPIO_PA5 AT91_PIN(0,0, 5)
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#define AT91_GPIO_PA6 AT91_PIN(0,0, 6)
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#define AT91_GPIO_PA7 AT91_PIN(0,0, 7)
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#define AT91_GPIO_PA8 AT91_PIN(0,0, 8)
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#define AT91_GPIO_PA9 AT91_PIN(0,0, 9)
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#define AT91_GPIO_PA10 AT91_PIN(0,0,10)
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#define AT91_GPIO_PA11 AT91_PIN(0,0,11)
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#define AT91_GPIO_PA12 AT91_PIN(0,0,12)
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#define AT91_GPIO_PA13 AT91_PIN(0,0,13)
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#define AT91_GPIO_PA14 AT91_PIN(0,0,14)
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#define AT91_GPIO_PA15 AT91_PIN(0,0,15)
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#define AT91_GPIO_PA16 AT91_PIN(0,0,16)
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#define AT91_GPIO_PA17 AT91_PIN(0,0,17)
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#define AT91_GPIO_PA18 AT91_PIN(0,0,18)
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#define AT91_GPIO_PA19 AT91_PIN(0,0,19)
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#define AT91_GPIO_PA20 AT91_PIN(0,0,20)
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#define AT91_GPIO_PA21 AT91_PIN(0,0,21)
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#define AT91_GPIO_PA22 AT91_PIN(0,0,22)
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#define AT91_GPIO_PA23 AT91_PIN(0,0,23)
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#define AT91_GPIO_PA24 AT91_PIN(0,0,24)
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#define AT91_GPIO_PA25 AT91_PIN(0,0,25)
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#define AT91_GPIO_PA26 AT91_PIN(0,0,26)
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#define AT91_GPIO_PA27 AT91_PIN(0,0,27)
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#define AT91_GPIO_PA28 AT91_PIN(0,0,28)
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#define AT91_GPIO_PA29 AT91_PIN(0,0,29)
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#define AT91_GPIO_PA30 AT91_PIN(0,0,30)
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#define AT91_GPIO_PA31 AT91_PIN(0,0,31)
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#ifdef AT91_PIOB
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// GPIO pins on PIOB.
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#define AT91_GPIO_PB0 AT91_PIN(1,0, 0)
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#define AT91_GPIO_PB1 AT91_PIN(1,0, 1)
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#define AT91_GPIO_PB2 AT91_PIN(1,0, 2)
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#define AT91_GPIO_PB3 AT91_PIN(1,0, 3)
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#define AT91_GPIO_PB4 AT91_PIN(1,0, 4)
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#define AT91_GPIO_PB5 AT91_PIN(1,0, 5)
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#define AT91_GPIO_PB6 AT91_PIN(1,0, 6)
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#define AT91_GPIO_PB7 AT91_PIN(1,0, 7)
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#define AT91_GPIO_PB8 AT91_PIN(1,0, 8)
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#define AT91_GPIO_PB9 AT91_PIN(1,0, 9)
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#define AT91_GPIO_PB10 AT91_PIN(1,0,10)
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#define AT91_GPIO_PB11 AT91_PIN(1,0,11)
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#define AT91_GPIO_PB12 AT91_PIN(1,0,12)
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#define AT91_GPIO_PB13 AT91_PIN(1,0,13)
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#define AT91_GPIO_PB14 AT91_PIN(1,0,14)
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#define AT91_GPIO_PB15 AT91_PIN(1,0,15)
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#define AT91_GPIO_PB16 AT91_PIN(1,0,16)
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#define AT91_GPIO_PB17 AT91_PIN(1,0,17)
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#define AT91_GPIO_PB18 AT91_PIN(1,0,18)
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#define AT91_GPIO_PB19 AT91_PIN(1,0,19)
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#define AT91_GPIO_PB20 AT91_PIN(1,0,20)
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#define AT91_GPIO_PB21 AT91_PIN(1,0,21)
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#define AT91_GPIO_PB22 AT91_PIN(1,0,22)
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#define AT91_GPIO_PB23 AT91_PIN(1,0,23)
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#define AT91_GPIO_PB24 AT91_PIN(1,0,24)
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#define AT91_GPIO_PB25 AT91_PIN(1,0,25)
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#define AT91_GPIO_PB26 AT91_PIN(1,0,26)
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#define AT91_GPIO_PB27 AT91_PIN(1,0,27)
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#define AT91_GPIO_PB28 AT91_PIN(1,0,28)
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#define AT91_GPIO_PB29 AT91_PIN(1,0,29)
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#define AT91_GPIO_PB30 AT91_PIN(1,0,30)
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#define AT91_GPIO_PB31 AT91_PIN(1,0,31)
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#endif //AT91_PIOB
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#ifdef AT91_PIOC
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// GPIO pins on PIOC.
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#define AT91_GPIO_PC0 AT91_PIN(2,0, 0)
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#define AT91_GPIO_PC1 AT91_PIN(2,0, 1)
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#define AT91_GPIO_PC2 AT91_PIN(2,0, 2)
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#define AT91_GPIO_PC3 AT91_PIN(2,0, 3)
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#define AT91_GPIO_PC4 AT91_PIN(2,0, 4)
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#define AT91_GPIO_PC5 AT91_PIN(2,0, 5)
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#define AT91_GPIO_PC6 AT91_PIN(2,0, 6)
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#define AT91_GPIO_PC7 AT91_PIN(2,0, 7)
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#define AT91_GPIO_PC8 AT91_PIN(2,0, 8)
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#define AT91_GPIO_PC9 AT91_PIN(2,0, 9)
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#define AT91_GPIO_PC10 AT91_PIN(2,0,10)
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#define AT91_GPIO_PC11 AT91_PIN(2,0,11)
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#define AT91_GPIO_PC12 AT91_PIN(2,0,12)
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#define AT91_GPIO_PC13 AT91_PIN(2,0,13)
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#define AT91_GPIO_PC14 AT91_PIN(2,0,14)
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#define AT91_GPIO_PC15 AT91_PIN(2,0,15)
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#define AT91_GPIO_PC16 AT91_PIN(2,0,16)
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#define AT91_GPIO_PC17 AT91_PIN(2,0,17)
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#define AT91_GPIO_PC18 AT91_PIN(2,0,18)
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#define AT91_GPIO_PC19 AT91_PIN(2,0,19)
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#define AT91_GPIO_PC20 AT91_PIN(2,0,20)
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#define AT91_GPIO_PC21 AT91_PIN(2,0,21)
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#define AT91_GPIO_PC22 AT91_PIN(2,0,22)
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#define AT91_GPIO_PC23 AT91_PIN(2,0,23)
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#define AT91_GPIO_PC24 AT91_PIN(2,0,24)
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#define AT91_GPIO_PC25 AT91_PIN(2,0,25)
|
275 |
|
|
#define AT91_GPIO_PC26 AT91_PIN(2,0,26)
|
276 |
|
|
#define AT91_GPIO_PC27 AT91_PIN(2,0,27)
|
277 |
|
|
#define AT91_GPIO_PC28 AT91_PIN(2,0,28)
|
278 |
|
|
#define AT91_GPIO_PC29 AT91_PIN(2,0,29)
|
279 |
|
|
#define AT91_GPIO_PC30 AT91_PIN(2,0,30)
|
280 |
|
|
#define AT91_GPIO_PC31 AT91_PIN(2,0,31)
|
281 |
|
|
#endif //AT91_PIOC
|
282 |
|
|
|
283 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91_M55800A)
|
284 |
|
|
|
285 |
|
|
#define AT91_TC_TCLK3 AT91_PIN(0,0, 0) // Timer 3 Clock signal
|
286 |
|
|
#define AT91_TC_TIOA3 AT91_PIN(0,0, 1) // Timer 3 Signal A
|
287 |
|
|
#define AT91_TC_TIOB3 AT91_PIN(0,0, 2) // Timer 3 Signal B
|
288 |
|
|
#define AT91_TC_TCLK4 AT91_PIN(0,0, 3) // Timer 4 Clock signal
|
289 |
|
|
#define AT91_TC_TIOA4 AT91_PIN(0,0, 4) // Timer 4 Signal A
|
290 |
|
|
#define AT91_TC_TIOB4 AT91_PIN(0,0, 5) // Timer 4 Signal B
|
291 |
|
|
#define AT91_TC_TCLK5 AT91_PIN(0,0, 6) // Timer 5 Clock signal
|
292 |
|
|
#define AT91_TC_TIOA5 AT91_PIN(0,0, 7) // Timer 5 Signal A
|
293 |
|
|
#define AT91_TC_TIOB5 AT91_PIN(0,0, 8) // Timer 5 Signal B
|
294 |
|
|
#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // External Interrupt 0
|
295 |
|
|
#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // External Interrupt 1
|
296 |
|
|
#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // External Interrupt 2
|
297 |
|
|
#define AT91_INT_IRQ3 AT91_PIN(0,0,12) // External Interrupt 3
|
298 |
|
|
#define AT91_INT_FIQ AT91_PIN(0,0,13) // Fast Interrupt
|
299 |
|
|
#define AT91_USART_SCK0 AT91_PIN(0,0,14) // USART 0 Clock signal
|
300 |
|
|
#define AT91_USART_TXD0 AT91_PIN(0,0,15) // USART 0 transmit data
|
301 |
|
|
#define AT91_USART_RXD0 AT91_PIN(0,0,16) // USART 0 receive data
|
302 |
|
|
#define AT91_USART_SCK1 AT91_PIN(0,0,17) // USART 1 Clock signal
|
303 |
|
|
#define AT91_USART_TXD1 AT91_PIN(0,0,18) // USART 1 transmit data
|
304 |
|
|
#define AT91_USART_RXD1 AT91_PIN(0,0,19) // USART 1 receive data
|
305 |
|
|
#define AT91_USART_SCK2 AT91_PIN(0,0,20) // USART 2 Clock signal
|
306 |
|
|
#define AT91_USART_TXD2 AT91_PIN(0,0,21) // USART 2 transmit data
|
307 |
|
|
#define AT91_USART_RXD2 AT91_PIN(0,0,22) // USART 2 receive data
|
308 |
|
|
#define AT91_SPI_SPCK AT91_PIN(0,0,23) // SPI Clock signal
|
309 |
|
|
#define AT91_SPI_MISO AT91_PIN(0,0,24) // SPI Master In Slave Out
|
310 |
|
|
#define AT91_SPI_MOSI AT91_PIN(0,0,25) // SPI Master Out Slave In
|
311 |
|
|
#define AT91_SPI_NPCS0 AT91_PIN(0,0,26) // SPI Peripheral Chip Select 0
|
312 |
|
|
#define AT91_SPI_NPCS1 AT91_PIN(0,0,27) // SPI Peripheral Chip Select 1
|
313 |
|
|
#define AT91_SPI_NPCS2 AT91_PIN(0,0,28) // SPI Peripheral Chip Select 2
|
314 |
|
|
#define AT91_SPI_NPCS3 AT91_PIN(0,0,29) // SPI Peripheral Chip Select 3
|
315 |
|
|
|
316 |
|
|
#define AT91_INT_IRQ4 AT91_PIN(1,0, 3) // External Interrupt 4
|
317 |
|
|
#define AT91_INT_IRQ5 AT91_PIN(1,0, 4) // External Interrupt 5
|
318 |
|
|
#define AT91_ADC_AD0TRIG AT91_PIN(1,0, 6) // ADC0 External Trigger
|
319 |
|
|
#define AT91_ADC_AD1TRIG AT91_PIN(1,0, 7) // ADC1 External Trigger
|
320 |
|
|
#define AT91_BOOT_BMS AT91_PIN(1,0,12) // Boot Mode Select
|
321 |
|
|
#define AT91_TC_TCLK0 AT91_PIN(1,0,14) // Timer 0 Clock signal
|
322 |
|
|
#define AT91_TC_TIOA0 AT91_PIN(1,0,15) // Timer 0 Signal A
|
323 |
|
|
#define AT91_TC_TIOB0 AT91_PIN(1,0,16) // Timer 0 Signal B
|
324 |
|
|
#define AT91_TC_TCLK1 AT91_PIN(1,0,17) // Timer 1 Clock signal
|
325 |
|
|
#define AT91_TC_TIOA1 AT91_PIN(1,0,18) // Timer 1 Signal A
|
326 |
|
|
#define AT91_TC_TIOB1 AT91_PIN(1,0,19) // Timer 1 Signal B
|
327 |
|
|
#define AT91_TC_TCLK2 AT91_PIN(1,0,20) // Timer 2 Clock signal
|
328 |
|
|
#define AT91_TC_TIOA2 AT91_PIN(1,0,21) // Timer 2 Signal A
|
329 |
|
|
#define AT91_TC_TIOB2 AT91_PIN(1,0,22) // Timer 2 Signal B
|
330 |
|
|
|
331 |
|
|
// PIOA
|
332 |
|
|
#define AT91_PIO_PSR_TCLK3 0x00000001 // Timer 3 Clock signal
|
333 |
|
|
#define AT91_PIO_PSR_TIOA3 0x00000002 // Timer 3 Signal A
|
334 |
|
|
#define AT91_PIO_PSR_TIOB3 0x00000004 // Timer 3 Signal B
|
335 |
|
|
#define AT91_PIO_PSR_TCLK4 0x00000008 // Timer 4 Clock signal
|
336 |
|
|
#define AT91_PIO_PSR_TIOA4 0x00000010 // Timer 4 Signal A
|
337 |
|
|
#define AT91_PIO_PSR_TIOB4 0x00000020 // Timer 4 Signal B
|
338 |
|
|
#define AT91_PIO_PSR_TCLK5 0x00000040 // Timer 5 Clock signal
|
339 |
|
|
#define AT91_PIO_PSR_TIOA5 0x00000080 // Timer 5 Signal A
|
340 |
|
|
#define AT91_PIO_PSR_TIOB5 0x00000100 // Timer 5 Signal B
|
341 |
|
|
#define AT91_PIO_PSR_IRQ0 0x00000200 // External Interrupt 0
|
342 |
|
|
#define AT91_PIO_PSR_IRQ1 0x00000400 // External Interrupt 1
|
343 |
|
|
#define AT91_PIO_PSR_IRQ2 0x00000800 // External Interrupt 2
|
344 |
|
|
#define AT91_PIO_PSR_IRQ3 0x00001000 // External Interrupt 3
|
345 |
|
|
#define AT91_PIO_PSR_FIQ 0x00002000 // Fast Interrupt
|
346 |
|
|
#define AT91_PIO_PSR_SCK0 0x00004000 // USART 0 Clock signal
|
347 |
|
|
#define AT91_PIO_PSR_TXD0 0x00008000 // USART 0 transmit data
|
348 |
|
|
#define AT91_PIO_PSR_RXD0 0x00010000 // USART 0 receive data
|
349 |
|
|
#define AT91_PIO_PSR_SCK1 0x00020000 // USART 1 Clock signal
|
350 |
|
|
#define AT91_PIO_PSR_TXD1 0x00040000 // USART 1 transmit data
|
351 |
|
|
#define AT91_PIO_PSR_RXD1 0x00080000 // USART 1 receive data
|
352 |
|
|
#define AT91_PIO_PSR_SCK2 0x00100000 // USART 2 Clock signal
|
353 |
|
|
#define AT91_PIO_PSR_TXD2 0x00200000 // USART 2 transmit data
|
354 |
|
|
#define AT91_PIO_PSR_RXD2 0x00400000 // USART 2 receive data
|
355 |
|
|
#define AT91_PIO_PSR_SPCK 0x00800000 // SPI Clock signal
|
356 |
|
|
#define AT91_PIO_PSR_MISO 0x01000000 // SPI Master In Slave Out
|
357 |
|
|
#define AT91_PIO_PSR_MOSI 0x02000000 // SPI Master Out Slave In
|
358 |
|
|
#define AT91_PIO_PSR_NPCS0 0x04000000 // SPI Peripheral Chip Select 0
|
359 |
|
|
#define AT91_PIO_PSR_NPCS1 0x08000000 // SPI Peripheral Chip Select 1
|
360 |
|
|
#define AT91_PIO_PSR_NPCS2 0x10000000 // SPI Peripheral Chip Select 2
|
361 |
|
|
#define AT91_PIO_PSR_NPCS3 0x20000000 // SPI Peripheral Chip Select 3
|
362 |
|
|
|
363 |
|
|
// PIOB
|
364 |
|
|
#define AT91_PIO_PSR_IRQ4 0x00000008 // External Interrupt 4
|
365 |
|
|
#define AT91_PIO_PSR_IRQ5 0x00000010 // External Interrupt 5
|
366 |
|
|
#define AT91_PIO_PSR_AD0TRIG 0x00000040 // ADC0 External Trigger
|
367 |
|
|
#define AT91_PIO_PSR_AD1TRIG 0x00000080 // ADC1 External Trigger
|
368 |
|
|
#define AT91_PIO_PSR_BMS 0x00040000 // Boot Mode Select
|
369 |
|
|
#define AT91_PIO_PSR_TCLK0 0x00080000 // Timer 0 Clock signal
|
370 |
|
|
#define AT91_PIO_PSR_TIOA0 0x00100000 // Timer 0 Signal A
|
371 |
|
|
#define AT91_PIO_PSR_TIOB0 0x00200000 // Timer 0 Signal B
|
372 |
|
|
#define AT91_PIO_PSR_TCLK1 0x00400000 // Timer 1 Clock signal
|
373 |
|
|
#define AT91_PIO_PSR_TIOA1 0x00800000 // Timer 1 Signal A
|
374 |
|
|
#define AT91_PIO_PSR_TIOB1 0x01000000 // Timer 1 Signal B
|
375 |
|
|
#define AT91_PIO_PSR_TCLK2 0x02000000 // Timer 2 Clock signal
|
376 |
|
|
#define AT91_PIO_PSR_TIOA2 0x04000000 // Timer 2 Signal A
|
377 |
|
|
#define AT91_PIO_PSR_TIOB2 0x08000000 // Timer 2 Signal B
|
378 |
|
|
|
379 |
|
|
#elif defined (CYGHWR_HAL_ARM_AT91SAM7)
|
380 |
|
|
#include <pkgconf/hal_arm_at91sam7.h>
|
381 |
|
|
|
382 |
|
|
#ifdef CYGHWR_HAL_ARM_AT91SAM7S
|
383 |
|
|
#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
|
384 |
|
|
#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
|
385 |
|
|
#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
|
386 |
|
|
#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
|
387 |
|
|
#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
|
388 |
|
|
#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
|
389 |
|
|
#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
|
390 |
|
|
#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
|
391 |
|
|
#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
|
392 |
|
|
#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
|
393 |
|
|
#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
|
394 |
|
|
#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
|
395 |
|
|
#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
|
396 |
|
|
#define AT91_SPI_MOSI AT91_PIN(0,0,13) // SPI Output
|
397 |
|
|
#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
|
398 |
|
|
#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
|
399 |
|
|
#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
|
400 |
|
|
#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
|
401 |
|
|
#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
|
402 |
|
|
#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
|
403 |
|
|
#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
|
404 |
|
|
#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
|
405 |
|
|
#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
|
406 |
|
|
#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
|
407 |
|
|
#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
|
408 |
|
|
#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
|
409 |
|
|
#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
|
410 |
|
|
#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
|
411 |
|
|
#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
|
412 |
|
|
#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
|
413 |
|
|
#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
|
414 |
|
|
#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
|
415 |
|
|
#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
|
416 |
|
|
#endif
|
417 |
|
|
|
418 |
|
|
#define AT91_TC_TIOA0 AT91_PIN(0,1, 0) // Timer/Counter 0 IO Line A
|
419 |
|
|
#define AT91_TC_TIOB0 AT91_PIN(0,1, 1) // Timer/Counter 0 IO Line B
|
420 |
|
|
#define AT91_USART_SCK0 AT91_PIN(0,1, 2) // USART 0 Serial Clock
|
421 |
|
|
#define AT91_SPI_NPCS3 AT91_PIN(0,1, 3) // SPI Chip Select 3
|
422 |
|
|
#define AT91_TC_TCLK0 AT91_PIN(0,1, 4) // Timer/Counter 0 Clock Input
|
423 |
|
|
#define AT91_SPI_NPCS3X AT91_PIN(0,1, 5) // SPI Chip Select 3 (again)
|
424 |
|
|
#define AT91_PCK_PCK0 AT91_PIN(0,1, 6) // Programmable Clock Output 0
|
425 |
|
|
#define AT91_PWM_PWM3 AT91_PIN(0,1, 7) // Pulse Width Modulation #3
|
426 |
|
|
#define AT91_ADC_ADTRG AT91_PIN(0,1, 8) // ADC Trigger
|
427 |
|
|
#define AT91_SPI_NPCS1X AT91_PIN(0,1, 9) // SPI Chip Select 1
|
428 |
|
|
#define AT91_SPI_NPCS2 AT91_PIN(0,1,10) // SPI Chip Select 2
|
429 |
|
|
#define AT91_PWM_PWM0X AT91_PIN(0,1,11) // Pulse Width Modulation #0
|
430 |
|
|
#define AT91_PIO_PWM_PWM1X AT91_PIN(0,1,12) // Pulse Width Modulation #1
|
431 |
|
|
#define AT91_PIO_PWM_PWM2X AT91_PIN(0,1,13) // Pulse Width Modulation #2
|
432 |
|
|
#define AT91_PIO_PWM_PWM4X AT91_PIN(0,1,14) // Pulse Width Modulation #4
|
433 |
|
|
#define AT91_TC_TIOA1 AT91_PIN(0,1,15) // Timer/Counter 1 IO Line A
|
434 |
|
|
#define AT91_TC_TIOB1 AT91_PIN(0,1,16) // Timer/Counter 1 IO Line B
|
435 |
|
|
#define AT91_PCK_PCK1 AT91_PIN(0,1,17) // Programmable Clock Output 1
|
436 |
|
|
#define AT91_PCK_PCK2 AT91_PIN(0,1,18) // Programmable Clock Output 2
|
437 |
|
|
#define AT91_INT_FIQ AT91_PIN(0,1,19) // Fast Interrupt Request
|
438 |
|
|
#define AT91_INT_IRQ0 AT91_PIN(0,1,20) // Interrupt Request 0
|
439 |
|
|
#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
|
440 |
|
|
#define AT91_PCK_PCK1X AT91_PIN(0,1,21) // Programmable Clock Output 1
|
441 |
|
|
#define AT91_SPI_NPCS3XX AT91_PIN(0,1,22) // SPI Chip Select 3 (yet again)
|
442 |
|
|
#define AT91_PWM_PWM0XX AT91_PIN(0,1,23) // Pulse Width Modulation #0
|
443 |
|
|
#define AT91_PWM_PWM1XX AT91_PIN(0,1,24) // Pulse Width Modulation #1
|
444 |
|
|
#define AT91_PWM_PWM2XX AT91_PIN(0,1,25) // Pulse Width Modulation 2
|
445 |
|
|
#define AT91_TC_TIOA2 AT91_PIN(0,1,26) // Timer/Counter 2 IO Line A
|
446 |
|
|
#define AT91_TC_TIOB2 AT91_PIN(0,1,27) // Timer/Counter 2 IO Line B
|
447 |
|
|
#define AT91_TC_TCLK1 AT91_PIN(0,1,28) // External Clock Input 1
|
448 |
|
|
#define AT91_TC_TCLK2 AT91_PIN(0,1,29) // External Clock Input 2
|
449 |
|
|
#define AT91_SPI_NPCS2X AT91_PIN(0,1,30) // SPI Chip Select 2 (again)
|
450 |
|
|
#define AT91_PCK_PCK2X AT91_PIN(0,1,31) // Programmable Clock Output 2
|
451 |
|
|
#endif //!defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
|
452 |
|
|
|
453 |
|
|
// PIO Peripheral A
|
454 |
|
|
#define AT91_PIO_PSR_PWM0 0x00000001 // Pulse Width Modulation 0
|
455 |
|
|
#define AT91_PIO_PSR_PWM1 0x00000002 // Pulse Width Modulation 1
|
456 |
|
|
#define AT91_PIO_PSR_PWM2 0x00000004 // Pulse Width Modulation 2
|
457 |
|
|
#define AT91_PIO_PSR_TWD 0x00000008 // Two Wire Data
|
458 |
|
|
#define AT91_PIO_PSR_TWCK 0x00000010 // Two Wire Clock
|
459 |
|
|
#define AT91_PIO_PSR_RXD0 0x00000020 // USART 0 Receive Data
|
460 |
|
|
#define AT91_PIO_PSR_TXD0 0x00000040 // USART 0 Transmit Data
|
461 |
|
|
#define AT91_PIO_PSR_RTS0 0x00000080 // USART 0 Ready To Send
|
462 |
|
|
#define AT91_PIO_PSR_CTS0 0x00000100 // USART 0 Clear To Send
|
463 |
|
|
#define AT91_PIO_PSR_DRXD 0x00000200 // Debug UART Receive
|
464 |
|
|
#define AT91_PIO_PSR_DTXD 0x00000400 // Debug UART Transmit
|
465 |
|
|
#define AT91_PIO_PSR_NPCS0 0x00000800 // SPI Chip Select 0
|
466 |
|
|
#define AT91_PIO_PSR_MISO 0x00001000 // SPI Input
|
467 |
|
|
#define AT91_PIO_PSR_MOSI 0x00002000 // SPI Output
|
468 |
|
|
#define AT91_PIO_PSR_SPCK 0x00004000 // SPI clock
|
469 |
|
|
#define AT91_PIO_PSR_TF 0x00008000 // S2C Transmit Frame Sync
|
470 |
|
|
#define AT91_PIO_PSR_TK 0x00010000 // S2C Transmit Clock
|
471 |
|
|
#define AT91_PIO_PSR_TD 0x00020000 // S2C Transmit Data
|
472 |
|
|
#define AT91_PIO_PSR_RD 0x00040000 // S2C Receive Data
|
473 |
|
|
#define AT91_PIO_PSR_RK 0x00080000 // S2C Receive Clock
|
474 |
|
|
#define AT91_PIO_PSR_RF 0x00100000 // S2C Receive Frame Sync
|
475 |
|
|
#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
|
476 |
|
|
#define AT91_PIO_PSR_RXD1 0x00200000 // USART 1 Receive Data
|
477 |
|
|
#define AT91_PIO_PSR_TXD1 0x00400000 // USART 1 Transmit Data
|
478 |
|
|
#define AT91_PIO_PSR_SCK1 0x00800000 // USART 1 Serial Clock
|
479 |
|
|
#define AT91_PIO_PSR_RTS1 0x01000000 // USART 1 Ready To Send
|
480 |
|
|
#define AT91_PIO_PSR_CTS1 0x02000000 // USART 1 Clear To Send
|
481 |
|
|
#define AT91_PIO_PSR_DCD1 0x04000000 // USART 1 Data Carrier Detect
|
482 |
|
|
#define AT91_PIO_PSR_DTR1 0x08000000 // USART 1 Data Terminal Ready
|
483 |
|
|
#define AT91_PIO_PSR_DSR1 0x10000000 // USART 1 Data Set Ready
|
484 |
|
|
#define AT91_PIO_PSR_RI1 0x20000000 // USART 2 Ring Indicator
|
485 |
|
|
#define AT91_PIO_PSR_IRQ1 0x40000000 // Interrupt Request 1
|
486 |
|
|
#define AT91_PIO_PSR_NPCS1 0x80000000 // SPI Chip Select 1
|
487 |
|
|
#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
|
488 |
|
|
|
489 |
|
|
// PIO Peripheral B
|
490 |
|
|
#define AT91_PIO_PSR_TIOA0 0x00000001 // Timer/Counter 0 IO Line A
|
491 |
|
|
#define AT91_PIO_PSR_TIOB0 0x00000002 // Timer/Counter 0 IO Line B
|
492 |
|
|
#define AT91_PIO_PSR_SCK0 0x00000004 // USART 0 Serial Clock
|
493 |
|
|
#define AT91_PIO_PSR_NPCS3 0x00000008 // SPI Chip Select 3
|
494 |
|
|
#define AT91_PIO_PSR_TCLK0 0x00000010 // Timer/Counter 0 Clock Input
|
495 |
|
|
#define AT91_PIO_PSR_NPCS3X 0x00000020 // SPI Chip Select 3 (again)
|
496 |
|
|
#define AT91_PIO_PSR_PCK0 0x00000040 // Programmable Clock Output 0
|
497 |
|
|
#define AT91_PIO_PSR_PWM3 0x00000080 // Pulse Width Modulation #3
|
498 |
|
|
#define AT91_PIO_PSR_ADTRG 0x00000100 // ADC Trigger
|
499 |
|
|
#define AT91_PIO_PSR_NPCS1X 0x00000200 // SPI Chip Select 1 (again)
|
500 |
|
|
#define AT91_PIO_PSR_NPCS2 0x00000400 // SPI Chip Select 2
|
501 |
|
|
#define AT91_PIO_PSR_PWMOX 0x00000800 // Pulse Width Modulation #0 (again)
|
502 |
|
|
#define AT91_PIO_PSR_PWM1X 0x00001000 // Pulse Width Modulation #1 (again)
|
503 |
|
|
#define AT91_PIO_PSR_PWM2X 0x00002000 // Pulse Width Modulation #2 (again)
|
504 |
|
|
#define AT91_PIO_PSR_PWM3X 0x00004000 // Pulse Width Modulation #4 (again)
|
505 |
|
|
#define AT91_PIO_PSR_TIOA1 0x00008000 // Timer/Counter 1 IO Line A
|
506 |
|
|
#define AT91_PIO_PSR_TIOB1 0x00010000 // Timer/Counter 1 IO Line B
|
507 |
|
|
#define AT91_PIO_PSR_PCK1 0x00020000 // Programmable Clock Output 1
|
508 |
|
|
#define AT91_PIO_PSR_PCK2 0x00040000 // Programmable Clock Output 2
|
509 |
|
|
#define AT91_PIO_PSR_FIQ 0x00080000 // Fast Interrupt Request
|
510 |
|
|
#define AT91_PIO_PSR_IRQ0 0x00100000 // Interrupt Request 0
|
511 |
|
|
#if !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
|
512 |
|
|
#define AT91_PIO_PSR_PCK1X 0x00200000 // Programmable Clock Output 1(again)
|
513 |
|
|
#define AT91_PIO_PSR_NPCS3XX 0x00400000 // SPI Chip Select 3 (yet again)
|
514 |
|
|
#define AT91_PIO_PSR_PWMOXX 0x00800000 // Pulse Width Modulation #0 (again)
|
515 |
|
|
#define AT91_PIO_PSR_PWM1XX 0x01000000 // Pulse Width Modulation #1 (again)
|
516 |
|
|
#define AT91_PIO_PSR_PWM2XX 0x02000000 // Pulse Width Modulation #2 (again)
|
517 |
|
|
#define AT91_PIO_PSR_TIOA2 0x04000000 // Timer/Counter 2 IO Line A
|
518 |
|
|
#define AT91_PIO_PSR_TIOB2 0x08000000 // Timer/Counter 2 IO Line B
|
519 |
|
|
#define AT91_PIO_PSR_TCLK1 0x10000000 // External Clock Input 1
|
520 |
|
|
#define AT91_PIO_PSR_TCLK2 0x20000000 // External Clock Input 2
|
521 |
|
|
#define AT91_PIO_PSR_NPCS2X 0x40000000 // SPI Chip Select 2 (again)
|
522 |
|
|
#define AT91_PIO_PSR_PCK2X 0x80000000 // Programmable Clock Output 2(again)
|
523 |
|
|
#endif // !defined(CYGHWR_HAL_ARM_AT91SAM7S_at91sam7s32)
|
524 |
|
|
#endif // CYGHWR_HAL_ARM_AT91SAM7S
|
525 |
|
|
|
526 |
|
|
#ifdef CYGHWR_HAL_ARM_AT91SAM7X
|
527 |
|
|
|
528 |
|
|
// PIO Controller A, peripheral A
|
529 |
|
|
#define AT91_USART_RXD0 AT91_PIN(0,0, 0) // USART 0 Receive Data
|
530 |
|
|
#define AT91_USART_TXD0 AT91_PIN(0,0, 1) // USART 0 Transmit Data
|
531 |
|
|
#define AT91_USART_SCK0 AT91_PIN(0,0, 2) // USART 0 Serial Clock
|
532 |
|
|
#define AT91_USART_RTS0 AT91_PIN(0,0, 3) // USART 0 Request To Send
|
533 |
|
|
#define AT91_USART_CTS0 AT91_PIN(0,0, 4) // USART 0 Clear To Send
|
534 |
|
|
#define AT91_USART_RXD1 AT91_PIN(0,0, 5) // USART 1 Receive Data
|
535 |
|
|
#define AT91_USART_TXD1 AT91_PIN(0,0, 6) // USART 1 Transmit Data
|
536 |
|
|
#define AT91_USART_SCK1 AT91_PIN(0,0, 7) // USART 1 Serial Clock
|
537 |
|
|
#define AT91_USART_RTS1 AT91_PIN(0,0, 8) // USART 1 Request To Send
|
538 |
|
|
#define AT91_USART_CTS1 AT91_PIN(0,0, 9) // USART 1 Clear To Send
|
539 |
|
|
#define AT91_TWI_TWD AT91_PIN(0,0,10) // Two Wire Data
|
540 |
|
|
#define AT91_TWI_TWCK AT91_PIN(0,0,11) // Two Wire Clock
|
541 |
|
|
#define AT91_SPI_NPCS0 AT91_PIN(0,0,12) // SPI 0 Chip Select 0
|
542 |
|
|
#define AT91_SPI_NPCS1 AT91_PIN(0,0,13) // SPI 0 Chip Select 1
|
543 |
|
|
#define AT91_SPI_NPCS2 AT91_PIN(0,0,14) // SPI 0 Chip Select 2
|
544 |
|
|
#define AT91_SPI_NPCS3 AT91_PIN(0,0,15) // SPI 0 Chip Select 3
|
545 |
|
|
#define AT91_SPI_MISO AT91_PIN(0,0,16) // SPI 0 Master In Slave Out
|
546 |
|
|
#define AT91_SPI_MOSI AT91_PIN(0,0,17) // SPI 0 Master Out Slave In
|
547 |
|
|
#define AT91_SPI_SPCK AT91_PIN(0,0,18) // SPI 0 Clock
|
548 |
|
|
#define AT91_CAN_CANRX AT91_PIN(0,0,19) // CAN Receive
|
549 |
|
|
#define AT91_CAN_CANTX AT91_PIN(0,0,20) // CAN Transmit
|
550 |
|
|
#define AT91_SSC_TF AT91_PIN(0,0,21) // SSC Transmit Frame Sync
|
551 |
|
|
#define AT91_S2C_TK AT91_PIN(0,0,22) // SSC Transmit Clock
|
552 |
|
|
#define AT91_S2C_TD AT91_PIN(0,0,23) // SSC Transmit Data
|
553 |
|
|
#define AT91_S2C_RD AT91_PIN(0,0,24) // SSC Receive Data
|
554 |
|
|
#define AT91_S2C_RK AT91_PIN(0,0,25) // SSC Receive Clock
|
555 |
|
|
#define AT91_S2C_RF AT91_PIN(0,0,26) // SSC Receive Frame Sync
|
556 |
|
|
#define AT91_DBG_DRXD AT91_PIN(0,0,27) // DBGU Receive Data
|
557 |
|
|
#define AT91_DBG_DTXD AT91_PIN(0,0,28) // DBGU Transmit Data
|
558 |
|
|
#define AT91_INT_FIQ AT91_PIN(0,0,29) // Fast Interrupt Request
|
559 |
|
|
#define AT91_INT_IRQ0 AT91_PIN(0,0,30) // Interrupt Request 0
|
560 |
|
|
|
561 |
|
|
//PIO controller A, peripheral B
|
562 |
|
|
#define AT91_SPI1_NPCS1 AT91_PIN(0,1, 2) // SPI 1 Chip Select 1
|
563 |
|
|
#define AT91_SPI1_NPCS2 AT91_PIN(0,1, 3) // SPI 1 Chip Select 2
|
564 |
|
|
#define AT91_SPI1_NPCS3 AT91_PIN(0,1, 4) // SPI 1 Chip Select 3
|
565 |
|
|
#define AT91_SPI_NPCS1X AT91_PIN(0,1, 7) // SPI 0 Chip Select 1
|
566 |
|
|
#define AT91_SPI_NPCS2X AT91_PIN(0,1, 8) // SPI 0 Chip Select 2
|
567 |
|
|
#define AT91_SPI_NPCS3X AT91_PIN(0,1, 9) // SPI 0 Chip Select 3
|
568 |
|
|
#define AT91_PCK_PCK1 AT91_PIN(0,1,13) // Programmable Clock Output 1
|
569 |
|
|
#define AT91_INT_IRQ1 AT91_PIN(0,1,14) // Interrupt Request 1
|
570 |
|
|
#define AT91_TC_TCLK1 AT91_PIN(0,1,15) // Timer/Counter 1 Clock Input
|
571 |
|
|
#define AT91_SPI1_NPCS0 AT91_PIN(0,1,21) // SPI 1 Chip Select 0
|
572 |
|
|
#define AT91_SPI1_SPCK AT91_PIN(0,1,22) // SPI 1 Clock
|
573 |
|
|
#define AT91_SPI1_MOSI AT91_PIN(0,1,23) // SPI 1 Master Out Slave In
|
574 |
|
|
#define AT91_SPI1_MISO AT91_PIN(0,1,24) // SPI 0 Master In Slave Out
|
575 |
|
|
#define AT91_SPI1_NPCS1X AT91_PIN(0,1,25) // SPI 1 Chip Select 1
|
576 |
|
|
#define AT91_SPI1_NPCS2X AT91_PIN(0,1,26) // SPI 1 Chip Select 2
|
577 |
|
|
#define AT91_PCK_PCK3 AT91_PIN(0,1,27) // Programmable Clock Output 3
|
578 |
|
|
#define AT91_SPI1_NPCS3X AT91_PIN(0,1,29) // SPI 1 Chip Select 3
|
579 |
|
|
#define AT91_PCK_PCK2 AT91_PIN(0,1,30) // Programmable Clock Output 2
|
580 |
|
|
|
581 |
|
|
//PIO Controller B, Peripheral A
|
582 |
|
|
#define AT91_EMAC_EREFCK AT91_PIN(1,0, 0) // EMAC Reference Clock
|
583 |
|
|
#define AT91_EMAC_ETXEN AT91_PIN(1,0, 1) // EMAC Transmit Enable
|
584 |
|
|
#define AT91_EMAC_ETX0 AT91_PIN(1,0, 2) // EMAC Transmit Data 0
|
585 |
|
|
#define AT91_EMAC_ETX1 AT91_PIN(1,0, 3) // EMAC Transmit Data 1
|
586 |
|
|
#define AT91_EMAC_ECRS AT91_PIN(1,0, 4) // EMAC Carrier Sense
|
587 |
|
|
#define AT91_EMAC_ERX0 AT91_PIN(1,0, 5) // EMAC Receive Data 0
|
588 |
|
|
#define AT91_EMAC_ERX1 AT91_PIN(1,0, 6) // EMAC Receive Data 1
|
589 |
|
|
#define AT91_EMAC_ERXER AT91_PIN(1,0, 7) // EMAC Receive Error
|
590 |
|
|
#define AT91_EMAC_EMDC AT91_PIN(1,0, 8) // EMAC Management Data Clock
|
591 |
|
|
#define AT91_EMAC_EMDIO AT91_PIN(1,0, 9) // EMAC Management Data IO
|
592 |
|
|
#define AT91_EMAC_ETX2 AT91_PIN(1,0,10) // EMAC Transmit Data 2
|
593 |
|
|
#define AT91_EMAC_ETX3 AT91_PIN(1,0,11) // EMAC Transmit Data 3
|
594 |
|
|
#define AT91_EMAC_ETXER AT91_PIN(1,0,12) // EMAC Transmit Coding Error
|
595 |
|
|
#define AT91_EMAC_ERX2 AT91_PIN(1,0,13) // EMAC Receive Data 2
|
596 |
|
|
#define AT91_EMAC_ERX3 AT91_PIN(1,0,14) // EMAC Receive Data 3
|
597 |
|
|
#define AT91_EMAC_ECRSDV AT91_PIN(1,0,15) // EMAC Carrier Sense And Data Valid
|
598 |
|
|
#define AT91_EMAC_ERXDV AT91_PIN(1,0,15) // EMAC Receive Data Valid
|
599 |
|
|
#define AT91_EMAC_ECOL AT91_PIN(1,0,16) // EMAC Collision Detected
|
600 |
|
|
#define AT91_EMAC_ERXCK AT91_PIN(1,0,17) // EMAC Receive Clock
|
601 |
|
|
#define AT91_EMAC_EF100 AT91_PIN(1,0,18) // EMAC Force 100Mb/s
|
602 |
|
|
#define AT91_PWM_PWM0 AT91_PIN(1,0,19) // Pulse Width Modulation #0
|
603 |
|
|
#define AT91_PWM_PWM1 AT91_PIN(1,0,20) // Pulse Width Modulation #1
|
604 |
|
|
#define AT91_PWM_PWM2 AT91_PIN(1,0,21) // Pulse Width Modulation #2
|
605 |
|
|
#define AT91_PWM_PWM3 AT91_PIN(1,0,22) // Pulse Width Modulation #3
|
606 |
|
|
#define AT91_TC_TIOA0 AT91_PIN(1,0,23) // Timer/Counter 0 IO Line A
|
607 |
|
|
#define AT91_TC_TIOB0 AT91_PIN(1,0,24) // Timer/Counter 0 IO Line B
|
608 |
|
|
#define AT91_TC_TIOA1 AT91_PIN(1,0,25) // Timer/Counter 1 IO Line A
|
609 |
|
|
#define AT91_TC_TIOB1 AT91_PIN(1,0,26) // Timer/Counter 1 IO Line B
|
610 |
|
|
#define AT91_TC_TIOA2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line A
|
611 |
|
|
#define AT91_TC_TIOB2 AT91_PIN(1,0,28) // Timer/Counter 2 IO Line B
|
612 |
|
|
#define AT91_PCK_PCK1X AT91_PIN(1,0,29) // Programmable Clock Output 1
|
613 |
|
|
#define AT91_PCK_PCK2X AT91_PIN(1,0,30) // Programmable Clock Output 2
|
614 |
|
|
|
615 |
|
|
//PIO Controller B Peripheral B
|
616 |
|
|
#define AT91_PCK_PCK0 AT91_PIN(1,1, 0) // Programmable Clock Output 0
|
617 |
|
|
#define AT91_SPI1_NPCS1XX AT91_PIN(1,1,10) // SPI 1 Chip Select 1
|
618 |
|
|
#define AT91_SPI1_NPCS2XX AT91_PIN(1,1,11) // SPI 1 Chip Select 2
|
619 |
|
|
#define AT91_TC_TCLK0 AT91_PIN(1,1,12) // Timer/Counter 0 Clock Input
|
620 |
|
|
#define AT91_SPI_NPCS1XX AT91_PIN(1,1,13) // SPI 0 Chip Select 1
|
621 |
|
|
#define AT91_SPI_NPCS2XX AT91_PIN(1,1,14) // SPI 0 Chip Select 2
|
622 |
|
|
#define AT91_SPI1_NPCS3XX AT91_PIN(1,1,16) // SPI 1 Chip Select 3
|
623 |
|
|
#define AT91_SPI_NPCS3XX AT91_PIN(1,1,17) // SPI 0 Chip Select 3
|
624 |
|
|
#define AT91_ADC_ADTRG AT91_PIN(1,1,18) // ADC Trigger
|
625 |
|
|
#define AT91_TC_TCLK1X AT91_PIN(1,1,19) // Timer/Counter 1 Clock Input
|
626 |
|
|
#define AT91_PCK_PCK0X AT91_PIN(1,1,20) // Programmable Clock Output 0
|
627 |
|
|
#define AT91_PCK_PCK1XX AT91_PIN(1,1,21) // Programmable Clock Output 1
|
628 |
|
|
#define AT91_PCK_PCK2XX AT91_PIN(1,1,22) // Programmable Clock Output 2
|
629 |
|
|
#define AT91_USART_DCD1 AT91_PIN(1,1,23) // USART 1 Data Carrier Detect
|
630 |
|
|
#define AT91_USART_DSR1 AT91_PIN(1,1,24) // USART 1 Data Set Ready
|
631 |
|
|
#define AT91_USART_DTR1 AT91_PIN(1,1,25) // USART 1 Data Terminal Ready
|
632 |
|
|
#define AT91_USART_RI1 AT91_PIN(1,1,26) // USART 1 Ring Indication
|
633 |
|
|
#define AT91_PWM_PWM0X AT91_PIN(1,1,27) // Pulse Width Modulation #0
|
634 |
|
|
#define AT91_PWM_PWM1X AT91_PIN(1,1,28) // Pulse Width Modulation #1
|
635 |
|
|
#define AT91_PWM_PWM2X AT91_PIN(1,1,29) // Pulse Width Modulation #2
|
636 |
|
|
#define AT91_PWM_PWM3X AT91_PIN(1,1,30) // Pulse Width Modulation #3
|
637 |
|
|
|
638 |
|
|
// PIO Controller A, peripheral A
|
639 |
|
|
#define AT91_PIO_PSR_RXD0 (1<< 0) // USART 0 Receive Data
|
640 |
|
|
#define AT91_PIO_PSR_TXD0 (1<< 1) // USART 0 Transmit Data
|
641 |
|
|
#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
|
642 |
|
|
#define AT91_PIO_PSR_RTS0 (1<< 3) // USART 0 Request To Send
|
643 |
|
|
#define AT91_PIO_PSR_CTS0 (1<< 4) // USART 0 Clear To Send
|
644 |
|
|
#define AT91_PIO_PSR_RXD1 (1<< 5) // USART 1 Receive Data
|
645 |
|
|
#define AT91_PIO_PSR_TXD1 (1<< 6) // USART 1 Transmit Data
|
646 |
|
|
#define AT91_PIO_PSR_SCK1 (1<< 7) // USART 1 Serial Clock
|
647 |
|
|
#define AT91_PIO_PSR_RTS1 (1<< 8) // USART 1 Request To Send
|
648 |
|
|
#define AT91_PIO_PSR_CTS1 (1<< 9) // USART 1 Clear To Send
|
649 |
|
|
#define AT91_PIO_PSR_TWD (1<<10) // Two Wire Data
|
650 |
|
|
#define AT91_PIO_PSR_TWCK (1<<11) // Two Wire Clock
|
651 |
|
|
#define AT91_PIO_PSR_SPI_NPCS0 (1<<12) // SPI 0 Chip Select 0
|
652 |
|
|
#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
|
653 |
|
|
#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
|
654 |
|
|
#define AT91_PIO_PSR_SPI_NPCS3 (1<<15) // SPI 0 Chip Select 3
|
655 |
|
|
#define AT91_PIO_PSR_SPI_MISO (1<<16) // SPI 0 Master In Slave Out
|
656 |
|
|
#define AT91_PIO_PSR_SPI_MOSI (1<<17) // SPI 0 Master Out Slave In
|
657 |
|
|
#define AT91_PIO_PSR_SPI_SPCK (1<<18) // SPI 0 Clock
|
658 |
|
|
#define AT91_PIO_PSR_CANRX (1<<19) // CAN Receive
|
659 |
|
|
#define AT91_PIO_PSR_CANTX (1<<20) // CAN Transmit
|
660 |
|
|
#define AT91_PIO_PSR_TF (1<<21) // SSC Transmit Frame Sync
|
661 |
|
|
#define AT91_PIO_PSR_TK (1<<22) // SSC Transmit Clock
|
662 |
|
|
#define AT91_PIO_PSR_TD (1<<23) // SSC Transmit Data
|
663 |
|
|
#define AT91_PIO_PSR_RD (1<<24) // SSC Receive Data
|
664 |
|
|
#define AT91_PIO_PSR_RK (1<<25) // SSC Receive Clock
|
665 |
|
|
#define AT91_PIO_PSR_RF (1<<26) // SSC Receive Frame Sync
|
666 |
|
|
#define AT91_PIO_PSR_DRXD (1<<27) // DBGU Receive Data
|
667 |
|
|
#define AT91_PIO_PSR_DTXD (1<<28) // DBGU Transmit Data
|
668 |
|
|
#define AT91_PIO_PSR_FIQ (1<<29) // Fast Interrupt Request
|
669 |
|
|
#define AT91_PIO_PSR_IRQ0 (1<<30) // Interrupt Request 0
|
670 |
|
|
|
671 |
|
|
//PIO controller A, peripheral B
|
672 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS1 (1<< 2) // SPI 1 Chip Select 1
|
673 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS2 (1<< 3) // SPI 1 Chip Select 2
|
674 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS3 (1<< 4) // SPI 1 Chip Select 3
|
675 |
|
|
#define AT91_PIO_PSR_SPI_NPCS1X (1<< 7) // SPI 0 Chip Select 1
|
676 |
|
|
#define AT91_PIO_PSR_SPI_NPCS2X (1<< 8) // SPI 0 Chip Select 2
|
677 |
|
|
#define AT91_PIO_PSR_SPI_NPCS3X (1<< 9) // SPI 0 Chip Select 3
|
678 |
|
|
#define AT91_PIO_PSR_PCK1 (1<<13) // Programmable Clock Output 1
|
679 |
|
|
#define AT91_PIO_PSR_IRQ1 (1<<14) // Interrupt Request 1
|
680 |
|
|
#define AT91_PIO_PSR_TCLK1 (1<<15) // Timer/Counter 1 Clock Input
|
681 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS0 (1<<21) // SPI 1 Chip Select 0
|
682 |
|
|
#define AT91_PIO_PSR_SPI1_SPCK (1<<22) // SPI 1 Clock
|
683 |
|
|
#define AT91_PIO_PSR_SPI1_MOSI (1<<23) // SPI 1 Master Out Slave In
|
684 |
|
|
#define AT91_PIO_PSR_SPI1_MISO (1<<24) // SPI 0 Master In Slave Out
|
685 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS1X (1<<25) // SPI 1 Chip Select 1
|
686 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS2X (1<<26) // SPI 1 Chip Select 2
|
687 |
|
|
#define AT91_PIO_PSR_PCK3 (1<<27) // Programmable Clock Output 3
|
688 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS3X (1<<29) // SPI 1 Chip Select 3
|
689 |
|
|
#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
|
690 |
|
|
|
691 |
|
|
//PIO Controller B, Peripheral A
|
692 |
|
|
#define AT91_PIO_PSR_EREFCK (1<< 0) // EMAC Reference Clock
|
693 |
|
|
#define AT91_PIO_PSR_ETXEN (1<< 1) // EMAC Transmit Enable
|
694 |
|
|
#define AT91_PIO_PSR_ETX0 (1<< 2) // EMAC Transmit Data 0
|
695 |
|
|
#define AT91_PIO_PSR_ETX1 (1<< 3) // EMAC Transmit Data 1
|
696 |
|
|
#define AT91_PIO_PSR_ECRS (1<< 4) // EMAC Carrier Sense
|
697 |
|
|
#define AT91_PIO_PSR_ERX0 (1<< 5) // EMAC Receive Data 0
|
698 |
|
|
#define AT91_PIO_PSR_ERX1 (1<< 6) // EMAC Receive Data 1
|
699 |
|
|
#define AT91_PIO_PSR_ERXER (1<< 7) // EMAC Receive Error
|
700 |
|
|
#define AT91_PIO_PSR_EMDC (1<< 8) // EMAC Management Data Clock
|
701 |
|
|
#define AT91_PIO_PSR_EMDIO (1<< 9) // EMAC Management Data IO
|
702 |
|
|
#define AT91_PIO_PSR_ETX2 (1<<10) // EMAC Transmit Data 2
|
703 |
|
|
#define AT91_PIO_PSR_ETX3 (1<<11) // EMAC Transmit Data 3
|
704 |
|
|
#define AT91_PIO_PSR_ETXER (1<<12) // EMAC Transmit Coding Error
|
705 |
|
|
#define AT91_PIO_PSR_ERX2 (1<<13) // EMAC Receive Data 2
|
706 |
|
|
#define AT91_PIO_PSR_ERX3 (1<<14) // EMAC Receive Data 3
|
707 |
|
|
#define AT91_PIO_PSR_ECRSDV (1<<15) // EMAC Carrier Sense And Data Valid
|
708 |
|
|
#define AT91_PIO_PSR_ECOL (1<<16) // EMAC Collision Detected
|
709 |
|
|
#define AT91_PIO_PSR_ERXCK (1<<17) // EMAC Receive Clock
|
710 |
|
|
#define AT91_PIO_PSR_EF100 (1<<18) // EMAC Force 100Mb/s
|
711 |
|
|
#define AT91_PIO_PSR_PWM0 (1<<19) // Pulse Width Modulation #0
|
712 |
|
|
#define AT91_PIO_PSR_PWM1 (1<<20) // Pulse Width Modulation #1
|
713 |
|
|
#define AT91_PIO_PSR_PWM2 (1<<21) // Pulse Width Modulation #2
|
714 |
|
|
#define AT91_PIO_PSR_PWM3 (1<<22) // Pulse Width Modulation #3
|
715 |
|
|
#define AT91_PIO_PSR_TIOA0 (1<<23) // Timer/Counter 0 IO Line A
|
716 |
|
|
#define AT91_PIO_PSR_TIOB0 (1<<24) // Timer/Counter 0 IO Line B
|
717 |
|
|
#define AT91_PIO_PSR_TIOA1 (1<<25) // Timer/Counter 1 IO Line A
|
718 |
|
|
#define AT91_PIO_PSR_TIOB1 (1<<26) // Timer/Counter 1 IO Line B
|
719 |
|
|
#define AT91_PIO_PSR_TIOA2 (1<<27) // Timer/Counter 2 IO Line A
|
720 |
|
|
#define AT91_PIO_PSR_TIOB2 (1<<28) // Timer/Counter 2 IO Line B
|
721 |
|
|
#define AT91_PIO_PSR_PCK1X (1<<29) // Programmable Clock Output 1
|
722 |
|
|
#define AT91_PIO_PSR_PCK2 (1<<30) // Programmable Clock Output 2
|
723 |
|
|
|
724 |
|
|
//PIO Controller B Peripheral B
|
725 |
|
|
#define AT91_PIO_PSR_PCK0 (1<< 0) // Programmable Clock Output 0
|
726 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS1XX (1<<10) // SPI 1 Chip Select 1
|
727 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS2XX (1<<11) // SPI 1 Chip Select 2
|
728 |
|
|
#define AT91_PIO_PSR_TCLK0 (1<<12) // Timer/Counter 0 Clock Input
|
729 |
|
|
#define AT91_PIO_PSR_SPI_NPCS1 (1<<13) // SPI 0 Chip Select 1
|
730 |
|
|
#define AT91_PIO_PSR_SPI_NPCS2 (1<<14) // SPI 0 Chip Select 2
|
731 |
|
|
#define AT91_PIO_PSR_SPI1_NPCS3XX (1<<16) // SPI 1 Chip Select 3
|
732 |
|
|
#define AT91_PIO_PSR_SPI_NPCS3XX (1<<17) // SPI 0 Chip Select 3
|
733 |
|
|
#define AT91_PIO_PSR_ADTRG (1<<18) // ADC Trigger
|
734 |
|
|
#define AT91_PIO_PSR_TCLK1X (1<<19) // Timer/Counter 1 Clock Input
|
735 |
|
|
#define AT91_PIO_PSR_PCK0X (1<<20) // Programmable Clock Output 0
|
736 |
|
|
#define AT91_PIO_PSR_PCK1XX (1<<21) // Programmable Clock Output 1
|
737 |
|
|
#define AT91_PIO_PSR_PCK2X (1<<22) // Programmable Clock Output 2
|
738 |
|
|
#define AT91_PIO_PSR_DCD1 (1<<23) // USART 1 Data Carrier Detect
|
739 |
|
|
#define AT91_PIO_PSR_DSR1 (1<<24) // USART 1 Data Set Ready
|
740 |
|
|
#define AT91_PIO_PSR_DTR1 (1<<25) // USART 1 Data Terminal Ready
|
741 |
|
|
#define AT91_PIO_PSR_RI1 (1<<26) // USART 1 Ring Indication
|
742 |
|
|
#define AT91_PIO_PSR_PWM0X (1<<27) // Pulse Width Modulation #0
|
743 |
|
|
#define AT91_PIO_PSR_PWM1X (1<<28) // Pulse Width Modulation #1
|
744 |
|
|
#define AT91_PIO_PSR_PWM2X (1<<29) // Pulse Width Modulation #2
|
745 |
|
|
#define AT91_PIO_PSR_PWM3X (1<<30) // Pulse Width Modulation #3
|
746 |
|
|
#endif // CYGHWR_HAL_ARM_AT91SAM7X
|
747 |
|
|
|
748 |
|
|
#ifdef CYGHWR_HAL_ARM_AT91SAM7XC
|
749 |
|
|
#error Sorry, still missing. Happy typing
|
750 |
|
|
#endif
|
751 |
|
|
|
752 |
|
|
#ifdef CYGHWR_HAL_ARM_AT91SAM7SE
|
753 |
|
|
//PIO Controller A Peripheral A
|
754 |
|
|
#define AT91_PWM_PWM0 AT91_PIN(0,0, 0) // Pulse Width Modulation 0
|
755 |
|
|
#define AT91_PWM_PWM1 AT91_PIN(0,0, 1) // Pulse Width Modulation 1
|
756 |
|
|
#define AT91_PWM_PWM2 AT91_PIN(0,0, 2) // Pulse Width Modulation 2
|
757 |
|
|
#define AT91_TWI_TWD AT91_PIN(0,0, 3) // Two Wire Data
|
758 |
|
|
#define AT91_TWI_TWCK AT91_PIN(0,0, 4) // Two Wire Clock
|
759 |
|
|
#define AT91_USART_RXD0 AT91_PIN(0,0, 5) // USART 0 Receive Data
|
760 |
|
|
#define AT91_USART_TXD0 AT91_PIN(0,0, 6) // USART 0 Transmit Data
|
761 |
|
|
#define AT91_USART_RTS0 AT91_PIN(0,0, 7) // USART 0 Ready To Send
|
762 |
|
|
#define AT91_USART_CTS0 AT91_PIN(0,0, 8) // USART 0 Clear To Send
|
763 |
|
|
#define AT91_DBG_DRXD AT91_PIN(0,0, 9) // Debug UART Receive
|
764 |
|
|
#define AT91_DBG_DTXD AT91_PIN(0,0,10) // Debug UART Transmit
|
765 |
|
|
#define AT91_SPI_NPCS0 AT91_PIN(0,0,11) // SPI Chip Select 0
|
766 |
|
|
#define AT91_SPI_MISO AT91_PIN(0,0,12) // SPI Input
|
767 |
|
|
#define AT91_SPI_MOSI AT91_PIN(0,0,13) // SPI Output
|
768 |
|
|
#define AT91_SPI_SPCK AT91_PIN(0,0,14) // SPI clock
|
769 |
|
|
#define AT91_S2C_TF AT91_PIN(0,0,15) // S2C Transmit Frame Sync
|
770 |
|
|
#define AT91_S2C_TK AT91_PIN(0,0,16) // S2C Transmit Clock
|
771 |
|
|
#define AT91_S2C_TD AT91_PIN(0,0,17) // S2C Transmit Data
|
772 |
|
|
#define AT91_S2C_RD AT91_PIN(0,0,18) // S2C Receive Data
|
773 |
|
|
#define AT91_S2C_RK AT91_PIN(0,0,19) // S2C Receive Clock
|
774 |
|
|
#define AT91_S2C_RF AT91_PIN(0,0,20) // S2C Receive Frame Sync
|
775 |
|
|
#define AT91_USART_RXD1 AT91_PIN(0,0,21) // USART 1 Receive Data
|
776 |
|
|
#define AT91_USART_TXD1 AT91_PIN(0,0,22) // USART 1 Transmit Data
|
777 |
|
|
#define AT91_USART_SCK1 AT91_PIN(0,0,23) // USART 1 Serial Clock
|
778 |
|
|
#define AT91_USART_RTS1 AT91_PIN(0,0,24) // USART 1 Ready To Send
|
779 |
|
|
#define AT91_USART_CTS1 AT91_PIN(0,0,25) // USART 1 Clear To Send
|
780 |
|
|
#define AT91_USART_DVD1 AT91_PIN(0,0,26) // USART 1 Data Carrier Detect
|
781 |
|
|
#define AT91_USART_DTR1 AT91_PIN(0,0,27) // USART 1 Data Terminal Ready
|
782 |
|
|
#define AT91_USART_DSR1 AT91_PIN(0,0,28) // USART 1 Data Set Ready
|
783 |
|
|
#define AT91_USART_RI1 AT91_PIN(0,0,29) // USART 2 Ring Indicator
|
784 |
|
|
#define AT91_INT_IRQ1 AT91_PIN(0,0,30) // Interrupt Request 1
|
785 |
|
|
#define AT91_SPI_NPCS1 AT91_PIN(0,0,31) // SPI Chip Select 1
|
786 |
|
|
|
787 |
|
|
//PIO Controller A Peripheral B
|
788 |
|
|
#define AT91_EBI_A0_NBS0 AT91_PIN(0,1, 0) // EBI: Addr 0 / SDRAM Byte Mask 0
|
789 |
|
|
#define AT91_EBI_A1_NBS2 AT91_PIN(0,1, 1) // EBI: Addr 1 / SDRAM Byte Mask 2
|
790 |
|
|
#define AT91_EBI_A2 AT91_PIN(0,1, 2) // EBI: Addr 2
|
791 |
|
|
#define AT91_EBI_A3 AT91_PIN(0,1, 3) // EBI: Addr 3
|
792 |
|
|
#define AT91_EBI_A4 AT91_PIN(0,1, 4) // EBI: Addr 4
|
793 |
|
|
#define AT91_EBI_A5 AT91_PIN(0,1, 5) // EBI: Addr 5
|
794 |
|
|
#define AT91_EBI_A6 AT91_PIN(0,1, 6) // EBI: Addr 6
|
795 |
|
|
#define AT91_EBI_A7 AT91_PIN(0,1, 7) // EBI: Addr 7
|
796 |
|
|
#define AT91_EBI_A8 AT91_PIN(0,1, 8) // EBI: Addr 8
|
797 |
|
|
#define AT91_EBI_A9 AT91_PIN(0,1, 9) // EBI: Addr 9
|
798 |
|
|
#define AT91_EBI_A10 AT91_PIN(0,1,10) // EBI: Addr 10
|
799 |
|
|
#define AT91_EBI_A11 AT91_PIN(0,1,11) // EBI: Addr 11
|
800 |
|
|
#define AT91_EBI_A12 AT91_PIN(0,1,12) // EBI: Addr 12
|
801 |
|
|
#define AT91_EBI_A13 AT91_PIN(0,1,13) // EBI: Addr 13
|
802 |
|
|
#define AT91_EBI_A14 AT91_PIN(0,1,14) // EBI: Addr 14
|
803 |
|
|
#define AT91_EBI_A15 AT91_PIN(0,1,15) // EBI: Addr 15
|
804 |
|
|
#define AT91_EBI_A16_BA0 AT91_PIN(0,1,16) // EBI: Addr 16 / SDRAM Bank Sel 0
|
805 |
|
|
#define AT91_EBI_A17_BA1 AT91_PIN(0,1,17) // EBI: Addr 17 / SDRAM Bank Sel 1
|
806 |
|
|
#define AT91_EBI_NBS3_CFIOW AT91_PIN(0,1,18) // EBI: SDRAM Byte Mask 3 /
|
807 |
|
|
// CompactFlash I/O Write Signal
|
808 |
|
|
#define AT91_EBI_NCS4_CFCS0 AT91_PIN(0,1,19) // EBI: Chip Select 4 /
|
809 |
|
|
// CompactFlash Chip Select 0
|
810 |
|
|
#define AT91_EBI_NCS2_CFCS1 AT91_PIN(0,1,20) // EBI: Chip Select 2 /
|
811 |
|
|
// CompactFlash Chip Select 1
|
812 |
|
|
#define AT91_EBI_NCS6_CFCE2 AT91_PIN(0,1,21) // EBI: Chip Select 6 /
|
813 |
|
|
// CompactFlash Chip Enable 2
|
814 |
|
|
#define AT91_EBI_NCS5_CFCE1 AT91_PIN(0,1,22) // EBI: Chip Select 5 /
|
815 |
|
|
// CompactFlash Chip Enable 1
|
816 |
|
|
#define AT91_EBI_NWR1_NBS1_CFIOR \
|
817 |
|
|
AT91_PIN(0,1,23) // EBI: SMC Write 1 /
|
818 |
|
|
// SDRAM Byte Mask 1 /
|
819 |
|
|
// CompactFlash I/O Read Signal
|
820 |
|
|
#define AT91_EBI_SDA10 AT91_PIN(0,1,24) // EBI: SDRAM Address 10
|
821 |
|
|
#define AT91_EBI_SDCKE AT91_PIN(0,1,25) // EBI: SDRAM Clock Enable
|
822 |
|
|
#define AT91_EBI_NCS1_SDCS AT91_PIN(0,1,26) // EBI: Chip Select 1 /
|
823 |
|
|
// SDRAM Controller Chip Select
|
824 |
|
|
#define AT91_EBI_SDWE AT91_PIN(0,1,27) // EBI: SDRAM Write Enable
|
825 |
|
|
#define AT91_EBI_CAS AT91_PIN(0,1,28) // EBI: SDRAM Column Signal
|
826 |
|
|
#define AT91_EBI_RAS AT91_PIN(0,1,29) // EBI: SDRAM Row Signal
|
827 |
|
|
#define AT91_EBI_D30 AT91_PIN(0,1,30) // EBI: Data 30
|
828 |
|
|
#define AT91_EBI_D31 AT91_PIN(0,1,31) // EBI: Data 31
|
829 |
|
|
|
830 |
|
|
//PIO Controller A Peripheral A
|
831 |
|
|
#define AT91_PIO_PSR_PWM0 (1<< 0) // Pulse Width Modulation 0
|
832 |
|
|
#define AT91_PIO_PSR_PWM1 (1<< 1) // Pulse Width Modulation 1
|
833 |
|
|
#define AT91_PIO_PSR_PWM2 (1<< 2) // Pulse Width Modulation 2
|
834 |
|
|
#define AT91_PIO_PSR_TWD (1<< 3) // Two Wire Data
|
835 |
|
|
#define AT91_PIO_PSR_TWCK (1<< 4) // Two Wire Clock
|
836 |
|
|
#define AT91_PIO_PSR_RXD0 (1<< 5) // USART 0 Receive Data
|
837 |
|
|
#define AT91_PIO_PSR_TXD0 (1<< 6) // USART 0 Transmit Data
|
838 |
|
|
#define AT91_PIO_PSR_RTS0 (1<< 7) // USART 0 Ready To Send
|
839 |
|
|
#define AT91_PIO_PSR_CTS0 (1<< 8) // USART 0 Clear To Send
|
840 |
|
|
#define AT91_PIO_PSR_DRXD (1<< 9) // Debug UART Receive
|
841 |
|
|
#define AT91_PIO_PSR_DTXD (1<<10) // Debug UART Transmit
|
842 |
|
|
#define AT91_PIO_PSR_NPCS0 (1<<11) // SPI Chip Select 0
|
843 |
|
|
#define AT91_PIO_PSR_MISO (1<<12) // SPI Input
|
844 |
|
|
#define AT91_PIO_PSR_MOSI (1<<13) // SPI Output
|
845 |
|
|
#define AT91_PIO_PSR_SPCK (1<<14) // SPI clock
|
846 |
|
|
#define AT91_PIO_PSR_TF (1<<15) // S2C Transmit Frame Sync
|
847 |
|
|
#define AT91_PIO_PSR_TK (1<<16) // S2C Transmit Clock
|
848 |
|
|
#define AT91_PIO_PSR_TD (1<<17) // S2C Transmit Data
|
849 |
|
|
#define AT91_PIO_PSR_RD (1<<18) // S2C Receive Data
|
850 |
|
|
#define AT91_PIO_PSR_RK (1<<19) // S2C Receive Clock
|
851 |
|
|
#define AT91_PIO_PSR_RF (1<<20) // S2C Receive Frame Sync
|
852 |
|
|
#define AT91_PIO_PSR_RXD1 (1<<21) // USART 1 Receive Data
|
853 |
|
|
#define AT91_PIO_PSR_TXD1 (1<<22) // USART 1 Transmit Data
|
854 |
|
|
#define AT91_PIO_PSR_SCK1 (1<<23) // USART 1 Serial Clock
|
855 |
|
|
#define AT91_PIO_PSR_RTS1 (1<<24) // USART 1 Ready To Send
|
856 |
|
|
#define AT91_PIO_PSR_CTS1 (1<<25) // USART 1 Clear To Send
|
857 |
|
|
#define AT91_PIO_PSR_DVD1 (1<<26) // USART 1 Data Carrier Detect
|
858 |
|
|
#define AT91_PIO_PSR_DTR1 (1<<27) // USART 1 Data Terminal Ready
|
859 |
|
|
#define AT91_PIO_PSR_DSR1 (1<<28) // USART 1 Data Set Ready
|
860 |
|
|
#define AT91_PIO_PSR_RI1 (1<<29) // USART 2 Ring Indicator
|
861 |
|
|
#define AT91_PIO_PSR_IRQ1 (1<<30) // Interrupt Request 1
|
862 |
|
|
#define AT91_PIO_PSR_NPCS1 (1<<31) // SPI Chip Select 1
|
863 |
|
|
|
864 |
|
|
//PIO Controller A Peripheral B
|
865 |
|
|
#define AT91_PIO_PSR_A0_NBS0 (1<< 0) // EBI: Address 0 / SDRAM Byte Mask 0
|
866 |
|
|
#define AT91_PIO_PSR_A1_NBS2 (1<< 1) // EBI: Address 1 / SDRAM Byte Mask 2
|
867 |
|
|
#define AT91_PIO_PSR_A2 (1<< 2) // EBI: Address 2
|
868 |
|
|
#define AT91_PIO_PSR_A3 (1<< 3) // EBI: Address 3
|
869 |
|
|
#define AT91_PIO_PSR_A4 (1<< 4) // EBI: Address 4
|
870 |
|
|
#define AT91_PIO_PSR_A5 (1<< 5) // EBI: Address 5
|
871 |
|
|
#define AT91_PIO_PSR_A6 (1<< 6) // EBI: Address 6
|
872 |
|
|
#define AT91_PIO_PSR_A7 (1<< 7) // EBI: Address 7
|
873 |
|
|
#define AT91_PIO_PSR_A8 (1<< 8) // EBI: Address 8
|
874 |
|
|
#define AT91_PIO_PSR_A9 (1<< 9) // EBI: Address 9
|
875 |
|
|
#define AT91_PIO_PSR_A10 (1<<10) // EBI: Address 10
|
876 |
|
|
#define AT91_PIO_PSR_A11 (1<<11) // EBI: Address 11
|
877 |
|
|
#define AT91_PIO_PSR_A12 (1<<12) // EBI: Address 12
|
878 |
|
|
#define AT91_PIO_PSR_A13 (1<<13) // EBI: Address 13
|
879 |
|
|
#define AT91_PIO_PSR_A14 (1<<14) // EBI: Address 14
|
880 |
|
|
#define AT91_PIO_PSR_A15 (1<<15) // EBI: Address 15
|
881 |
|
|
#define AT91_PIO_PSR_A16_BA0 (1<<16) // EBI: Address 16 / SDRAM Bank Sel 0
|
882 |
|
|
#define AT91_PIO_PSR_A17_BA1 (1<<17) // EBI: Address 17 / SDRAM Bank Sel 1
|
883 |
|
|
#define AT91_PIO_PSR_NBS3_CFIOW (1<<18) // EBI: SDRAM Byte Mask 3 /
|
884 |
|
|
// CompactFlash I/O Write Signal
|
885 |
|
|
#define AT91_PIO_PSR_NCS4_CFCS0 (1<<19) // EBI: Chip Select 4 /
|
886 |
|
|
// CompactFlash Chip Select 0
|
887 |
|
|
#define AT91_PIO_PSR_NCS2_CFCS1 (1<<20) // EBI: Chip Select 2 /
|
888 |
|
|
// CompactFlash Chip Select 1
|
889 |
|
|
#define AT91_PIO_PSR_NCS6_CFCE2 (1<<21) // EBI: Chip Select 6 /
|
890 |
|
|
// CompactFlash Chip Enable 2
|
891 |
|
|
#define AT91_PIO_PSR_NCS5_CFCE1 (1<<22) // EBI: Chip Select 5 /
|
892 |
|
|
// CompactFlash Chip Enable 1
|
893 |
|
|
#define AT91_PIO_PSR_NWR1_NBS1_CFIOR \
|
894 |
|
|
(1<<23) // EBI: Write 1 / SDRAM Byte Mask 1 /
|
895 |
|
|
// CompactFlash I/O Read Signal
|
896 |
|
|
#define AT91_PIO_PSR_SDA10 (1<<24) // EBI: SDRAM Address 10
|
897 |
|
|
#define AT91_PIO_PSR_SDCKE (1<<25) // EBI: SDRAM Clock Enable
|
898 |
|
|
#define AT91_PIO_PSR_NCS1_SDCS (1<<26) // EBI: Chip Select 1 /
|
899 |
|
|
// SDRAM Controller Chip Select
|
900 |
|
|
#define AT91_PIO_PSR_SDWE (1<<27) // EBI: SDRAM Write Enable
|
901 |
|
|
#define AT91_PIO_PSR_CAS (1<<28) // EBI: SDRAM Column Signal
|
902 |
|
|
#define AT91_PIO_PSR_RAS (1<<29) // EBI: SDRAM Row Signal
|
903 |
|
|
#define AT91_PIO_PSR_D30 (1<<30) // EBI: Data 30
|
904 |
|
|
#define AT91_PIO_PSR_D31 (1<<31) // EBI: Data 31
|
905 |
|
|
|
906 |
|
|
//PIO Controller B Peripheral A
|
907 |
|
|
#define AT91_TC_TIOA0 AT91_PIN(1,0, 0) // Timer/Counter 0 IO Line A
|
908 |
|
|
#define AT91_TC_TIOB0 AT91_PIN(1,0, 1) // Timer/Counter 0 IO Line B
|
909 |
|
|
#define AT91_USART_SCK0 AT91_PIN(1,0, 2) // USART 0 Serial Clock
|
910 |
|
|
#define AT91_SPI_NPCS3 AT91_PIN(1,0, 3) // SPI Chip Select 3
|
911 |
|
|
#define AT91_TC_TCLK0 AT91_PIN(1,0, 4) // Timer/Counter 0 Clock Input
|
912 |
|
|
#define AT91_SPI_NPCS3X AT91_PIN(1,0, 5) // SPI Chip Select 3 (again)
|
913 |
|
|
#define AT91_PCK_PCK0 AT91_PIN(1,0, 6) // Programmable Clock Output 0
|
914 |
|
|
#define AT91_PWM_PWM3 AT91_PIN(1,0, 7) // Pulse Width Modulation #3
|
915 |
|
|
#define AT91_ADC_ADTRG AT91_PIN(1,0, 8) // ADC Trigger
|
916 |
|
|
#define AT91_SPI_NPCS1X AT91_PIN(1,0, 9) // SPI Chip Select 1
|
917 |
|
|
#define AT91_SPI_NPCS2 AT91_PIN(1,0,10) // SPI Chip Select 2
|
918 |
|
|
#define AT91_PWM_PWM0X AT91_PIN(1,0,11) // Pulse Width Modulation #0
|
919 |
|
|
#define AT91_PIO_PWM_PWM1X AT91_PIN(1,0,12) // Pulse Width Modulation #1
|
920 |
|
|
#define AT91_PIO_PWM_PWM2X AT91_PIN(1,0,13) // Pulse Width Modulation #2
|
921 |
|
|
#define AT91_PIO_PWM_PWM4X AT91_PIN(1,0,14) // Pulse Width Modulation #4
|
922 |
|
|
#define AT91_TC_TIOA1 AT91_PIN(1,0,15) // Timer/Counter 1 IO Line A
|
923 |
|
|
#define AT91_TC_TIOB1 AT91_PIN(1,0,16) // Timer/Counter 1 IO Line B
|
924 |
|
|
#define AT91_PCK_PCK1 AT91_PIN(1,0,17) // Programmable Clock Output 1
|
925 |
|
|
#define AT91_PCK_PCK2 AT91_PIN(1,0,18) // Programmable Clock Output 2
|
926 |
|
|
#define AT91_INT_FIQ AT91_PIN(1,0,19) // Fast Interrupt Request
|
927 |
|
|
#define AT91_INT_IRQ0 AT91_PIN(1,0,20) // Interrupt Request 0
|
928 |
|
|
#define AT91_PCK_PCK1X AT91_PIN(1,0,21) // Programmable Clock Output 1
|
929 |
|
|
#define AT91_SPI_NPCS3XX AT91_PIN(1,0,22) // SPI Chip Select 3 (yet again)
|
930 |
|
|
#define AT91_PWM_PWM0XX AT91_PIN(1,0,23) // Pulse Width Modulation #0
|
931 |
|
|
#define AT91_PWM_PWM1XX AT91_PIN(1,0,24) // Pulse Width Modulation #1
|
932 |
|
|
#define AT91_PWM_PWM2XX AT91_PIN(1,0,25) // Pulse Width Modulation 2
|
933 |
|
|
#define AT91_TC_TIOA2 AT91_PIN(1,0,26) // Timer/Counter 2 IO Line A
|
934 |
|
|
#define AT91_TC_TIOB2 AT91_PIN(1,0,27) // Timer/Counter 2 IO Line B
|
935 |
|
|
#define AT91_TC_TCLK1 AT91_PIN(1,0,28) // External Clock Input 1
|
936 |
|
|
#define AT91_TC_TCLK2 AT91_PIN(1,0,29) // External Clock Input 2
|
937 |
|
|
#define AT91_SPI_NPCS2X AT91_PIN(1,0,30) // SPI Chip Select 2 (again)
|
938 |
|
|
#define AT91_PCK_PCK2X AT91_PIN(1,0,31) // Programmable Clock Output 2
|
939 |
|
|
|
940 |
|
|
//PIO Controller B Peripheral B
|
941 |
|
|
#define AT91_EBI_A0_NBS0X AT91_PIN(1,1, 0) // EBI: Addr 0 / SDRAM Byte Mask 0
|
942 |
|
|
#define AT91_EBI_A1_NBS2X AT91_PIN(1,1, 1) // EBI: Addr 1 / SDRAM Byte Mask 2
|
943 |
|
|
#define AT91_EBI_A2X AT91_PIN(1,1, 2) // EBI: Addr 2
|
944 |
|
|
#define AT91_EBI_A3X AT91_PIN(1,1, 3) // EBI: Addr 3
|
945 |
|
|
#define AT91_EBI_A4X AT91_PIN(1,1, 4) // EBI: Addr 4
|
946 |
|
|
#define AT91_EBI_A5X AT91_PIN(1,1, 5) // EBI: Addr 5
|
947 |
|
|
#define AT91_EBI_A6X AT91_PIN(1,1, 6) // EBI: Addr 6
|
948 |
|
|
#define AT91_EBI_A7X AT91_PIN(1,1, 7) // EBI: Addr 7
|
949 |
|
|
#define AT91_EBI_A8X AT91_PIN(1,1, 8) // EBI: Addr 8
|
950 |
|
|
#define AT91_EBI_A9X AT91_PIN(1,1, 9) // EBI: Addr 9
|
951 |
|
|
#define AT91_EBI_A10X AT91_PIN(1,1,10) // EBI: Addr 10
|
952 |
|
|
#define AT91_EBI_A11X AT91_PIN(1,1,11) // EBI: Addr 11
|
953 |
|
|
#define AT91_EBI_A12X AT91_PIN(1,1,12) // EBI: Addr 12
|
954 |
|
|
#define AT91_EBI_A13X AT91_PIN(1,1,13) // EBI: Addr 13
|
955 |
|
|
#define AT91_EBI_A14X AT91_PIN(1,1,14) // EBI: Addr 14
|
956 |
|
|
#define AT91_EBI_A15X AT91_PIN(1,1,15) // EBI: Addr 15
|
957 |
|
|
#define AT91_EBI_A16_BA0X AT91_PIN(1,1,16) // EBI: Addr 16 /
|
958 |
|
|
// SDRAM Bank Select 0
|
959 |
|
|
#define AT91_EBI_A17_BA1X AT91_PIN(1,1,17) // EBI: Addr 17 /
|
960 |
|
|
// SDRAM Bank Select 1
|
961 |
|
|
#define AT91_EBI_D16 AT91_PIN(1,1,18) // EBI: Data 16
|
962 |
|
|
#define AT91_EBI_D17 AT91_PIN(1,1,19) // EBI: Data 17
|
963 |
|
|
#define AT91_EBI_D18 AT91_PIN(1,1,20) // EBI: Data 18
|
964 |
|
|
#define AT91_EBI_D19 AT91_PIN(1,1,21) // EBI: Data 19
|
965 |
|
|
#define AT91_EBI_D20 AT91_PIN(1,1,22) // EBI: Data 20
|
966 |
|
|
#define AT91_EBI_D21 AT91_PIN(1,1,23) // EBI: Data 21
|
967 |
|
|
#define AT91_EBI_D22 AT91_PIN(1,1,24) // EBI: Data 22
|
968 |
|
|
#define AT91_EBI_D23 AT91_PIN(1,1,25) // EBI: Data 23
|
969 |
|
|
#define AT91_EBI_D24 AT91_PIN(1,1,26) // EBI: Data 24
|
970 |
|
|
#define AT91_EBI_D25 AT91_PIN(1,1,27) // EBI: Data 25
|
971 |
|
|
#define AT91_EBI_D26 AT91_PIN(1,1,28) // EBI: Data 26
|
972 |
|
|
#define AT91_EBI_D27 AT91_PIN(1,1,29) // EBI: Data 27
|
973 |
|
|
#define AT91_EBI_D28 AT91_PIN(1,1,30) // EBI: Data 28
|
974 |
|
|
#define AT91_EBI_D29 AT91_PIN(1,1,31) // EBI: Data 29
|
975 |
|
|
|
976 |
|
|
//PIO Controller B Peripheral A
|
977 |
|
|
#define AT91_PIO_PSR_TIOA0 (1<< 0) // Timer/Counter 0 IO Line A
|
978 |
|
|
#define AT91_PIO_PSR_TIOB0 (1<< 1) // Timer/Counter 0 IO Line B
|
979 |
|
|
#define AT91_PIO_PSR_SCK0 (1<< 2) // USART 0 Serial Clock
|
980 |
|
|
#define AT91_PIO_PSR_NPCS3 (1<< 3) // SPI Chip Select 3
|
981 |
|
|
#define AT91_PIO_PSR_TCLK0 (1<< 4) // Timer/Counter 0 Clock Input
|
982 |
|
|
#define AT91_PIO_PSR_NPCS3X (1<< 5) // SPI Chip Select 3 (again)
|
983 |
|
|
#define AT91_PIO_PSR_PCK0 (1<< 6) // Programmable Clock Output 0
|
984 |
|
|
#define AT91_PIO_PSR_PWM3 (1<< 7) // Pulse Width Modulation #3
|
985 |
|
|
#define AT91_PIO_PSR_ADTRG (1<< 8) // ADC Trigger
|
986 |
|
|
#define AT91_PIO_PSR_NPCS1X (1<< 9) // SPI Chip Select 1
|
987 |
|
|
#define AT91_PIO_PSR_NPCS2 (1<<10) // SPI Chip Select 2
|
988 |
|
|
#define AT91_PIO_PSR_PWM0X (1<<11) // Pulse Width Modulation #0
|
989 |
|
|
#define AT91_PIO_PSR_PWM1X (1<<12) // Pulse Width Modulation #1
|
990 |
|
|
#define AT91_PIO_PSR_PWM2X (1<<13) // Pulse Width Modulation #2
|
991 |
|
|
#define AT91_PIO_PSR_PWM4X (1<<14) // Pulse Width Modulation #4
|
992 |
|
|
#define AT91_PIO_PSR_TIOA1 (1<<15) // Timer/Counter 1 IO Line A
|
993 |
|
|
#define AT91_PIO_PSR_TIOB1 (1<<16) // Timer/Counter 1 IO Line B
|
994 |
|
|
#define AT91_PIO_PSR_PCK1 (1<<17) // Programmable Clock Output 1
|
995 |
|
|
#define AT91_PIO_PSR_PCK2 (1<<18) // Programmable Clock Output 2
|
996 |
|
|
#define AT91_PIO_PSR_FIQ (1<<19) // Fast Interrupt Request
|
997 |
|
|
#define AT91_PIO_PSR_IRQ0 (1<<20) // Interrupt Request 0
|
998 |
|
|
#define AT91_PIO_PSR_PCK1X (1<<21) // Programmable Clock Output 1
|
999 |
|
|
#define AT91_PIO_PSR_NPCS3XX (1<<22) // SPI Chip Select 3 (yet again)
|
1000 |
|
|
#define AT91_PIO_PSR_PWM0XX (1<<23) // Pulse Width Modulation #0
|
1001 |
|
|
#define AT91_PIO_PSR_PWM1XX (1<<24) // Pulse Width Modulation #1
|
1002 |
|
|
#define AT91_PIO_PSR_PWM2XX (1<<25) // Pulse Width Modulation 2
|
1003 |
|
|
#define AT91_PIO_PSR_TIOA2 (1<<26) // Timer/Counter 2 IO Line A
|
1004 |
|
|
#define AT91_PIO_PSR_TIOB2 (1<<27) // Timer/Counter 2 IO Line B
|
1005 |
|
|
#define AT91_PIO_PSR_TCLK1 (1<<28) // External Clock Input 1
|
1006 |
|
|
#define AT91_PIO_PSR_TCLK2 (1<<29) // External Clock Input 2
|
1007 |
|
|
#define AT91_PIO_PSR_NPCS2X (1<<30) // SPI Chip Select 2 (again)
|
1008 |
|
|
#define AT91_PIO_PSR_PCK2X (1<<31) // Programmable Clock Output 2
|
1009 |
|
|
|
1010 |
|
|
//PIO Controller B Peripheral B
|
1011 |
|
|
#define AT91_PIO_PSR_NBS0X (1<< 0) // EBI: Address 0 / SDRAM Byte Mask 0
|
1012 |
|
|
#define AT91_PIO_PSR_NBS2X (1<< 1) // EBI: Address 1 / SDRAM Byte Mask 2
|
1013 |
|
|
#define AT91_PIO_PSR_A2X (1<< 2) // EBI: Address 2
|
1014 |
|
|
#define AT91_PIO_PSR_A3X (1<< 3) // EBI: Address 3
|
1015 |
|
|
#define AT91_PIO_PSR_A4X (1<< 4) // EBI: Address 4
|
1016 |
|
|
#define AT91_PIO_PSR_A5X (1<< 5) // EBI: Address 5
|
1017 |
|
|
#define AT91_PIO_PSR_A6X (1<< 6) // EBI: Address 6
|
1018 |
|
|
#define AT91_PIO_PSR_A7X (1<< 7) // EBI: Address 7
|
1019 |
|
|
#define AT91_PIO_PSR_A8X (1<< 8) // EBI: Address 8
|
1020 |
|
|
#define AT91_PIO_PSR_A9X (1<< 9) // EBI: Address 9
|
1021 |
|
|
#define AT91_PIO_PSR_A10X (1<<10) // EBI: Address 10
|
1022 |
|
|
#define AT91_PIO_PSR_A11X (1<<11) // EBI: Address 11
|
1023 |
|
|
#define AT91_PIO_PSR_A12X (1<<12) // EBI: Address 12
|
1024 |
|
|
#define AT91_PIO_PSR_A13X (1<<13) // EBI: Address 13
|
1025 |
|
|
#define AT91_PIO_PSR_A14X (1<<14) // EBI: Address 14
|
1026 |
|
|
#define AT91_PIO_PSR_A15X (1<<15) // EBI: Address 15
|
1027 |
|
|
#define AT91_PIO_PSR_BA0X (1<<16) // EBI: Address 16 /
|
1028 |
|
|
// SDRAM Bank Select 0
|
1029 |
|
|
#define AT91_PIO_PSR_BA1X (1<<17) // EBI: Address 17 /
|
1030 |
|
|
// SDRAM Bank Select 1
|
1031 |
|
|
#define AT91_PIO_PSR_D16 (1<<18) // EBI: Data 16
|
1032 |
|
|
#define AT91_PIO_PSR_D17 (1<<19) // EBI: Data 17
|
1033 |
|
|
#define AT91_PIO_PSR_D18 (1<<20) // EBI: Data 18
|
1034 |
|
|
#define AT91_PIO_PSR_D19 (1<<21) // EBI: Data 19
|
1035 |
|
|
#define AT91_PIO_PSR_D20 (1<<22) // EBI: Data 20
|
1036 |
|
|
#define AT91_PIO_PSR_D21 (1<<23) // EBI: Data 21
|
1037 |
|
|
#define AT91_PIO_PSR_D22 (1<<24) // EBI: Data 22
|
1038 |
|
|
#define AT91_PIO_PSR_D23 (1<<25) // EBI: Data 23
|
1039 |
|
|
#define AT91_PIO_PSR_D24 (1<<26) // EBI: Data 24
|
1040 |
|
|
#define AT91_PIO_PSR_D25 (1<<27) // EBI: Data 25
|
1041 |
|
|
#define AT91_PIO_PSR_D26 (1<<28) // EBI: Data 26
|
1042 |
|
|
#define AT91_PIO_PSR_D27 (1<<29) // EBI: Data 27
|
1043 |
|
|
#define AT91_PIO_PSR_D28 (1<<30) // EBI: Data 28
|
1044 |
|
|
#define AT91_PIO_PSR_D29 (1<<31) // EBI: Data 29
|
1045 |
|
|
|
1046 |
|
|
//PIO Controller C Peripheral A
|
1047 |
|
|
#define AT91_EBI_D0 AT91_PIN(2,0, 0) // EBI: Data 0
|
1048 |
|
|
#define AT91_EBI_D1 AT91_PIN(2,0, 1) // EBI: Data 1
|
1049 |
|
|
#define AT91_EBI_D2 AT91_PIN(2,0, 2) // EBI: Data 2
|
1050 |
|
|
#define AT91_EBI_D3 AT91_PIN(2,0, 3) // EBI: Data 3
|
1051 |
|
|
#define AT91_EBI_D4 AT91_PIN(2,0, 4) // EBI: Data 4
|
1052 |
|
|
#define AT91_EBI_D5 AT91_PIN(2,0, 5) // EBI: Data 5
|
1053 |
|
|
#define AT91_EBI_D6 AT91_PIN(2,0, 6) // EBI: Data 6
|
1054 |
|
|
#define AT91_EBI_D7 AT91_PIN(2,0, 7) // EBI: Data 7
|
1055 |
|
|
#define AT91_EBI_D8 AT91_PIN(2,0, 8) // EBI: Data 8
|
1056 |
|
|
#define AT91_EBI_D9 AT91_PIN(2,0, 9) // EBI: Data 9
|
1057 |
|
|
#define AT91_EBI_D10 AT91_PIN(2,0,10) // EBI: Data 10
|
1058 |
|
|
#define AT91_EBI_D11 AT91_PIN(2,0,11) // EBI: Data 11
|
1059 |
|
|
#define AT91_EBI_D12 AT91_PIN(2,0,12) // EBI: Data 12
|
1060 |
|
|
#define AT91_EBI_D13 AT91_PIN(2,0,13) // EBI: Data 13
|
1061 |
|
|
#define AT91_EBI_D14 AT91_PIN(2,0,14) // EBI: Data 14
|
1062 |
|
|
#define AT91_EBI_D15 AT91_PIN(2,0,15) // EBI: Data 15
|
1063 |
|
|
#define AT91_EBI_A18 AT91_PIN(2,0,16) // EBI: Address 18
|
1064 |
|
|
#define AT91_EBI_A19 AT91_PIN(2,0,17) // EBI: Address 19
|
1065 |
|
|
#define AT91_EBI_A20 AT91_PIN(2,0,18) // EBI: Address 20
|
1066 |
|
|
#define AT91_EBI_A21_NANDALE \
|
1067 |
|
|
AT91_PIN(2,0,19) // EBI: Address 21 /
|
1068 |
|
|
// NAND Flash Address Line Enable
|
1069 |
|
|
#define AT91_EBI_A22_REG_NANDCLE \
|
1070 |
|
|
AT91_PIN(2,0,20) // EBI: Address 22 /
|
1071 |
|
|
// CompactFlash REG Signal /
|
1072 |
|
|
// NAND Flash Command Line Enable
|
1073 |
|
|
#define AT91_EBI_CFNRW AT91_PIN(2,0,23) // EBI: CF Read Not Write Signal
|
1074 |
|
|
|
1075 |
|
|
//PIO Controller C Peripheral B
|
1076 |
|
|
#define AT91_USART_RTS1X AT91_PIN(2,1, 8) // USART 1 Ready To Send
|
1077 |
|
|
#define AT91_USART_DTR1X AT91_PIN(2,1, 9) // USART 1 Data Terminal Ready
|
1078 |
|
|
#define AT91_PCK_PCK0X AT91_PIN(2,1,10) // Programmable Clock Output 0
|
1079 |
|
|
#define AT91_PCK_PCK1XX AT91_PIN(2,1,11) // Programmable Clock Output 1
|
1080 |
|
|
#define AT91_PCK_PCK2XX AT91_PIN(2,1,12) // Programmable Clock Output 2
|
1081 |
|
|
#define AT91_SPI_NPCS1XX AT91_PIN(2,1,14) // SPI Chip Select 1
|
1082 |
|
|
#define AT91_EBI_NCS3_NANDCS \
|
1083 |
|
|
AT91_PIN(2,1,15) // EBI: Chip Select 3 /
|
1084 |
|
|
// NAND Flash Chip Select
|
1085 |
|
|
#define AT91_EBI_NWAIT AT91_PIN(2,1,16) // EBI: External Wait Signal
|
1086 |
|
|
#define AT91_EBI_NANDOE AT91_PIN(2,1,17) // EBI: NAND Flash Output Enable
|
1087 |
|
|
#define AT91_EBI_NANDWE AT91_PIN(2,1,18) // EBI: NAND Flash Write Enable
|
1088 |
|
|
#define AT91_EBI_NCS7 AT91_PIN(2,1,20) // EBI: Chip Select 7
|
1089 |
|
|
#define AT91_EBI_NWR0_NWE_CFWE \
|
1090 |
|
|
AT91_PIN(2,1,21) // EBI: Write 0 /
|
1091 |
|
|
// SMC Write Enable /
|
1092 |
|
|
// CompactFlash Write Enable
|
1093 |
|
|
#define AT91_EBI_NRD_CFOE AT91_PIN(2,1,22) // EBI: SMC Read Enable /
|
1094 |
|
|
// CompactFlash Output Enable
|
1095 |
|
|
#define AT91_EBI_NCS0 AT91_PIN(2,1,23) // EBI: Chip Select 0
|
1096 |
|
|
|
1097 |
|
|
//PIO Controller C Peripheral A
|
1098 |
|
|
#define AT91_PIO_PSR_D0 (1<< 0) // EBI: Data 0
|
1099 |
|
|
#define AT91_PIO_PSR_D1 (1<< 1) // EBI: Data 1
|
1100 |
|
|
#define AT91_PIO_PSR_D2 (1<< 2) // EBI: Data 2
|
1101 |
|
|
#define AT91_PIO_PSR_D3 (1<< 3) // EBI: Data 3
|
1102 |
|
|
#define AT91_PIO_PSR_D4 (1<< 4) // EBI: Data 4
|
1103 |
|
|
#define AT91_PIO_PSR_D5 (1<< 5) // EBI: Data 5
|
1104 |
|
|
#define AT91_PIO_PSR_D6 (1<< 6) // EBI: Data 6
|
1105 |
|
|
#define AT91_PIO_PSR_D7 (1<< 7) // EBI: Data 7
|
1106 |
|
|
#define AT91_PIO_PSR_D8 (1<< 8) // EBI: Data 8
|
1107 |
|
|
#define AT91_PIO_PSR_D9 (1<< 9) // EBI: Data 9
|
1108 |
|
|
#define AT91_PIO_PSR_D10 (1<<10) // EBI: Data 10
|
1109 |
|
|
#define AT91_PIO_PSR_D11 (1<<11) // EBI: Data 11
|
1110 |
|
|
#define AT91_PIO_PSR_D12 (1<<12) // EBI: Data 12
|
1111 |
|
|
#define AT91_PIO_PSR_D13 (1<<13) // EBI: Data 13
|
1112 |
|
|
#define AT91_PIO_PSR_D14 (1<<14) // EBI: Data 14
|
1113 |
|
|
#define AT91_PIO_PSR_D15 (1<<15) // EBI: Data 15
|
1114 |
|
|
#define AT91_PIO_PSR_A18 (1<<16) // EBI: Address 18
|
1115 |
|
|
#define AT91_PIO_PSR_A19 (1<<17) // EBI: Address 19
|
1116 |
|
|
#define AT91_PIO_PSR_A20 (1<<18) // EBI: Address 20
|
1117 |
|
|
#define AT91_PIO_PSR_NANDALE (1<<19) // EBI: Address 21 /
|
1118 |
|
|
// NAND Flash Address Line Enable
|
1119 |
|
|
#define AT91_PIO_PSR_NANDCLE (1<<20) // EBI: Address 22 /
|
1120 |
|
|
// CompactFlash REG Signal /
|
1121 |
|
|
// NAND Flash Command Line Enable
|
1122 |
|
|
#define AT91_PIO_PSR_CFNRW (1<<23) // EBI: CF Read Not Write Signal
|
1123 |
|
|
|
1124 |
|
|
//PIO Controller C Peripheral B
|
1125 |
|
|
#define AT91_PIO_PSR_RTS1X (1<< 8) // USART 1 Ready To Send
|
1126 |
|
|
#define AT91_PIO_PSR_DTR1X (1<< 9) // USART 1 Data Terminal Ready
|
1127 |
|
|
#define AT91_PIO_PSR_PCK0X (1<<10) // Programmable Clock Output 0
|
1128 |
|
|
#define AT91_PIO_PSR_PCK1XX (1<<11) // Programmable Clock Output 1
|
1129 |
|
|
#define AT91_PIO_PSR_PCK2XX (1<<12) // Programmable Clock Output 2
|
1130 |
|
|
#define AT91_PIO_PSR_NPCS1XX (1<<14) // SPI Chip Select 1
|
1131 |
|
|
#define AT91_PIO_PSR_NANDCS (1<<15) // EBI: Chip Select 3 /
|
1132 |
|
|
// NAND Flash Chip Select
|
1133 |
|
|
#define AT91_PIO_PSR_NWAIT (1<<16) // EBI: External Wait Signal
|
1134 |
|
|
#define AT91_PIO_PSR_NANDOE (1<<17) // EBI: NAND Flash Output Enable
|
1135 |
|
|
#define AT91_PIO_PSR_NANDWE (1<<18) // EBI: NAND Flash Write Enable
|
1136 |
|
|
#define AT91_PIO_PSR_NCS7 (1<<20) // EBI: Chip Select 7
|
1137 |
|
|
#define AT91_PIO_PSR_CFWE (1<<21) // EBI: Write 0 / SMC Write Enable /
|
1138 |
|
|
// CompactFlash Write Enable
|
1139 |
|
|
#define AT91_PIO_PSR_CFOE (1<<22) // EBI: SMC Read Enable /
|
1140 |
|
|
// CompactFlash Output Enable
|
1141 |
|
|
#define AT91_PIO_PSR_NCS0 (1<<23) // EBI: Chip Select 0
|
1142 |
|
|
|
1143 |
|
|
#endif // CYGHWR_HAL_ARM_AT91SAM7SE
|
1144 |
|
|
|
1145 |
|
|
#else
|
1146 |
|
|
#define AT91_TC_TCLK0 AT91_PIN(0,0, 0) // Timer #0 clock
|
1147 |
|
|
#define AT91_TC_TIOA0 AT91_PIN(0,0, 1) // Timer #0 signal A
|
1148 |
|
|
#define AT91_TC_TIOB0 AT91_PIN(0,0, 2) // Timer #0 signal B
|
1149 |
|
|
#define AT91_TC_TCLK1 AT91_PIN(0,0, 3) // Timer #1 clock
|
1150 |
|
|
#define AT91_TC_TIOA1 AT91_PIN(0,0, 4) // Timer #1 signal A
|
1151 |
|
|
#define AT91_TC_TIOB1 AT91_PIN(0,0, 5) // Timer #1 signal B
|
1152 |
|
|
#define AT91_TC_TCLK2 AT91_PIN(0,0, 6) // Timer #2 clock
|
1153 |
|
|
#define AT91_TC_TIOA2 AT91_PIN(0,0, 7) // Timer #2 signal A
|
1154 |
|
|
#define AT91_TC_TIOB2 AT91_PIN(0,0, 8) // Timer #2 signal B
|
1155 |
|
|
#define AT91_INT_IRQ0 AT91_PIN(0,0, 9) // IRQ #0
|
1156 |
|
|
#define AT91_INT_IRQ1 AT91_PIN(0,0,10) // IRQ #1
|
1157 |
|
|
#define AT91_INT_IRQ2 AT91_PIN(0,0,11) // IRQ #2
|
1158 |
|
|
#define AT91_INT_FIQ AT91_PIN(0,0,12) // FIQ
|
1159 |
|
|
#define AT91_USART_SCK0 AT91_PIN(0,0,13) // Serial port #0 clock
|
1160 |
|
|
#define AT91_USART_TXD0 AT91_PIN(0,0,14) // Serial port #0 TxD
|
1161 |
|
|
#define AT91_USART_RXD0 AT91_PIN(0,0,15) // Serial port #0 RxD
|
1162 |
|
|
#define AT91_USART_SCK1 AT91_PIN(0,0,20) // Serial port #1 clock
|
1163 |
|
|
#define AT91_USART_TXD1 AT91_PIN(0,0,21) // Serial port #1 TxD
|
1164 |
|
|
#define AT91_USART_RXD1 AT91_PIN(0,0,22) // Serial port #1 RxD
|
1165 |
|
|
#define AT91_CLK_MCKO AT91_PIN(0,0,25) // Master clock out
|
1166 |
|
|
|
1167 |
|
|
#define AT91_PIO_PSR_TCLK0 0x00000001 // Timer #0 clock
|
1168 |
|
|
#define AT91_PIO_PSR_TIOA0 0x00000002 // Timer #0 signal A
|
1169 |
|
|
#define AT91_PIO_PSR_TIOB0 0x00000004 // Timer #0 signal B
|
1170 |
|
|
#define AT91_PIO_PSR_TCLK1 0x00000008 // Timer #1 clock
|
1171 |
|
|
#define AT91_PIO_PSR_TIOA1 0x00000010 // Timer #1 signal A
|
1172 |
|
|
#define AT91_PIO_PSR_TIOB1 0x00000020 // Timer #1 signal B
|
1173 |
|
|
#define AT91_PIO_PSR_TCLK2 0x00000040 // Timer #2 clock
|
1174 |
|
|
#define AT91_PIO_PSR_TIOA2 0x00000080 // Timer #2 signal A
|
1175 |
|
|
#define AT91_PIO_PSR_TIOB2 0x00000100 // Timer #2 signal B
|
1176 |
|
|
#define AT91_PIO_PSR_IRQ0 0x00000200 // IRQ #0
|
1177 |
|
|
#define AT91_PIO_PSR_IRQ1 0x00000400 // IRQ #1
|
1178 |
|
|
#define AT91_PIO_PSR_IRQ2 0x00000800 // IRQ #2
|
1179 |
|
|
#define AT91_PIO_PSR_FIQ 0x00001000 // FIQ
|
1180 |
|
|
#define AT91_PIO_PSR_SCK0 0x00002000 // Serial port #0 clock
|
1181 |
|
|
#define AT91_PIO_PSR_TXD0 0x00004000 // Serial port #0 TxD
|
1182 |
|
|
#define AT91_PIO_PSR_RXD0 0x00008000 // Serial port #0 RxD
|
1183 |
|
|
#define AT91_PIO_PSR_P16 0x00010000 // PIO port #16
|
1184 |
|
|
#define AT91_PIO_PSR_P17 0x00020000 // PIO port #17
|
1185 |
|
|
#define AT91_PIO_PSR_P18 0x00040000 // PIO port #18
|
1186 |
|
|
#define AT91_PIO_PSR_P19 0x00080000 // PIO port #19
|
1187 |
|
|
#define AT91_PIO_PSR_SCK1 0x00100000 // Serial port #1 clock
|
1188 |
|
|
#define AT91_PIO_PSR_TXD1 0x00200000 // Serial port #1 TxD
|
1189 |
|
|
#define AT91_PIO_PSR_RXD1 0x00400000 // Serial port #1 RxD
|
1190 |
|
|
#define AT91_PIO_PSR_P23 0x00800000 // PIO port #23
|
1191 |
|
|
#define AT91_PIO_PSR_P24 0x01000000 // PIO port #24
|
1192 |
|
|
#define AT91_PIO_PSR_MCKO 0x02000000 // Master clock out
|
1193 |
|
|
#define AT91_PIO_PSR_NCS2 0x04000000 // Chip select #2
|
1194 |
|
|
#define AT91_PIO_PSR_NCS3 0x08000000 // Chip select #3
|
1195 |
|
|
#define AT91_PIO_PSR_CS7_A20 0x10000000 // Chip select #7 or A20
|
1196 |
|
|
#define AT91_PIO_PSR_CS6_A21 0x20000000 // Chip select #6 or A21
|
1197 |
|
|
#define AT91_PIO_PSR_CS5_A22 0x40000000 // Chip select #5 or A22
|
1198 |
|
|
#define AT91_PIO_PSR_CS4_A23 0x80000000 // Chip select #4 or A23
|
1199 |
|
|
#endif
|
1200 |
|
|
|
1201 |
|
|
#define AT91_PIO_OER 0x10 // Output enable
|
1202 |
|
|
#define AT91_PIO_ODR 0x14 // Output disable
|
1203 |
|
|
#define AT91_PIO_OSR 0x18 // Output status
|
1204 |
|
|
#define AT91_PIO_IFER 0x20 // Input Filter enable
|
1205 |
|
|
#define AT91_PIO_IFDR 0x24 // Input Filter disable
|
1206 |
|
|
#define AT91_PIO_IFSR 0x28 // Input Filter status
|
1207 |
|
|
#define AT91_PIO_SODR 0x30 // Set out bits
|
1208 |
|
|
#define AT91_PIO_CODR 0x34 // Clear out bits
|
1209 |
|
|
#define AT91_PIO_ODSR 0x38 // Output data status
|
1210 |
|
|
#define AT91_PIO_PDSR 0x3C // Pin data status
|
1211 |
|
|
#define AT91_PIO_IER 0x40 // Interrupt enable
|
1212 |
|
|
#define AT91_PIO_IDR 0x44 // Interrupt disable
|
1213 |
|
|
#define AT91_PIO_IMR 0x48 // Interrupt mask
|
1214 |
|
|
#define AT91_PIO_ISR 0x4C // Interrupt status
|
1215 |
|
|
|
1216 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
1217 |
|
|
#define AT91_PIO_MDER 0x50 // Multi-drive Enable Register
|
1218 |
|
|
#define AT91_PIO_MDDR 0x54 // Multi-drive Disable Register
|
1219 |
|
|
#define AT91_PIO_MDSR 0x58 // Multi-drive Status Register
|
1220 |
|
|
#define AT91_PIO_PPUDR 0x60 // Pad Pull-up Disable Register
|
1221 |
|
|
#define AT91_PIO_PPUER 0x64 // Pad Pull-up Enable Register
|
1222 |
|
|
#define AT91_PIO_PPUSR 0x68 // Pad Pull-Up Status Register
|
1223 |
|
|
#define AT91_PIO_ASR 0x70 // Select A Register
|
1224 |
|
|
#define AT91_PIO_BSR 0x74 // Select B Regsiter
|
1225 |
|
|
#define AT91_PIO_ABS 0x78 // AB Select Regsiter
|
1226 |
|
|
#define AT91_PIO_OWER 0xa0 // Output Write Enable Register
|
1227 |
|
|
#define AT91_PIO_OWDR 0xa4 // Output Write Disable Register
|
1228 |
|
|
#define AT91_PIO_OWSR 0xa8 // Output Write Status Register
|
1229 |
|
|
#endif // CYGHWR_HAL_ARM_AT91SAM7
|
1230 |
|
|
|
1231 |
|
|
//=============================================================================
|
1232 |
|
|
// Advanced Interrupt Controller (AIC)
|
1233 |
|
|
|
1234 |
|
|
#ifndef AT91_AIC
|
1235 |
|
|
#define AT91_AIC 0xFFFFF000
|
1236 |
|
|
#endif
|
1237 |
|
|
|
1238 |
|
|
#define AT91_AIC_SMR0 ((0*4)+0x000)
|
1239 |
|
|
#define AT91_AIC_SMR1 ((1*4)+0x000)
|
1240 |
|
|
#define AT91_AIC_SMR2 ((2*4)+0x000)
|
1241 |
|
|
#define AT91_AIC_SMR3 ((3*4)+0x000)
|
1242 |
|
|
#define AT91_AIC_SMR4 ((4*4)+0x000)
|
1243 |
|
|
#define AT91_AIC_SMR5 ((5*4)+0x000)
|
1244 |
|
|
#define AT91_AIC_SMR6 ((6*4)+0x000)
|
1245 |
|
|
#define AT91_AIC_SMR7 ((7*4)+0x000)
|
1246 |
|
|
#define AT91_AIC_SMR8 ((8*4)+0x000)
|
1247 |
|
|
#define AT91_AIC_SMR9 ((9*4)+0x000)
|
1248 |
|
|
#define AT91_AIC_SMR10 ((10*4)+0x000)
|
1249 |
|
|
#define AT91_AIC_SMR11 ((11*4)+0x000)
|
1250 |
|
|
#define AT91_AIC_SMR12 ((12*4)+0x000)
|
1251 |
|
|
#define AT91_AIC_SMR13 ((13*4)+0x000)
|
1252 |
|
|
#define AT91_AIC_SMR14 ((14*4)+0x000)
|
1253 |
|
|
#define AT91_AIC_SMR15 ((15*4)+0x000)
|
1254 |
|
|
#define AT91_AIC_SMR16 ((16*4)+0x000)
|
1255 |
|
|
#define AT91_AIC_SMR17 ((17*4)+0x000)
|
1256 |
|
|
#define AT91_AIC_SMR18 ((18*4)+0x000)
|
1257 |
|
|
#define AT91_AIC_SMR19 ((19*4)+0x000)
|
1258 |
|
|
#define AT91_AIC_SMR20 ((20*4)+0x000)
|
1259 |
|
|
#define AT91_AIC_SMR21 ((21*4)+0x000)
|
1260 |
|
|
#define AT91_AIC_SMR22 ((22*4)+0x000)
|
1261 |
|
|
#define AT91_AIC_SMR23 ((23*4)+0x000)
|
1262 |
|
|
#define AT91_AIC_SMR24 ((24*4)+0x000)
|
1263 |
|
|
#define AT91_AIC_SMR25 ((25*4)+0x000)
|
1264 |
|
|
#define AT91_AIC_SMR26 ((26*4)+0x000)
|
1265 |
|
|
#define AT91_AIC_SMR27 ((27*4)+0x000)
|
1266 |
|
|
#define AT91_AIC_SMR28 ((28*4)+0x000)
|
1267 |
|
|
#define AT91_AIC_SMR29 ((29*4)+0x000)
|
1268 |
|
|
#define AT91_AIC_SMR30 ((30*4)+0x000)
|
1269 |
|
|
#define AT91_AIC_SMR31 ((31*4)+0x000)
|
1270 |
|
|
#define AT91_AIC_SMR_LEVEL_LOW (0<<5)
|
1271 |
|
|
#define AT91_AIC_SMR_LEVEL_HI (2<<5)
|
1272 |
|
|
#define AT91_AIC_SMR_EDGE_NEG (1<<5)
|
1273 |
|
|
#define AT91_AIC_SMR_EDGE_POS (3<<5)
|
1274 |
|
|
#define AT91_AIC_SMR_PRIORITY 0x07
|
1275 |
|
|
#define AT91_AIC_SVR0 ((0*4)+0x080)
|
1276 |
|
|
#define AT91_AIC_SVR1 ((1*4)+0x080)
|
1277 |
|
|
#define AT91_AIC_SVR2 ((2*4)+0x080)
|
1278 |
|
|
#define AT91_AIC_SVR3 ((3*4)+0x080)
|
1279 |
|
|
#define AT91_AIC_SVR4 ((4*4)+0x080)
|
1280 |
|
|
#define AT91_AIC_SVR5 ((5*4)+0x080)
|
1281 |
|
|
#define AT91_AIC_SVR6 ((6*4)+0x080)
|
1282 |
|
|
#define AT91_AIC_SVR7 ((7*4)+0x080)
|
1283 |
|
|
#define AT91_AIC_SVR8 ((8*4)+0x080)
|
1284 |
|
|
#define AT91_AIC_SVR9 ((9*4)+0x080)
|
1285 |
|
|
#define AT91_AIC_SVR10 ((10*4)+0x080)
|
1286 |
|
|
#define AT91_AIC_SVR11 ((11*4)+0x080)
|
1287 |
|
|
#define AT91_AIC_SVR12 ((12*4)+0x080)
|
1288 |
|
|
#define AT91_AIC_SVR13 ((13*4)+0x080)
|
1289 |
|
|
#define AT91_AIC_SVR14 ((14*4)+0x080)
|
1290 |
|
|
#define AT91_AIC_SVR15 ((15*4)+0x080)
|
1291 |
|
|
#define AT91_AIC_SVR16 ((16*4)+0x080)
|
1292 |
|
|
#define AT91_AIC_SVR17 ((17*4)+0x080)
|
1293 |
|
|
#define AT91_AIC_SVR18 ((18*4)+0x080)
|
1294 |
|
|
#define AT91_AIC_SVR19 ((19*4)+0x080)
|
1295 |
|
|
#define AT91_AIC_SVR20 ((20*4)+0x080)
|
1296 |
|
|
#define AT91_AIC_SVR21 ((21*4)+0x080)
|
1297 |
|
|
#define AT91_AIC_SVR22 ((22*4)+0x080)
|
1298 |
|
|
#define AT91_AIC_SVR23 ((23*4)+0x080)
|
1299 |
|
|
#define AT91_AIC_SVR24 ((24*4)+0x080)
|
1300 |
|
|
#define AT91_AIC_SVR25 ((25*4)+0x080)
|
1301 |
|
|
#define AT91_AIC_SVR26 ((26*4)+0x080)
|
1302 |
|
|
#define AT91_AIC_SVR27 ((27*4)+0x080)
|
1303 |
|
|
#define AT91_AIC_SVR28 ((28*4)+0x080)
|
1304 |
|
|
#define AT91_AIC_SVR29 ((29*4)+0x080)
|
1305 |
|
|
#define AT91_AIC_SVR30 ((30*4)+0x080)
|
1306 |
|
|
#define AT91_AIC_SVR31 ((31*4)+0x080)
|
1307 |
|
|
#define AT91_AIC_IVR 0x100
|
1308 |
|
|
#define AT91_AIC_FVR 0x104
|
1309 |
|
|
#define AT91_AIC_ISR 0x108
|
1310 |
|
|
#define AT91_AIC_IPR 0x10C
|
1311 |
|
|
#define AT91_AIC_IMR 0x110
|
1312 |
|
|
#define AT91_AIC_CISR 0x114
|
1313 |
|
|
#define AT91_AIC_IECR 0x120
|
1314 |
|
|
#define AT91_AIC_IDCR 0x124
|
1315 |
|
|
#define AT91_AIC_ICCR 0x128
|
1316 |
|
|
#define AT91_AIC_ISCR 0x12C
|
1317 |
|
|
#define AT91_AIC_EOI 0x130
|
1318 |
|
|
#define AT91_AIC_SVR 0x134
|
1319 |
|
|
|
1320 |
|
|
#ifdef CYGHWR_HAL_ARM_AT91SAM7
|
1321 |
|
|
#define AT91_AIC_DCR 0x138 // Debug Control Register
|
1322 |
|
|
#define AT91_AIC_FFER 0x140 // Fast Forcing Enable Register
|
1323 |
|
|
#define AT91_AIC_FFDR 0x144 // Fast Forcing Disable Register
|
1324 |
|
|
#define AT91_AIC_FFSR 0x148 // Fast Forcing Status Register
|
1325 |
|
|
#endif // CYGHWR_HAL_ARM_AT91SAM7
|
1326 |
|
|
|
1327 |
|
|
//=============================================================================
|
1328 |
|
|
// Timer / counter
|
1329 |
|
|
|
1330 |
|
|
#ifndef AT91_TC
|
1331 |
|
|
#define AT91_TC 0xFFFE0000
|
1332 |
|
|
#endif
|
1333 |
|
|
|
1334 |
|
|
#define AT91_TC_TC0 0x00
|
1335 |
|
|
#define AT91_TC_TC1 0x40
|
1336 |
|
|
#define AT91_TC_TC2 0x80
|
1337 |
|
|
#define AT91_TC_TC_SIZE 0x40
|
1338 |
|
|
|
1339 |
|
|
#define AT91_TC_CCR 0x00
|
1340 |
|
|
#define AT91_TC_CCR_CLKEN 0x01
|
1341 |
|
|
#define AT91_TC_CCR_CLKDIS 0x02
|
1342 |
|
|
#define AT91_TC_CCR_TRIG 0x04
|
1343 |
|
|
// Channel Mode Register
|
1344 |
|
|
#define AT91_TC_CMR 0x04
|
1345 |
|
|
#define AT91_TC_CMR_CLKS 0
|
1346 |
|
|
#define AT91_TC_CMR_CLKS_MCK2 (0<<0)
|
1347 |
|
|
#define AT91_TC_CMR_CLKS_MCK8 (1<<0)
|
1348 |
|
|
#define AT91_TC_CMR_CLKS_MCK32 (2<<0)
|
1349 |
|
|
#define AT91_TC_CMR_CLKS_MCK128 (3<<0)
|
1350 |
|
|
#define AT91_TC_CMR_CLKS_MCK1024 (4<<0)
|
1351 |
|
|
#define AT91_TC_CMR_CLKS_XC0 (5<<0)
|
1352 |
|
|
#define AT91_TC_CMR_CLKS_XC1 (6<<0)
|
1353 |
|
|
#define AT91_TC_CMR_CLKS_XC2 (7<<0)
|
1354 |
|
|
#define AT91_TC_CMR_CLKI (1<<3)
|
1355 |
|
|
#define AT91_TC_CMR_BURST_NONE (0<<4)
|
1356 |
|
|
#define AT91_TC_CMR_BURST_XC0 (1<<4)
|
1357 |
|
|
#define AT91_TC_CMR_BURST_XC1 (2<<4)
|
1358 |
|
|
#define AT91_TC_CMR_BURST_XC2 (3<<4)
|
1359 |
|
|
// Capture mode definitions
|
1360 |
|
|
#define AT91_TC_CMR_LDBSTOP (1<<6)
|
1361 |
|
|
#define AT91_TC_CMR_LDBDIS (1<<7)
|
1362 |
|
|
#define AT91_TC_CMR_TRIG_NONE (0<<8)
|
1363 |
|
|
#define AT91_TC_CMR_TRIG_NEG (1<<8)
|
1364 |
|
|
#define AT91_TC_CMR_TRIG_POS (2<<8)
|
1365 |
|
|
#define AT91_TC_CMR_TRIG_BOTH (3<<8)
|
1366 |
|
|
#define AT91_TC_CMR_EXT_TRIG_TIOB (0<<10)
|
1367 |
|
|
#define AT91_TC_CMR_EXT_TRIG_TIOA (1<<10)
|
1368 |
|
|
#define AT91_TC_CMR_CPCTRG (1<<14)
|
1369 |
|
|
#define AT91_TC_CMR_LDRA_NONE (0<<16)
|
1370 |
|
|
#define AT91_TC_CMR_LDRA_TIOA_NEG (1<<16)
|
1371 |
|
|
#define AT91_TC_CMR_LDRA_TIOA_POS (2<<16)
|
1372 |
|
|
#define AT91_TC_CMR_LDRA_TIOA_BOTH (3<<16)
|
1373 |
|
|
#define AT91_TC_CMR_LDRB_NONE (0<<18)
|
1374 |
|
|
#define AT91_TC_CMR_LDRB_TIOA_NEG (1<<18)
|
1375 |
|
|
#define AT91_TC_CMR_LDRB_TIOA_POS (2<<18)
|
1376 |
|
|
#define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<18)
|
1377 |
|
|
// Waveform mode definitions
|
1378 |
|
|
#define AT91_TC_CMR_CPCSTOP (1<<6)
|
1379 |
|
|
#define AT91_TC_CMR_CPCDIS (1<<7)
|
1380 |
|
|
#define AT91_TC_CMR_EEVTEDG_NONE (0<<8)
|
1381 |
|
|
#define AT91_TC_CMR_EEVTEDG_NEG (1<<8)
|
1382 |
|
|
#define AT91_TC_CMR_EEVTEDG_POS (2<<8)
|
1383 |
|
|
#define AT91_TC_CMR_EEVTEDG_BOTH (3<<8)
|
1384 |
|
|
#define AT91_TC_CMR_EEVT_TIOB (0<<10)
|
1385 |
|
|
#define AT91_TC_CMR_EEVT_XC0 (1<<10)
|
1386 |
|
|
#define AT91_TC_CMR_EEVT_XC1 (2<<10)
|
1387 |
|
|
#define AT91_TC_CMR_EEVT_XC2 (3<<10)
|
1388 |
|
|
#define AT91_TC_CMR_ENETRG (1<<12)
|
1389 |
|
|
#define AT91_TC_CMR_CPCTRG (1<<14)
|
1390 |
|
|
#define AT91_TC_CMR_WAVE (1<<15)
|
1391 |
|
|
#define AT91_TC_CMR_ACPA_NONE (0<<16)
|
1392 |
|
|
#define AT91_TC_CMR_ACPA_SET (1<<16)
|
1393 |
|
|
#define AT91_TC_CMR_ACPA_CLEAR (2<<16)
|
1394 |
|
|
#define AT91_TC_CMR_ACPA_TOGGLE (3<<16)
|
1395 |
|
|
#define AT91_TC_CMR_ACPC_NONE (0<<18)
|
1396 |
|
|
#define AT91_TC_CMR_ACPC_SET (1<<18)
|
1397 |
|
|
#define AT91_TC_CMR_ACPC_CLEAR (2<<18)
|
1398 |
|
|
#define AT91_TC_CMR_ACPC_TOGGLE (3<<18)
|
1399 |
|
|
#define AT91_TC_CMR_AEEVT_NONE (0<<20)
|
1400 |
|
|
#define AT91_TC_CMR_AEEVT_SET (1<<20)
|
1401 |
|
|
#define AT91_TC_CMR_AEEVT_CLEAR (2<<20)
|
1402 |
|
|
#define AT91_TC_CMR_AEEVT_TOGGLE (3<<20)
|
1403 |
|
|
#define AT91_TC_CMR_ASWTRG_NONE (0<<22)
|
1404 |
|
|
#define AT91_TC_CMR_ASWTRG_SET (1<<22)
|
1405 |
|
|
#define AT91_TC_CMR_ASWTRG_CLEAR (2<<22)
|
1406 |
|
|
#define AT91_TC_CMR_ASWTRG_TOGGLE (3<<22)
|
1407 |
|
|
#define AT91_TC_CMR_BCPB_NONE (0<<24)
|
1408 |
|
|
#define AT91_TC_CMR_BCPB_SET (1<<24)
|
1409 |
|
|
#define AT91_TC_CMR_BCPB_CLEAR (2<<24)
|
1410 |
|
|
#define AT91_TC_CMR_BCPB_TOGGLE (3<<24)
|
1411 |
|
|
#define AT91_TC_CMR_BCPC_NONE (0<<26)
|
1412 |
|
|
#define AT91_TC_CMR_BCPC_SET (1<<26)
|
1413 |
|
|
#define AT91_TC_CMR_BCPC_CLEAR (2<<26)
|
1414 |
|
|
#define AT91_TC_CMR_BCPC_TOGGLE (3<<26)
|
1415 |
|
|
#define AT91_TC_CMR_BEEVT_NONE (0<<28)
|
1416 |
|
|
#define AT91_TC_CMR_BEEVT_SET (1<<28)
|
1417 |
|
|
#define AT91_TC_CMR_BEEVT_CLEAR (2<<28)
|
1418 |
|
|
#define AT91_TC_CMR_BEEVT_TOGGLE (3<<28)
|
1419 |
|
|
#define AT91_TC_CMR_BSWTRG_NONE (0<<30)
|
1420 |
|
|
#define AT91_TC_CMR_BSWTRG_SET (1<<30)
|
1421 |
|
|
#define AT91_TC_CMR_BSWTRG_CLEAR (2<<30)
|
1422 |
|
|
#define AT91_TC_CMR_BSWTRG_TOGGLE (3<<30)
|
1423 |
|
|
|
1424 |
|
|
#define AT91_TC_CV 0x10
|
1425 |
|
|
#define AT91_TC_RA 0x14
|
1426 |
|
|
#define AT91_TC_RB 0x18
|
1427 |
|
|
#define AT91_TC_RC 0x1C
|
1428 |
|
|
#define AT91_TC_SR 0x20
|
1429 |
|
|
#define AT91_TC_SR_COVF (1<<0) // Counter overrun
|
1430 |
|
|
#define AT91_TC_SR_LOVR (1<<1) // Load overrun
|
1431 |
|
|
#define AT91_TC_SR_CPA (1<<2) // RA compare
|
1432 |
|
|
#define AT91_TC_SR_CPB (1<<3) // RB compare
|
1433 |
|
|
#define AT91_TC_SR_CPC (1<<4) // RC compare
|
1434 |
|
|
#define AT91_TC_SR_LDRA (1<<5) // Load A status
|
1435 |
|
|
#define AT91_TC_SR_LDRB (1<<6) // Load B status
|
1436 |
|
|
#define AT91_TC_SR_EXT (1<<7) // External trigger
|
1437 |
|
|
#define AT91_TC_SR_CLKSTA (1<<16) // Clock enable/disable status
|
1438 |
|
|
#define AT91_TC_SR_MTIOA (1<<17) // TIOA mirror
|
1439 |
|
|
#define AT91_TC_SR_MTIOB (1<<18) // TIOB mirror
|
1440 |
|
|
#define AT91_TC_IER 0x24
|
1441 |
|
|
#define AT91_TC_IER_COVF (1<<0) // Counter overrun
|
1442 |
|
|
#define AT91_TC_IER_LOVR (1<<1) // Load overrun
|
1443 |
|
|
#define AT91_TC_IER_CPA (1<<2) // RA compare
|
1444 |
|
|
#define AT91_TC_IER_CPB (1<<3) // RB compare
|
1445 |
|
|
#define AT91_TC_IER_CPC (1<<4) // RC compare
|
1446 |
|
|
#define AT91_TC_IER_LDRA (1<<5) // Load A status
|
1447 |
|
|
#define AT91_TC_IER_LDRB (1<<6) // Load B status
|
1448 |
|
|
#define AT91_TC_IER_EXT (1<<7) // External trigger
|
1449 |
|
|
#define AT91_TC_IDR 0x28
|
1450 |
|
|
#define AT91_TC_IMR 0x2C
|
1451 |
|
|
#define AT91_TC_TC1 0x40
|
1452 |
|
|
#define AT91_TC_TC2 0x80
|
1453 |
|
|
#define AT91_TC_BCR 0xC0
|
1454 |
|
|
#define AT91_TC_BCR_SYNC 0x01
|
1455 |
|
|
#define AT91_TC_BMR 0xC4
|
1456 |
|
|
#define AT91_TC_BMR_MASK (0x3f)
|
1457 |
|
|
#define AT91_TC_BMR_TC0XC0S_TCLK0 (0 << 0) // XC0S = TCLK0
|
1458 |
|
|
#define AT91_TC_BMR_TC0XC0S_NONE (1 << 0) // XC0S = none
|
1459 |
|
|
#define AT91_TC_BMR_TC0XC0S_TIOA1 (2 << 0) // XC0S = TIOA1
|
1460 |
|
|
#define AT91_TC_BMR_TC0XC0S_TIOA2 (3 << 0) // XC0S = TIOA2
|
1461 |
|
|
#define AT91_TC_BMR_TC1XC1S_TCLK1 (0 << 2) // XC1S = TCLK1
|
1462 |
|
|
#define AT91_TC_BMR_TC1XC1S_NONE (1 << 2) // XC1S = none
|
1463 |
|
|
#define AT91_TC_BMR_TC1XC1S_TIOA0 (2 << 2) // XC1S = TIOA0
|
1464 |
|
|
#define AT91_TC_BMR_TC1XC1S_TIOA2 (3 << 2) // XC1S = TIOA2
|
1465 |
|
|
#define AT91_TC_BMR_TC2XC2S_TCLK2 (0 << 4) // XC2S = TCLK2
|
1466 |
|
|
#define AT91_TC_BMR_TC2XC2S_NONE (1 << 4) // XC2S = none
|
1467 |
|
|
#define AT91_TC_BMR_TC2XC2S_TIOA0 (2 << 4) // XC2S = TIOA0
|
1468 |
|
|
#define AT91_TC_BMR_TC2XC2S_TIOA1 (3 << 4) // XC2S = TIOA1
|
1469 |
|
|
|
1470 |
|
|
|
1471 |
|
|
|
1472 |
|
|
//=============================================================================
|
1473 |
|
|
// External Bus Interface
|
1474 |
|
|
|
1475 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91_R40807) || \
|
1476 |
|
|
defined(CYGHWR_HAL_ARM_AT91_R40008) || \
|
1477 |
|
|
defined(CYGHWR_HAL_ARM_AT91_M42800A) || \
|
1478 |
|
|
defined(CYGHWR_HAL_ARM_AT91_M55800A)
|
1479 |
|
|
|
1480 |
|
|
|
1481 |
|
|
#ifndef AT91_EBI
|
1482 |
|
|
#define AT91_EBI 0xFFE00000
|
1483 |
|
|
#endif
|
1484 |
|
|
|
1485 |
|
|
#define AT91_EBI_CSR0 0x00
|
1486 |
|
|
#define AT91_EBI_CSR1 0x04
|
1487 |
|
|
#define AT91_EBI_CSR2 0x08
|
1488 |
|
|
#define AT91_EBI_CSR3 0x0C
|
1489 |
|
|
#define AT91_EBI_CSR4 0x10
|
1490 |
|
|
#define AT91_EBI_CSR5 0x14
|
1491 |
|
|
#define AT91_EBI_CSR6 0x18
|
1492 |
|
|
#define AT91_EBI_CSR7 0x1C // Chip select
|
1493 |
|
|
#define AT91_EBI_CSR_DBW_16 0x1 // Data bus 16 bits wide
|
1494 |
|
|
#define AT91_EBI_CSR_DBW_8 0x2 // Data bus 8 bits wide
|
1495 |
|
|
#define AT91_EBI_CSR_NWS_1 (0x0 << 2)
|
1496 |
|
|
#define AT91_EBI_CSR_NWS_2 (0x1 << 2)
|
1497 |
|
|
#define AT91_EBI_CSR_NWS_3 (0x2 << 2)
|
1498 |
|
|
#define AT91_EBI_CSR_NWS_4 (0x3 << 2)
|
1499 |
|
|
#define AT91_EBI_CSR_NWS_5 (0x4 << 2)
|
1500 |
|
|
#define AT91_EBI_CSR_NWS_6 (0x5 << 2)
|
1501 |
|
|
#define AT91_EBI_CSR_NWS_7 (0x6 << 2)
|
1502 |
|
|
#define AT91_EBI_CSR_NWS_8 (0x7 << 2) // Number of wait states
|
1503 |
|
|
#define AT91_EBI_CSR_WSE (0x1 << 5) // Wait state enable
|
1504 |
|
|
#define AT91_EBI_CSR_PAGES_1M (0x0 << 7)
|
1505 |
|
|
#define AT91_EBI_CSR_PAGES_4M (0x1 << 7)
|
1506 |
|
|
#define AT91_EBI_CSR_PAGES_16M (0x2 << 7)
|
1507 |
|
|
#define AT91_EBI_CSR_PAGES_64M (0x3 << 7) // Page size
|
1508 |
|
|
#define AT91_EBI_CSR_TDF_0 (0x0 << 9)
|
1509 |
|
|
#define AT91_EBI_CSR_TDF_1 (0x1 << 9)
|
1510 |
|
|
#define AT91_EBI_CSR_TDF_2 (0x2 << 9)
|
1511 |
|
|
#define AT91_EBI_CSR_TDF_3 (0x3 << 9)
|
1512 |
|
|
#define AT91_EBI_CSR_TDF_4 (0x4 << 9)
|
1513 |
|
|
#define AT91_EBI_CSR_TDF_5 (0x5 << 9)
|
1514 |
|
|
#define AT91_EBI_CSR_TDF_6 (0x6 << 9)
|
1515 |
|
|
#define AT91_EBI_CSR_TDF_7 (0x7 << 9) // Data float output time
|
1516 |
|
|
#define AT91_EBI_CSR_BAT (0x1 << 12) // Byte access type
|
1517 |
|
|
#define AT91_EBI_CSR_CSEN (0x1 << 13) // Chip select enable
|
1518 |
|
|
#define AT91_EBI_CSR_BA (0xFFF << 20) // Base address
|
1519 |
|
|
#define AT91_EBI_RCR 0x20 // Reset control
|
1520 |
|
|
#define AT91_EBI_RCR_RCB 0x1 // Remap command bit
|
1521 |
|
|
#define AT91_EBI_MCR 0x24 // Memory control
|
1522 |
|
|
#define AT91_EBI_MCR_ALE_16M 0x0
|
1523 |
|
|
#define AT91_EBI_MCR_ALE_8M 0x4
|
1524 |
|
|
#define AT91_EBI_MCR_ALE_4M 0x5
|
1525 |
|
|
#define AT91_EBI_MCR_ALE_2M 0x6
|
1526 |
|
|
#define AT91_EBI_MCR_ALE_1M 0x7 // Address line enable
|
1527 |
|
|
#define AT91_EBI_MCR_DRP (0x1 << 4) // Data read protocol
|
1528 |
|
|
|
1529 |
|
|
#elif defined(CYGHWR_HAL_ARM_AT91SAM7SE)
|
1530 |
|
|
|
1531 |
|
|
#ifndef AT91_EBI
|
1532 |
|
|
#define AT91_EBI 0xFFFFFF80
|
1533 |
|
|
#endif
|
1534 |
|
|
|
1535 |
|
|
#define AT91_EBI_CSA 0x00
|
1536 |
|
|
#define AT91_EBI_CSA_CS1A (1 << 1) // Assign NCS1 to SDRAM instead of
|
1537 |
|
|
// static memory
|
1538 |
|
|
#define AT91_EBI_CSA_CS2A (1 << 2) // Assign NCS2 (as second slot CS),
|
1539 |
|
|
// NCS5, NCS6 to CompactFlash (access of
|
1540 |
|
|
// NCS5, NCS6 areas are undefined)
|
1541 |
|
|
// instead of static memory
|
1542 |
|
|
#define AT91_EBI_CSA_CS3A (1 << 3) // Assign NCS3 to NAND Flash instead of
|
1543 |
|
|
// static memory
|
1544 |
|
|
#define AT91_EBI_CSA_CS4A (1 << 4) // Assign NCS4 (as second slot CS), NCS5,
|
1545 |
|
|
// NCS6 to CompactFlash (access of NCS5,
|
1546 |
|
|
// NCS6 areas are undefined) instead of
|
1547 |
|
|
// static memory
|
1548 |
|
|
#define AT91_EBI_CSA_NWPC (1 << 16) // Enable SMC NWAIT pin
|
1549 |
|
|
|
1550 |
|
|
#define AT91_EBI_SMC 0x90 // SMC Configuration Registers
|
1551 |
|
|
#define AT91_EBI_SMC_CSR(n) (AT91_EBI_SMC+0x4*(n)) // Chip select registers
|
1552 |
|
|
#define AT91_EBI_SMC_CSR_NWS_MASK (0x7F << 0) // Number of Wait States mask
|
1553 |
|
|
#define AT91_EBI_SMC_CSR_NWS(n) \
|
1554 |
|
|
( ((n)<< 0) & AT91_EBI_SMC_CSR_NWS_MASK ) // Number of Wait States
|
1555 |
|
|
// (depends on read protocol)
|
1556 |
|
|
#define AT91_EBI_SMC_CSR_WSEN (1 << 7) // Wait State Enable
|
1557 |
|
|
#define AT91_EBI_SMC_CSR_TDF_MASK (0x0F << 8) // Data Float Time mask
|
1558 |
|
|
#define AT91_EBI_SMC_CSR_TDF(n) \
|
1559 |
|
|
( ((n)<< 8) & AT91_EBI_SMC_CSR_TDF_MASK ) // Data Float Time (between
|
1560 |
|
|
// different chip selects)
|
1561 |
|
|
#define AT91_EBI_SMC_CSR_BAT_2x8 (0 << 7) // Byte Access Type
|
1562 |
|
|
// (two 8-bit wide devices)
|
1563 |
|
|
#define AT91_EBI_SMC_CSR_BAT_1x16 (1 << 7) // Byte Access Type
|
1564 |
|
|
// (one 16-bit wide device)
|
1565 |
|
|
#define AT91_EBI_SMC_CSR_DBW_MASK (0x03 << 13) // Data Bus Width mask
|
1566 |
|
|
#define AT91_EBI_SMC_CSR_DBW_16 (0x01 << 13) // Data Bus Width: 16 bit
|
1567 |
|
|
#define AT91_EBI_SMC_CSR_DBW_8 (0x02 << 13) // Data Bus Width: 8 bit
|
1568 |
|
|
#define AT91_EBI_SMC_CSR_DRP_STD (0x00 << 15) // Data Read Protocol: standard
|
1569 |
|
|
#define AT91_EBI_SMC_CSR_DRP_EARLY (0x01 << 15) // Data Read Protocol: early
|
1570 |
|
|
#define AT91_EBI_SMC_CSR_ACSS_MASK (0x03 << 16) // Address to Chip Select
|
1571 |
|
|
// Setup mask
|
1572 |
|
|
#define AT91_EBI_SMC_CSR_ACSS(n) \
|
1573 |
|
|
( ((n)<< 16) & AT91_EBI_SMC_CSR_ACSS_MASK ) // Address to Chip Select
|
1574 |
|
|
// Setup: hold address before
|
1575 |
|
|
// and after CS for n cycles
|
1576 |
|
|
#define AT91_EBI_SMC_CSR_RWSETUP_MASK \
|
1577 |
|
|
(0x07 << 24) // Read and Write Signal
|
1578 |
|
|
// Setup Time
|
1579 |
|
|
#define AT91_EBI_SMC_CSR_RWSETUP(n) \
|
1580 |
|
|
( ((n)<< 24) & AT91_EBI_SMC_CSR_RWSETUP_MASK )// Read and Write Signal
|
1581 |
|
|
// Setup Time is (n+0.5)
|
1582 |
|
|
// (there are exceptions)
|
1583 |
|
|
#define AT91_EBI_SMC_CSR_RWHOLD_MASK \
|
1584 |
|
|
(0x07 << 28) // Read and Write Signal
|
1585 |
|
|
// Hold Time
|
1586 |
|
|
#define AT91_EBI_SMC_CSR_RWHOLD(n) \
|
1587 |
|
|
( ((n)<< 28) & AT91_EBI_SMC_CSR_RWHOLD_MASK ) // Read and Write Signal Hold
|
1588 |
|
|
// Time is n (there are
|
1589 |
|
|
// exceptions)
|
1590 |
|
|
|
1591 |
|
|
#define AT91_MC_SDRAMC 0xB0 // SDRAMC Configuration Registers
|
1592 |
|
|
#define AT91_MC_ECC 0xDC // ECC Configuration Registers
|
1593 |
|
|
#endif
|
1594 |
|
|
|
1595 |
|
|
|
1596 |
|
|
//=============================================================================
|
1597 |
|
|
// Power Saving or Management
|
1598 |
|
|
|
1599 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91_R40807) || \
|
1600 |
|
|
defined(CYGHWR_HAL_ARM_AT91_R40008)
|
1601 |
|
|
|
1602 |
|
|
// Power Saving
|
1603 |
|
|
|
1604 |
|
|
#ifndef AT91_PS
|
1605 |
|
|
#define AT91_PS 0xFFFF4000
|
1606 |
|
|
#endif
|
1607 |
|
|
|
1608 |
|
|
#define AT91_PS_CR 0x000 // Control
|
1609 |
|
|
#define AT91_PS_CR_CPU (1<<0) // Disable CPU clock (idle mode)
|
1610 |
|
|
#define AT91_PS_PCER 0x004 // Peripheral clock enable
|
1611 |
|
|
#define AT91_PS_PCDR 0x008 // Peripheral clock disable
|
1612 |
|
|
#define AT91_PS_PCSR 0x00c // Peripheral clock status
|
1613 |
|
|
|
1614 |
|
|
#elif defined(CYGHWR_HAL_ARM_AT91_M42800A) || \
|
1615 |
|
|
defined(CYGHWR_HAL_ARM_AT91_M55800A) || \
|
1616 |
|
|
defined(CYGHWR_HAL_ARM_AT91SAM7)
|
1617 |
|
|
|
1618 |
|
|
// (Advanced) Power Management
|
1619 |
|
|
|
1620 |
|
|
#ifndef AT91_PMC
|
1621 |
|
|
#define AT91_PMC 0xFFFF4000
|
1622 |
|
|
#endif
|
1623 |
|
|
|
1624 |
|
|
#define AT91_PMC_SCER 0x00
|
1625 |
|
|
#define AT91_PMC_SCDR 0x04
|
1626 |
|
|
#define AT91_PMC_SCSR 0x08
|
1627 |
|
|
|
1628 |
|
|
#define AT91_PMC_PCER 0x10
|
1629 |
|
|
#define AT91_PMC_PCDR 0x14
|
1630 |
|
|
#define AT91_PMC_PCSR 0x18
|
1631 |
|
|
|
1632 |
|
|
#define AT91_PMC_CGMR 0x20
|
1633 |
|
|
|
1634 |
|
|
#ifndef AT91_PMC_SR
|
1635 |
|
|
#define AT91_PMC_SR 0x30
|
1636 |
|
|
#endif
|
1637 |
|
|
|
1638 |
|
|
#ifndef AT91_PMC_IER
|
1639 |
|
|
#define AT91_PMC_IER 0x34
|
1640 |
|
|
#endif
|
1641 |
|
|
|
1642 |
|
|
#ifndef AT91_PMC_IDR
|
1643 |
|
|
#define AT91_PMC_IDR 0x38
|
1644 |
|
|
#endif
|
1645 |
|
|
|
1646 |
|
|
#ifndef AT91_PMC_IMR
|
1647 |
|
|
#define AT91_PMC_IMR 0x3c
|
1648 |
|
|
#endif
|
1649 |
|
|
|
1650 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
|
1651 |
|
|
|
1652 |
|
|
#define AT91_PMC_PCER_US0 (1<<2)
|
1653 |
|
|
#define AT91_PMC_PCER_US1 (1<<3)
|
1654 |
|
|
#define AT91_PMC_PCER_SPIA (1<<4)
|
1655 |
|
|
#define AT91_PMC_PCER_SPIB (1<<5)
|
1656 |
|
|
#define AT91_PMC_PCER_TC0 (1<<6)
|
1657 |
|
|
#define AT91_PMC_PCER_TC1 (1<<7)
|
1658 |
|
|
#define AT91_PMC_PCER_TC2 (1<<8)
|
1659 |
|
|
#define AT91_PMC_PCER_TC3 (1<<9)
|
1660 |
|
|
#define AT91_PMC_PCER_TC4 (1<<10)
|
1661 |
|
|
#define AT91_PMC_PCER_TC5 (1<<11)
|
1662 |
|
|
#define AT91_PMC_PCER_PIOA (1<<13)
|
1663 |
|
|
#define AT91_PMC_PCER_PIOB (1<<14)
|
1664 |
|
|
|
1665 |
|
|
#define AT91_PMC_CGMR_PRES_NONE 0
|
1666 |
|
|
#define AT91_PMC_CGMR_PRES_DIV2 1
|
1667 |
|
|
#define AT91_PMC_CGMR_PRES_DIV4 2
|
1668 |
|
|
#define AT91_PMC_CGMR_PRES_DIV8 3
|
1669 |
|
|
#define AT91_PMC_CGMR_PRES_DIV16 4
|
1670 |
|
|
#define AT91_PMC_CGMR_PRES_DIV32 5
|
1671 |
|
|
#define AT91_PMC_CGMR_PRES_DIV64 6
|
1672 |
|
|
#define AT91_PMC_CGMR_PRES_RES 7
|
1673 |
|
|
#define AT91_PMC_CGMR_PLLA 0x00
|
1674 |
|
|
#define AT91_PMC_CGMR_PLLB 0x08
|
1675 |
|
|
#define AT91_PMC_CGMR_MCK_SLCK (0<<4)
|
1676 |
|
|
#define AT91_PMC_CGMR_MCK_MCK (1<<4)
|
1677 |
|
|
#define AT91_PMC_CGMR_MCK_MCKINV (2<<4)
|
1678 |
|
|
#define AT91_PMC_CGMR_MCK_MCKD2 (3<<4)
|
1679 |
|
|
#define AT91_PMC_CGMR_MCKO_ENA (0<<6)
|
1680 |
|
|
#define AT91_PMC_CGMR_MCKO_DIS (1<<6)
|
1681 |
|
|
#define AT91_PMC_CGMR_CSS_SLCK (0<<7)
|
1682 |
|
|
#define AT91_PMC_CGMR_CSS_PLL (1<<7)
|
1683 |
|
|
|
1684 |
|
|
#define AT91_PMC_CGMR_PLL_MUL(x) ((x)<<8)
|
1685 |
|
|
#define AT91_PMC_CGMR_PLL_CNT(x) ((x)<<24)
|
1686 |
|
|
|
1687 |
|
|
#define AT91_PMC_SR_LOCK 0x01
|
1688 |
|
|
|
1689 |
|
|
#elif defined(CYGHWR_HAL_ARM_AT91_M55800A)
|
1690 |
|
|
|
1691 |
|
|
#define AT91_PMC_PCER_US0 (1<<2)
|
1692 |
|
|
#define AT91_PMC_PCER_US1 (1<<3)
|
1693 |
|
|
#define AT91_PMC_PCER_US2 (1<<4)
|
1694 |
|
|
#define AT91_PMC_PCER_SPI (1<<5)
|
1695 |
|
|
#define AT91_PMC_PCER_TC0 (1<<6)
|
1696 |
|
|
#define AT91_PMC_PCER_TC1 (1<<7)
|
1697 |
|
|
#define AT91_PMC_PCER_TC2 (1<<8)
|
1698 |
|
|
#define AT91_PMC_PCER_TC3 (1<<9)
|
1699 |
|
|
#define AT91_PMC_PCER_TC4 (1<<10)
|
1700 |
|
|
#define AT91_PMC_PCER_TC5 (1<<11)
|
1701 |
|
|
#define AT91_PMC_PCER_PIOA (1<<13)
|
1702 |
|
|
#define AT91_PMC_PCER_PIOB (1<<14)
|
1703 |
|
|
#define AT91_PMC_PCER_ADC0 (1<<15)
|
1704 |
|
|
#define AT91_PMC_PCER_ADC1 (1<<16)
|
1705 |
|
|
#define AT91_PMC_PCER_DAC0 (1<<17)
|
1706 |
|
|
#define AT91_PMC_PCER_DAC1 (1<<18)
|
1707 |
|
|
|
1708 |
|
|
#define AT91_PMC_CGMR_MOSC_XTAL 0
|
1709 |
|
|
#define AT91_PMC_CGMR_MOSC_BYP 1
|
1710 |
|
|
#define AT91_PMC_CGMR_MOSC_DIS (0<<1)
|
1711 |
|
|
#define AT91_PMC_CGMR_MOSC_ENA (1<<1)
|
1712 |
|
|
#define AT91_PMC_CGMR_MCKO_ENA (0<<2)
|
1713 |
|
|
#define AT91_PMC_CGMR_MCKO_DIS (1<<2)
|
1714 |
|
|
#define AT91_PMC_CGMR_PRES_NONE (0<<4)
|
1715 |
|
|
#define AT91_PMC_CGMR_PRES_DIV2 (1<<4)
|
1716 |
|
|
#define AT91_PMC_CGMR_PRES_DIV4 (2<<4)
|
1717 |
|
|
#define AT91_PMC_CGMR_PRES_DIV8 (3<<4)
|
1718 |
|
|
#define AT91_PMC_CGMR_PRES_DIV16 (4<<4)
|
1719 |
|
|
#define AT91_PMC_CGMR_PRES_DIV32 (5<<4)
|
1720 |
|
|
#define AT91_PMC_CGMR_PRES_DIV64 (6<<4)
|
1721 |
|
|
#define AT91_PMC_CGMR_PRES_RES (7<<4)
|
1722 |
|
|
#define AT91_PMC_CGMR_CSS_LF (0<<14)
|
1723 |
|
|
#define AT91_PMC_CGMR_CSS_MOSC (1<<14)
|
1724 |
|
|
#define AT91_PMC_CGMR_CSS_PLL (2<<14)
|
1725 |
|
|
#define AT91_PMC_CGMR_CSS_RES (3<<14)
|
1726 |
|
|
|
1727 |
|
|
#define AT91_PMC_CGMR_PLL_MUL(x) ((x)<<8)
|
1728 |
|
|
#define AT91_PMC_CGMR_OSC_CNT(x) ((x)<<16)
|
1729 |
|
|
#define AT91_PMC_CGMR_PLL_CNT(x) ((x)<<24)
|
1730 |
|
|
|
1731 |
|
|
#define AT91_PMC_PCR 0x28
|
1732 |
|
|
#define AT91_PMC_PCR_SHDALC 1
|
1733 |
|
|
#define AT91_PMC_PCR_WKACKC 2
|
1734 |
|
|
|
1735 |
|
|
#define AT91_PMC_PMR 0x2c
|
1736 |
|
|
#define AT91_PMC_PMR_SHDALS_TRI 0
|
1737 |
|
|
#define AT91_PMC_PMR_SHDALS_LEVEL0 1
|
1738 |
|
|
#define AT91_PMC_PMR_SHDALS_LEVEL1 2
|
1739 |
|
|
#define AT91_PMC_PMR_SHDALS_RES 3
|
1740 |
|
|
#define AT91_PMC_PMR_WKACKS_TRI (0<<2)
|
1741 |
|
|
#define AT91_PMC_PMR_WKACKS_LEVEL0 (1<<2)
|
1742 |
|
|
#define AT91_PMC_PMR_WKACKS_LEVEL1 (2<<2)
|
1743 |
|
|
#define AT91_PMC_PMR_WKACKS_RES (3<<2)
|
1744 |
|
|
#define AT91_PMC_PMR_ALWKEN (1<<4)
|
1745 |
|
|
#define AT91_PMC_PMR_ALSHEN (1<<5)
|
1746 |
|
|
|
1747 |
|
|
#define AT91_PMC_PMR_WKEDG_NONE (0<<6)
|
1748 |
|
|
#define AT91_PMC_PMR_WKEDG_POS (1<<6)
|
1749 |
|
|
#define AT91_PMC_PMR_WKEDG_NEG (2<<6)
|
1750 |
|
|
#define AT91_PMC_PMR_WKEDG_BOTH (3<<6)
|
1751 |
|
|
|
1752 |
|
|
#define AT91_PMC_SR_MOSCS 0x01
|
1753 |
|
|
#define AT91_PMC_SR_LOCK 0x02
|
1754 |
|
|
|
1755 |
|
|
#elif defined(CYGHWR_HAL_ARM_AT91_JTST)
|
1756 |
|
|
// No power management control for the JTST
|
1757 |
|
|
|
1758 |
|
|
#elif defined(CYGHWR_HAL_ARM_AT91SAM7S)
|
1759 |
|
|
#define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock
|
1760 |
|
|
#define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock
|
1761 |
|
|
#define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output
|
1762 |
|
|
#define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output
|
1763 |
|
|
#define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output
|
1764 |
|
|
#define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
|
1765 |
|
|
|
1766 |
|
|
#define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
|
1767 |
|
|
#define AT91_PMC_PCER_ADC (1 << 4) // Analog-to-Digital Converter
|
1768 |
|
|
#define AT91_PMC_PCER_SPI (1 << 5) // Serial Peripheral Interface
|
1769 |
|
|
#define AT91_PMC_PCER_US0 (1 << 6) // USART 0
|
1770 |
|
|
#define AT91_PMC_PCER_US1 (1 << 7) // USART 1
|
1771 |
|
|
#define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller
|
1772 |
|
|
#define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface
|
1773 |
|
|
#define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller
|
1774 |
|
|
#define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port
|
1775 |
|
|
#define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0
|
1776 |
|
|
#define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1
|
1777 |
|
|
#define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2
|
1778 |
|
|
|
1779 |
|
|
#elif defined(CYGHWR_HAL_ARM_AT91SAM7X)
|
1780 |
|
|
#define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock
|
1781 |
|
|
#define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock
|
1782 |
|
|
#define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output
|
1783 |
|
|
#define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output
|
1784 |
|
|
#define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output
|
1785 |
|
|
#define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
|
1786 |
|
|
|
1787 |
|
|
#define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
|
1788 |
|
|
#define AT91_PMC_PCER_PIOB (1 << 3) // Parallel IO Controller
|
1789 |
|
|
#define AT91_PMC_PCER_SPI (1 << 4) // Serial Peripheral Interface
|
1790 |
|
|
#define AT91_PMC_PCER_SPI1 (1 << 5) // Serial Peripheral Interface
|
1791 |
|
|
#define AT91_PMC_PCER_US0 (1 << 6) // USART 0
|
1792 |
|
|
#define AT91_PMC_PCER_US1 (1 << 7) // USART 1
|
1793 |
|
|
#define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller
|
1794 |
|
|
#define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface
|
1795 |
|
|
#define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller
|
1796 |
|
|
#define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port
|
1797 |
|
|
#define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0
|
1798 |
|
|
#define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1
|
1799 |
|
|
#define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2
|
1800 |
|
|
#define AT91_PMC_PCER_CAN (1 <<15) // Controller Area Network
|
1801 |
|
|
#define AT91_PMC_PCER_EMAC (1 <<16) // Ethernet MAC
|
1802 |
|
|
#define AT91_PMC_PCER_ADC (1 <<17) // Analog-to-Digital Converter
|
1803 |
|
|
|
1804 |
|
|
#elif defined(CYGHWR_HAL_ARM_AT91SAM7SE)
|
1805 |
|
|
#define AT91_PMC_SCER_PCK (1 << 0) // Processor Clock
|
1806 |
|
|
#define AT91_PMC_SCER_UDP (1 << 7) // USB Device Clock
|
1807 |
|
|
#define AT91_PMC_SCER_PCK0 (1 << 8) // Programmable Clock Output
|
1808 |
|
|
#define AT91_PMC_SCER_PCK1 (1 << 9) // Programmable Clock Output
|
1809 |
|
|
#define AT91_PMC_SCER_PCK2 (1 << 10) // Programmable Clock Output
|
1810 |
|
|
#define AT91_PMC_SCER_PCK3 (1 << 11) // Programmable Clock Output
|
1811 |
|
|
|
1812 |
|
|
#define AT91_PMC_PCER_PIOA (1 << 2) // Parallel IO Controller
|
1813 |
|
|
#define AT91_PMC_PCER_PIOB (1 << 3) // Parallel IO Controller
|
1814 |
|
|
#define AT91_PMC_PCER_PIOC (1 << 4) // Parallel IO Controller
|
1815 |
|
|
#define AT91_PMC_PCER_SPI (1 << 5) // Serial Peripheral Interface
|
1816 |
|
|
#define AT91_PMC_PCER_US0 (1 << 6) // USART 0
|
1817 |
|
|
#define AT91_PMC_PCER_US1 (1 << 7) // USART 1
|
1818 |
|
|
#define AT91_PMC_PCER_SSC (1 << 8) // Serial Synchronous Controller
|
1819 |
|
|
#define AT91_PMC_PCER_TWI (1 << 9) // Two-Wire Interface
|
1820 |
|
|
#define AT91_PMC_PCER_PWMC (1 <<10) // PWM Controller
|
1821 |
|
|
#define AT91_PMC_PCER_UDP (1 <<11) // USB Device Port
|
1822 |
|
|
#define AT91_PMC_PCER_TC0 (1 <<12) // Timer Counter 0
|
1823 |
|
|
#define AT91_PMC_PCER_TC1 (1 <<13) // Timer Counter 1
|
1824 |
|
|
#define AT91_PMC_PCER_TC2 (1 <<14) // Timer Counter 2
|
1825 |
|
|
#define AT91_PMC_PCER_ADC (1 <<15) // Analog-to-Digital Converter
|
1826 |
|
|
|
1827 |
|
|
#else // Something unknown
|
1828 |
|
|
|
1829 |
|
|
#error Unknown AT91 variant
|
1830 |
|
|
|
1831 |
|
|
#endif
|
1832 |
|
|
#endif
|
1833 |
|
|
|
1834 |
|
|
//=============================================================================
|
1835 |
|
|
// Watchdog
|
1836 |
|
|
|
1837 |
|
|
#ifndef AT91_WD
|
1838 |
|
|
#define AT91_WD 0xFFFF8000
|
1839 |
|
|
#endif
|
1840 |
|
|
|
1841 |
|
|
#define AT91_WD_OMR 0x00
|
1842 |
|
|
#define AT91_WD_OMR_WDEN 0x00000001
|
1843 |
|
|
#define AT91_WD_OMR_RSTEN 0x00000002
|
1844 |
|
|
#define AT91_WD_OMR_IRQEN 0x00000004
|
1845 |
|
|
#define AT91_WD_OMR_EXTEN 0x00000008
|
1846 |
|
|
#define AT91_WD_OMR_OKEY (0x00000234 << 4)
|
1847 |
|
|
#define AT91_WD_CMR 0x04
|
1848 |
|
|
#define AT91_WD_CMR_WDCLKS 0x00000003
|
1849 |
|
|
#define AT91_WD_CMR_HPCV 0x0000003C
|
1850 |
|
|
#define AT91_WD_CMR_CKEY (0x0000006E << 7)
|
1851 |
|
|
#define AT91_WD_CR 0x08
|
1852 |
|
|
#define AT91_WD_CR_RSTKEY 0x0000C071
|
1853 |
|
|
#define AT91_WD_SR 0x0C
|
1854 |
|
|
#define AT91_WD_SR_WDOVF 0x00000001
|
1855 |
|
|
|
1856 |
|
|
//=============================================================================
|
1857 |
|
|
// SPI
|
1858 |
|
|
|
1859 |
|
|
#ifndef AT91_SPI
|
1860 |
|
|
#define AT91_SPI 0xFFFBC000
|
1861 |
|
|
#endif
|
1862 |
|
|
|
1863 |
|
|
#define AT91_SPI_CR 0x00 // Control Register
|
1864 |
|
|
#define AT91_SPI_CR_SPIEN 0x00000001 // SPI Enable
|
1865 |
|
|
#define AT91_SPI_CR_SPIDIS 0x00000002 // SPI Disable
|
1866 |
|
|
#define AT91_SPI_CR_SWRST 0x00000080 // SPI Software reset
|
1867 |
|
|
#define AT91_SPI_MR 0x04 // Mode Register
|
1868 |
|
|
#define AT91_SPI_MR_MSTR 0x00000001 // Master/Slave Mode
|
1869 |
|
|
#define AT91_SPI_MR_PS 0x00000002 // Peripheral Select
|
1870 |
|
|
#define AT91_SPI_MR_PCSDEC 0x00000004 // Chip Select Decode
|
1871 |
|
|
#define AT91_SPI_MR_DIV32 0x00000008 // Clock Selection
|
1872 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
1873 |
|
|
#define AT91_SPI_MR_MODFDIS (1<<4) // Mode Failure Detect Disable
|
1874 |
|
|
#endif
|
1875 |
|
|
#define AT91_SPI_MR_LLB 0x00000080 // Local Loopback Enable
|
1876 |
|
|
#define AT91_SPI_MR_PCS(x) (((x)&0x0F)<<16) // Peripheral Chip Select
|
1877 |
|
|
#define AT91_SPI_MR_DLYBCS(x) (((x)&0xFF)<<24) // Delay Between Chip Selects
|
1878 |
|
|
#define AT91_SPI_RDR 0x08 // Receive Data Register
|
1879 |
|
|
#define AT91_SPI_TDR 0x0C // Transmit Data Register
|
1880 |
|
|
#define AT91_SPI_SR 0x10 // Status Register
|
1881 |
|
|
#define AT91_SPI_SR_RDRF 0x00000001 // Receive Data Register Full
|
1882 |
|
|
#define AT91_SPI_SR_TDRE 0x00000002 // Tx Data Register Empty
|
1883 |
|
|
#define AT91_SPI_SR_MODF 0x00000004 // Mode Fault Error
|
1884 |
|
|
#define AT91_SPI_SR_OVRES 0x00000008 // Overrun Error Status
|
1885 |
|
|
#define AT91_SPI_SR_ENDRX 0x00000010 // End of Receiver Transfer
|
1886 |
|
|
#define AT91_SPI_SR_ENDTX 0x00000020 // End of Transmitter Transfer
|
1887 |
|
|
#define AT91_SPI_SR_RXBUFF 0x00000040 // RX Buffer Full
|
1888 |
|
|
#define AT91_SPI_SR_TXBUFE 0x00000080 // TX Buffer Empty
|
1889 |
|
|
#define AT91_SPI_SR_NSSR 0x00000100 // NSS Rising
|
1890 |
|
|
#define AT91_SPI_SR_TXEMPTY 0x00000200 // Transmission Registers Empty
|
1891 |
|
|
#define AT91_SPI_SR_SPIENS 0x00010000 // SPI Enable Status
|
1892 |
|
|
#define AT91_SPI_IER 0x14 // Interrupt Enable Register
|
1893 |
|
|
#define AT91_SPI_IDR 0x18 // Interrupt Disable Register
|
1894 |
|
|
#define AT91_SPI_IMR 0x1C // Interrupt Mask Register
|
1895 |
|
|
// DMA registers are PDC registers
|
1896 |
|
|
// can be different from target to target
|
1897 |
|
|
#ifndef AT91_SPI_RPR
|
1898 |
|
|
#define AT91_SPI_RPR 0x20 // Receive Pointer Register
|
1899 |
|
|
#endif
|
1900 |
|
|
#ifndef AT91_SPI_RCR
|
1901 |
|
|
#define AT91_SPI_RCR 0x24 // Receive Counter Register
|
1902 |
|
|
#endif
|
1903 |
|
|
#ifndef AT91_SPI_TPR
|
1904 |
|
|
#define AT91_SPI_TPR 0x28 // Transmit Pointer Register
|
1905 |
|
|
#endif
|
1906 |
|
|
#ifndef AT91_SPI_TCR
|
1907 |
|
|
#define AT91_SPI_TCR 0x2C // Transmit Counter Register
|
1908 |
|
|
#endif
|
1909 |
|
|
|
1910 |
|
|
// PDC Control register bits
|
1911 |
|
|
#define AT91_SPI_PTCR_RXTEN (1 << 0)
|
1912 |
|
|
#define AT91_SPI_PTCR_RXTDIS (1 << 1)
|
1913 |
|
|
#define AT91_SPI_PTCR_TXTEN (1 << 8)
|
1914 |
|
|
#define AT91_SPI_PTCR_TXTDIS (1 << 9)
|
1915 |
|
|
|
1916 |
|
|
#define AT91_SPI_CSR0 0x30 // Chip Select Register 0
|
1917 |
|
|
#define AT91_SPI_CSR1 0x34 // Chip Select Register 1
|
1918 |
|
|
#define AT91_SPI_CSR2 0x38 // Chip Select Register 2
|
1919 |
|
|
#define AT91_SPI_CSR3 0x3C // Chip Select Register 3
|
1920 |
|
|
#define AT91_SPI_CSR_CPOL 0x00000001 // Clock Polarity
|
1921 |
|
|
#define AT91_SPI_CSR_NCPHA 0x00000002 // Clock Phase
|
1922 |
|
|
#define AT91_SPI_CSR_BITS(x) (((x)&0x0F)<<4) // Bits Per Transfer
|
1923 |
|
|
#define AT91_SPI_CSR_BITS8 AT91_SPI_CSR_BITS(0)
|
1924 |
|
|
#define AT91_SPI_CSR_BITS9 AT91_SPI_CSR_BITS(1)
|
1925 |
|
|
#define AT91_SPI_CSR_BITS10 AT91_SPI_CSR_BITS(2)
|
1926 |
|
|
#define AT91_SPI_CSR_BITS11 AT91_SPI_CSR_BITS(3)
|
1927 |
|
|
#define AT91_SPI_CSR_BITS12 AT91_SPI_CSR_BITS(4)
|
1928 |
|
|
#define AT91_SPI_CSR_BITS13 AT91_SPI_CSR_BITS(5)
|
1929 |
|
|
#define AT91_SPI_CSR_BITS14 AT91_SPI_CSR_BITS(6)
|
1930 |
|
|
#define AT91_SPI_CSR_BITS15 AT91_SPI_CSR_BITS(7)
|
1931 |
|
|
#define AT91_SPI_CSR_BITS16 AT91_SPI_CSR_BITS(8)
|
1932 |
|
|
#define AT91_SPI_CSR_SCBR(x) (((x)&0xFF)<<8) // Serial Clock Baud Rate
|
1933 |
|
|
#define AT91_SPI_CSR_DLYBS(x) (((x)&0xFF)<<16) // Delay Before SPCK
|
1934 |
|
|
#define AT91_SPI_CSR_DLYBCT(x) (((x)&0xFF)<<24) // Delay Between two transfers
|
1935 |
|
|
|
1936 |
|
|
//=============================================================================
|
1937 |
|
|
// Watchdog Timer Controller
|
1938 |
|
|
|
1939 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
1940 |
|
|
|
1941 |
|
|
#ifndef AT91_WDTC
|
1942 |
|
|
#define AT91_WDTC 0xFFFFFD40
|
1943 |
|
|
#endif
|
1944 |
|
|
|
1945 |
|
|
#define AT91_WDTC_WDCR 0x00 // Watchdog Control Register
|
1946 |
|
|
#define AT91_WDTC_WDCR_RELOAD (1 << 0) // Reload the watchdog
|
1947 |
|
|
#define AT91_WDTC_WDCR_KEY (0xa5 << 24) // Password for the write op
|
1948 |
|
|
#define AT91_WDTC_WDMR 0x04 // Watchdog Mode Register
|
1949 |
|
|
#define AT91_WDTC_WDMR_FIEN (1 << 12) // Fault Interrupt Mode Enable
|
1950 |
|
|
#define AT91_WDTC_WDMR_RSTEN (1 << 13) // Reset Enable
|
1951 |
|
|
#define AT91_WDTC_WDMR_RPROC (1 << 14) // Trigger a processor reset
|
1952 |
|
|
#define AT91_WDTC_WDMR_DIS (1 << 15) // Disable
|
1953 |
|
|
#define AT91_WDTC_WDMR_WDD_SHIFT (16) // Delta Value shift
|
1954 |
|
|
#define AT91_WDTC_WDMR_DBGHLT (1 << 28) // Stop when in debug state
|
1955 |
|
|
#define AT91_WDTC_WDMR_IDLEHLT (1 << 29) // Stop when in idle more
|
1956 |
|
|
#define AT91_WDTC_WDSR 0x08 // Watchdog Status Register
|
1957 |
|
|
#define AT91_WDTC_WDSR_UNDER (1 << 0) // Underflow has occurred
|
1958 |
|
|
#define AT91_WDTC_WDSR_ERROR (1 << 1) // Error has occurred
|
1959 |
|
|
#endif //CYGHWR_HAL_ARM_AT91SAM7
|
1960 |
|
|
|
1961 |
|
|
//=============================================================================
|
1962 |
|
|
// Reset Controller
|
1963 |
|
|
|
1964 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
1965 |
|
|
|
1966 |
|
|
#ifndef AT91_RST
|
1967 |
|
|
#define AT91_RST 0xFFFFFD00
|
1968 |
|
|
#endif
|
1969 |
|
|
|
1970 |
|
|
#define AT91_RST_RCR 0x00 // Reset Control Register
|
1971 |
|
|
#define AT91_RST_RCR_PROCRST (1 << 0) // Processor Reset
|
1972 |
|
|
#define AT91_RST_RCR_ICERST (1 << 1) // ICE Reset
|
1973 |
|
|
#define AT91_RST_RCR_PERRST (1 << 2) // Peripheral Reset
|
1974 |
|
|
#define AT91_RST_RCR_EXTRST (1 << 3) // External Reset
|
1975 |
|
|
#define AT91_RST_RCR_KEY (0xA5 << 24) // Key
|
1976 |
|
|
#define AT91_RST_RSR 0x04 // Reset Status Register
|
1977 |
|
|
#define AT91_RST_RSR_USER (1 << 0) // User Reset
|
1978 |
|
|
#define AT91_RST_RSR_BROWN (1 << 1) // Brownout detected
|
1979 |
|
|
#define AT91_RST_RSR_TYPE_POWERUP (0 << 8) // Power on Reset
|
1980 |
|
|
#define AT91_RST_RSR_TYPE_WATCHDOG (2 << 8) // Watchdog Reset
|
1981 |
|
|
#define AT91_RST_RSR_TYPE_SW (3 << 8) // Software Reset
|
1982 |
|
|
#define AT91_RST_RSR_TYPE_USER (4 << 8) // NRST pin Reset
|
1983 |
|
|
#define AT91_RST_RSR_TYPE_BROWNOUT (5 << 8) // Brown-out Reset
|
1984 |
|
|
#define AT91_RST_RSR_NRST_SET (1 << 16) // NRST pin set
|
1985 |
|
|
#define AT91_RST_RSR_SRCMP (1 << 17) // Software reset in progress
|
1986 |
|
|
#define AT91_RST_RMR 0x08 // Reset Mode Register
|
1987 |
|
|
#define AT91_RST_RMR_URSTEN (1 << 0) // User Reset Enabled
|
1988 |
|
|
#define AT91_RST_RMR_URSTIEN (1 << 4) // User Reset Interrupt Enabled
|
1989 |
|
|
#define AT91_RST_RMR_BODIEN (1 << 16) // Brownout Dection Interrupt Enabled
|
1990 |
|
|
#define AT91_RST_RMR_KEY (0xA5 << 24) // Key
|
1991 |
|
|
|
1992 |
|
|
#endif
|
1993 |
|
|
|
1994 |
|
|
//=============================================================================
|
1995 |
|
|
// Memory Controller
|
1996 |
|
|
|
1997 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
1998 |
|
|
|
1999 |
|
|
#ifndef AT91_MC
|
2000 |
|
|
#define AT91_MC 0xFFFFFF00
|
2001 |
|
|
#endif
|
2002 |
|
|
|
2003 |
|
|
#define AT91_MC_RCR 0x00 // Remap Control Register
|
2004 |
|
|
#define AT91_MC_ASR 0x04 // Abort Status Register
|
2005 |
|
|
#define AT91_MC_AASR 0x08 // Abort Address Status Register
|
2006 |
|
|
#ifndef AT91_MC_FMR
|
2007 |
|
|
#define AT91_MC_FMR 0x60 // Flash Mode Register
|
2008 |
|
|
#endif
|
2009 |
|
|
#define AT91_MC_FMR_FRDY (1 << 0) // Enable interrupt for Flash Ready
|
2010 |
|
|
#define AT91_MC_FMR_LOCKE (1 << 2) // Enable interrupt for Flash Lock Error
|
2011 |
|
|
#define AT91_MC_FMR_PROGE (1 << 3) // Enable interrupt for Flash Prog Error
|
2012 |
|
|
#define AT91_MC_FMR_NEBP (1 << 7) // No erase before programming
|
2013 |
|
|
#define AT91_MC_FMR_0FWS (0 << 8) // 1R,2W wait states
|
2014 |
|
|
#define AT91_MC_FMR_1FWS (1 << 8) // 2R,3W wait states
|
2015 |
|
|
#define AT91_MC_FMR_2FWS (2 << 8) // 3R,4W wait states
|
2016 |
|
|
#define AT91_MC_FMR_3FWS (3 << 8) // 4R,4W wait states
|
2017 |
|
|
#define AT91_MC_FMR_FMCN_MASK (0xff << 16)
|
2018 |
|
|
#define AT91_MC_FMR_FMCN_SHIFT 16
|
2019 |
|
|
#ifndef AT91_MC_FCR
|
2020 |
|
|
#define AT91_MC_FCR 0x64 // Flash Command Register
|
2021 |
|
|
#endif
|
2022 |
|
|
#define AT91_MC_FCR_START_PROG (0x1 << 0) // Start Programming of Page
|
2023 |
|
|
#define AT91_MC_FCR_LOCK (0x2 << 0) // Lock sector
|
2024 |
|
|
#define AT91_MC_FCR_PROG_LOCK (0x3 << 0) // Program and Lock
|
2025 |
|
|
#define AT91_MC_FCR_UNLOCK (0x4 << 0) // Unlock a segment
|
2026 |
|
|
#define AT91_MC_FCR_ERASE_ALL (0x8 << 0) // Erase everything
|
2027 |
|
|
#define AT91_MC_FCR_SET_GP_NVM (0xb << 0) // Set general purpose NVM bits
|
2028 |
|
|
#define AT91_MC_FCR_CLR_GP_NVM (0xd << 0) // Clear general purpose NVM bits
|
2029 |
|
|
#define AT91_MC_FCR_SET_SECURITY (0xf << 0) // Set security bit
|
2030 |
|
|
#define AT91_MC_FCR_PAGE_MASK (0x3ff)
|
2031 |
|
|
#define AT91_MC_FCR_PAGE_SHIFT 8
|
2032 |
|
|
#define AT91_MC_FCR_KEY (0x5a << 24) // Key to enable command
|
2033 |
|
|
#ifndef AT91_MC_FSR
|
2034 |
|
|
#define AT91_MC_FSR 0x68 // Flash Status Register
|
2035 |
|
|
#endif
|
2036 |
|
|
#define AT91_MC_FSR_FRDY (1 << 0) // Flash Ready for next command
|
2037 |
|
|
#define AT91_MC_FSR_LOCKE (1 << 2) // Programming of a locked block
|
2038 |
|
|
#define AT91_MC_FSR_PROGE (1 << 3) // Programming error
|
2039 |
|
|
#define AT91_MC_FSR_SECURITY (1 << 4) // Security bit is set
|
2040 |
|
|
#define AT91_MC_FSR_GPNVM0 (1 << 8) // General purpose NVM bit 0
|
2041 |
|
|
#define AT91_MC_FSR_GPNVM1 (1 << 9) // General purpose NVM bit 1
|
2042 |
|
|
#endif
|
2043 |
|
|
|
2044 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7SE)
|
2045 |
|
|
#define AT91_MC_PUIA(n) (0x10+(n)*4) // MC Protection Unit Area n
|
2046 |
|
|
#define AT91_MC_PUIA_PROT_MASK (0x3 << 0) // Protection mask
|
2047 |
|
|
#define AT91_MC_PUIA_PROT_PNAUNA (0x0 << 0) // No Access, User=No Access
|
2048 |
|
|
#define AT91_MC_PUIA_PROT_PRWUNA (0x1 << 0) // Privilige=R/W, User=No Access
|
2049 |
|
|
#define AT91_MC_PUIA_PROT_PRWURO (0x2 << 0) // Privilige=R/W, User=R Only
|
2050 |
|
|
#define AT91_MC_PUIA_PROT_PRWURW (0x3 << 0) // Privilige=R/W, User=R/W
|
2051 |
|
|
#define AT91_MC_PUIA_SIZE_MASK (0xF << 4) // Area Size mask
|
2052 |
|
|
#define AT91_MC_PUIA_SIZE_1KB (0x0 << 4) // Area Size=1KB
|
2053 |
|
|
#define AT91_MC_PUIA_SIZE_2KB (0x1 << 4) // Area Size=2KB
|
2054 |
|
|
#define AT91_MC_PUIA_SIZE_4KB (0x2 << 4) // Area Size=4KB
|
2055 |
|
|
#define AT91_MC_PUIA_SIZE_8KB (0x3 << 4) // Area Size=8KB
|
2056 |
|
|
#define AT91_MC_PUIA_SIZE_16KB (0x4 << 4) // Area Size=16KB
|
2057 |
|
|
#define AT91_MC_PUIA_SIZE_32KB (0x5 << 4) // Area Size=32KB
|
2058 |
|
|
#define AT91_MC_PUIA_SIZE_64KB (0x6 << 4) // Area Size=64KB
|
2059 |
|
|
#define AT91_MC_PUIA_SIZE_128KB (0x7 << 4) // Area Size=128KB
|
2060 |
|
|
#define AT91_MC_PUIA_SIZE_256KB (0x8 << 4) // Area Size=256KB
|
2061 |
|
|
#define AT91_MC_PUIA_SIZE_512KB (0x9 << 4) // Area Size=512KB
|
2062 |
|
|
#define AT91_MC_PUIA_SIZE_1MB (0xA << 4) // Area Size=1MB
|
2063 |
|
|
#define AT91_MC_PUIA_SIZE_2MB (0xB << 4) // Area Size=2MB
|
2064 |
|
|
// Datasheet says value is 0xD, but it's out of the sequence and
|
2065 |
|
|
// Atmel header also says 0xC.
|
2066 |
|
|
#define AT91_MC_PUIA_SIZE_4MB (0xC << 4) // Area Size=4MB
|
2067 |
|
|
// The following are not mentioned in datasheet, but present in Atmel header
|
2068 |
|
|
#define AT91_MC_PUIA_SIZE_8MB (0xD << 4) // Area Size=8MByte
|
2069 |
|
|
#define AT91_MC_PUIA_SIZE_16MB (0xE << 4) // Area Size=16MByte
|
2070 |
|
|
#define AT91_MC_PUIA_SIZE_64MB (0xF << 4) // Area Size=64MByte
|
2071 |
|
|
#define AT91_MC_BA_MASK (0x3FFFF << 10) // Area Base Address Mask
|
2072 |
|
|
#define AT91_MC_BA(addr) ((addr) << 10) // Set Area Base Address in
|
2073 |
|
|
// multiples of 1KB (must be
|
2074 |
|
|
// a multiple of the selected
|
2075 |
|
|
// Area Size)
|
2076 |
|
|
#define AT91_MC_PUP 0x50 // MC Protection Unit Peripherals
|
2077 |
|
|
#define AT91_MC_PUP_PROT_MASK (0x3 << 0) // Protection mask
|
2078 |
|
|
#define AT91_MC_PUP_PROT_PNAUNA (0x0 << 0) // Privilige=No Access,
|
2079 |
|
|
// User=No Access (DO NOT USE)
|
2080 |
|
|
#define AT91_MC_PUP_PROT_PRWUNA (0x1 << 0) // Privilige=R/W, User=No Access
|
2081 |
|
|
#define AT91_MC_PUP_PROT_PRWURO (0x2 << 0) // Privilige=R/W, User=R Only
|
2082 |
|
|
#define AT91_MC_PUP_PROT_PRWURW (0x3 << 0) // Privilige=R/W, User=R/W
|
2083 |
|
|
#define AT91_MC_PUER 0x54 // Protection Unit Enable Register
|
2084 |
|
|
#define AT91_MC_PUER_PUEB (0x1) // Protection Unit Enable Bit
|
2085 |
|
|
// (PROGRAM ALL AREA REGISTERS BEFORE
|
2086 |
|
|
// ENABLE)
|
2087 |
|
|
#endif
|
2088 |
|
|
|
2089 |
|
|
//=============================================================================
|
2090 |
|
|
// Debug Unit
|
2091 |
|
|
|
2092 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2093 |
|
|
|
2094 |
|
|
#ifndef AT91_DBG
|
2095 |
|
|
#define AT91_DBG 0xFFFFF200
|
2096 |
|
|
#endif
|
2097 |
|
|
|
2098 |
|
|
#define AT91_DBG_CR 0x00 // Control Register
|
2099 |
|
|
#define AT91_DBG_CR_RSTRX (0x1 << 2) // Reset Receiver
|
2100 |
|
|
#define AT91_DBG_CR_RSTTX (0x1 << 3) // Reset Transmitter
|
2101 |
|
|
#define AT91_DBG_CR_RXEN (0x1 << 4) // Receiver Enable
|
2102 |
|
|
#define AT91_DBG_CR_RXDIS (0x1 << 5) // Receiver Disable
|
2103 |
|
|
#define AT91_DBG_CR_TXEN (0x1 << 6) // Transmitter Enable
|
2104 |
|
|
#define AT91_DBG_CR_TXDIS (0x1 << 7) // Transmitter Disable
|
2105 |
|
|
#define AT91_DBG_CR_RSTSTA (0x1 << 8) // Reset Status Bits
|
2106 |
|
|
#define AT91_DBG_MR 0x04 // Mode Register
|
2107 |
|
|
#define AT91_DBG_MR_PAR_EVEN (0x0 << 9) // Even Parity
|
2108 |
|
|
#define AT91_DBG_MR_PAR_ODD (0x1 << 9) // Odd Parity
|
2109 |
|
|
#define AT91_DBG_MR_PAR_SPACE (0x2 << 9) // Parity forced to Space
|
2110 |
|
|
#define AT91_DBG_MR_PAR_MARK (0x3 << 9) // Parity forced to Mark
|
2111 |
|
|
#define AT91_DBG_MR_PAR_NONE (0x4 << 9) // No Parity
|
2112 |
|
|
#define AT91_DBG_MR_PAR_MULTI (0x6 << 9) // Multi-drop mode
|
2113 |
|
|
#define AT91_DBG_MR_CHMODE_NORMAL (0x0 << 14) // Normal mode
|
2114 |
|
|
#define AT91_DBG_MR_CHMODE_AUTO (0x1 << 14) // Automatic Echo
|
2115 |
|
|
#define AT91_DBG_MR_CHMODE_LOCAL (0x2 << 14) // Local Loopback
|
2116 |
|
|
#define AT91_DBG_MR_CHMODE_REMOTE (0x3 << 14) // Remote Loopback
|
2117 |
|
|
#define AT91_DBG_IER 0x08 // Interrupt Enable Register
|
2118 |
|
|
#define AT91_DBG_IDR 0x0c // Interrupt Disable Register
|
2119 |
|
|
#define AT91_DBG_IMR 0x10 // Interrupt Mask Register
|
2120 |
|
|
#define AT91_DBG_CSR 0x14 // Channel Status Register
|
2121 |
|
|
#define AT91_DBG_CSR_RXRDY (1 << 0) // Receiver Ready
|
2122 |
|
|
#define AT91_DBG_CSR_TXRDY (1 << 1) // Transmitter Ready
|
2123 |
|
|
#define AT91_DBG_RHR 0x18 // Receiver Holding Register
|
2124 |
|
|
#define AT91_DBG_THR 0x1c // Transmitter Holding Register
|
2125 |
|
|
#define AT91_DBG_BRGR 0x20 // Baud Rate Generator Register
|
2126 |
|
|
#define AT91_DBG_C1R 0x40 // Chip ID1 register
|
2127 |
|
|
#define AT91_DBG_C1R_ARM945ES (1 << 5)
|
2128 |
|
|
#define AT91_DBG_C1R_ARM7TDMI (2 << 5)
|
2129 |
|
|
#define AT91_DBG_C1R_ARM920T (4 << 5)
|
2130 |
|
|
#define AT91_DBG_C1R_ARM926EJ (5 << 5)
|
2131 |
|
|
#define AT91_DBG_C1R_CPU_MASK (0x7 << 5)
|
2132 |
|
|
#define AT91_DBG_C1R_FLASH_0K (0x0 << 8)
|
2133 |
|
|
#define AT91_DBG_C1R_FLASH_8K (0x1 << 8)
|
2134 |
|
|
#define AT91_DBG_C1R_FLASH_16K (0x2 << 8)
|
2135 |
|
|
#define AT91_DBG_C1R_FLASH_32K (0x3 << 8)
|
2136 |
|
|
#define AT91_DBG_C1R_FLASH_64K (0x5 << 8)
|
2137 |
|
|
#define AT91_DBG_C1R_FLASH_128K (0x7 << 8)
|
2138 |
|
|
#define AT91_DBG_C1R_FLASH_256K (0x9 << 8)
|
2139 |
|
|
#define AT91_DBG_C1R_FLASH_512K (0xa << 8)
|
2140 |
|
|
#define AT91_DBG_C1R_FLASH_1024K (0xc << 8)
|
2141 |
|
|
#define AT91_DBG_C1R_FLASH_2048K (0xe << 8)
|
2142 |
|
|
#define AT91_DBG_C1R_FLASH_MASK (0xf << 8)
|
2143 |
|
|
#define AT91_DBG_C1R_FLASH2_0K (0x0 << 12)
|
2144 |
|
|
#define AT91_DBG_C1R_FLASH2_8K (0x1 << 12)
|
2145 |
|
|
#define AT91_DBG_C1R_FLASH2_16K (0x2 << 12)
|
2146 |
|
|
#define AT91_DBG_C1R_FLASH2_32K (0x3 << 12)
|
2147 |
|
|
#define AT91_DBG_C1R_FLASH2_64K (0x5 << 12)
|
2148 |
|
|
#define AT91_DBG_C1R_FLASH2_128K (0x7 << 12)
|
2149 |
|
|
#define AT91_DBG_C1R_FLASH2_256K (0x9 << 12)
|
2150 |
|
|
#define AT91_DBG_C1R_FLASH2_512K (0xa << 12)
|
2151 |
|
|
#define AT91_DBG_C1R_FLASH2_1024K (0xc << 12)
|
2152 |
|
|
#define AT91_DBG_C1R_FLASH2_2048K (0xe << 12)
|
2153 |
|
|
#define AT91_DBG_C1R_FLASH2_MASK (0xf << 12)
|
2154 |
|
|
#define AT91_DBG_C1R_SRAM_1K (0x1 << 16)
|
2155 |
|
|
#define AT91_DBG_C1R_SRAM_2K (0x2 << 16)
|
2156 |
|
|
#define AT91_DBG_C1R_SRAM_112K (0x4 << 16)
|
2157 |
|
|
#define AT91_DBG_C1R_SRAM_4K (0x5 << 16)
|
2158 |
|
|
#define AT91_DBG_C1R_SRAM_80K (0x6 << 16)
|
2159 |
|
|
#define AT91_DBG_C1R_SRAM_160K (0x7 << 16)
|
2160 |
|
|
#define AT91_DBG_C1R_SRAM_8K (0x8 << 16)
|
2161 |
|
|
#define AT91_DBG_C1R_SRAM_16K (0x9 << 16)
|
2162 |
|
|
#define AT91_DBG_C1R_SRAM_32K (0xa << 16)
|
2163 |
|
|
#define AT91_DBG_C1R_SRAM_64K (0xb << 16)
|
2164 |
|
|
#define AT91_DBG_C1R_SRAM_128K (0xc << 16)
|
2165 |
|
|
#define AT91_DBG_C1R_SRAM_256K (0xd << 16)
|
2166 |
|
|
#define AT91_DBG_C1R_SRAM_96K (0xe << 16)
|
2167 |
|
|
#define AT91_DBG_C1R_SRAM_512K (0xf << 16)
|
2168 |
|
|
#define AT91_DBG_C1R_SRAM_MASK (0xf << 16)
|
2169 |
|
|
#define AT91_DBG_C1R_ARCH_AT75Cxx (0xf0 << 20)
|
2170 |
|
|
#define AT91_DBG_C1R_ARCH_AT91x40 (0x40 << 20)
|
2171 |
|
|
#define AT91_DBG_C1R_ARCH_AT91x63 (0x63 << 20)
|
2172 |
|
|
#define AT91_DBG_C1R_ARCH_AT91x55 (0x55 << 20)
|
2173 |
|
|
#define AT91_DBG_C1R_ARCH_AT91x42 (0x42 << 20)
|
2174 |
|
|
#define AT91_DBG_C1R_ARCH_AT91x92 (0x92 << 20)
|
2175 |
|
|
#define AT91_DBG_C1R_ARCH_AT91x34 (0x24 << 20)
|
2176 |
|
|
#define AT91_DBG_C1R_ARCH_AT91SAM7Axx (0x60 << 20)
|
2177 |
|
|
#define AT91_DBG_C1R_ARCH_AT91SAM7Sxx (0x70 << 20)
|
2178 |
|
|
#define AT91_DBG_C1R_ARCH_AT91SAM7XC (0x71 << 20)
|
2179 |
|
|
#define AT91_DBG_C1R_ARCH_AT91SAM7SExx (0x72 << 20)
|
2180 |
|
|
#define AT91_DBG_C1R_ARCH_AT91SAM7Lxx (0x73 << 20)
|
2181 |
|
|
#define AT91_DBG_C1R_ARCH_AT91SAM7Xxx (0x75 << 20)
|
2182 |
|
|
#define AT91_DBG_C1R_ARCH_AT91SAM9xx (0x19 << 20)
|
2183 |
|
|
#define AT91_DBG_C1R_ARCH_MASK (0xff << 20)
|
2184 |
|
|
#define AT91_DBG_C1R_NVPTYP_ROM (0 << 28) // ROM only
|
2185 |
|
|
#define AT91_DBG_C1R_NVPTYP_RLOCF (1 << 28) // ROMless of on chip Flash
|
2186 |
|
|
#define AT91_DBG_C1R_NVPTYP_SRAMROM (4 << 28) // SRAM emulating ROM
|
2187 |
|
|
#define AT91_DBG_C1R_NVPTYP_EFLASH (2 << 28) // Embedded Flash
|
2188 |
|
|
#define AT91_DBG_C1R_NVPTYP_ROMFLASH (3 << 28) // ROM & FLASH
|
2189 |
|
|
#define AT91_DBG_C1R_NVPTYP_MASK (7 << 28)
|
2190 |
|
|
#define AT91_DBG_C1R_EXT (1 << 31) // Extension Register Exists
|
2191 |
|
|
#define AT91_DBG_C2R 0x44 // Chip ID2 register
|
2192 |
|
|
#define AT91_DBG_FNTR 0x48 // Force NTRST Register
|
2193 |
|
|
#define AT91_DBG_RPR 0x100 // Receiver Pointer Register
|
2194 |
|
|
#define AT91_DBG_RCR 0x104 // Receiver Counter Register
|
2195 |
|
|
#define AT91_DBG_TPR 0x108 // Transmit Pointer Register
|
2196 |
|
|
#define AT91_DBG_TCR 0x10c // Transmit Counter Register
|
2197 |
|
|
#define AT91_DBG_RNPR 0x110 // Receiver Next Pointer Register
|
2198 |
|
|
#define AT91_DBG_RNCR 0x114 // Receiver Next Counter Register
|
2199 |
|
|
#define AT91_DBG_TNPR 0x118 // Transmit Next Pointer Register
|
2200 |
|
|
#define AT91_DBG_TNCR 0x11c // Transmit Next Counter Register
|
2201 |
|
|
#define AT91_DBG_PTCR 0x120 // PDC Transfer Control Register
|
2202 |
|
|
#define AT91_DBG_PTSR 0x124 // PDC Transfer Status Register
|
2203 |
|
|
#endif
|
2204 |
|
|
|
2205 |
|
|
//=============================================================================
|
2206 |
|
|
// Periodic Interval Timer Controller
|
2207 |
|
|
|
2208 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2209 |
|
|
|
2210 |
|
|
#ifndef AT91_PITC
|
2211 |
|
|
#define AT91_PITC 0xfffffd30
|
2212 |
|
|
#endif
|
2213 |
|
|
|
2214 |
|
|
#define AT91_PITC_PIMR 0x00 // Period Interval Mode Register
|
2215 |
|
|
#define AT91_PITC_PIMR_PITEN (1 << 24) // Periodic Interval Timer Enable
|
2216 |
|
|
#define AT91_PITC_PIMR_PITIEN (1 << 25) // Periodic Interval Timer Intr Enable
|
2217 |
|
|
#define AT91_PITC_PISR 0x04 // Period Interval Status Register
|
2218 |
|
|
#define AT91_PITC_PISR_PITS (1 << 0) // Periodic Interval Timer Status
|
2219 |
|
|
#define AT91_PITC_PIVR 0x08 // Period Interval Status Register
|
2220 |
|
|
#define AT91_PITC_PIIR 0x0C // Period Interval Image Register
|
2221 |
|
|
#define AT91_PITC_VALUE_MASK 0x000fffff // 20-bit period value
|
2222 |
|
|
#endif
|
2223 |
|
|
|
2224 |
|
|
//=============================================================================
|
2225 |
|
|
// Real Time Timer Controller
|
2226 |
|
|
|
2227 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2228 |
|
|
|
2229 |
|
|
#ifndef AT91_RTTC
|
2230 |
|
|
#define AT91_RTTC 0xFFFFFD20
|
2231 |
|
|
#endif
|
2232 |
|
|
|
2233 |
|
|
#define AT91_RTTC_RTMR 0x00 // Real Time Mode Register
|
2234 |
|
|
#define AT91_RTTC_RTMR_ALMIEN (1 << 16) // Alarm Interrupt Enable
|
2235 |
|
|
#define AT91_RTTC_RTMR_RTTINCIEN (1 << 17) // Timer Increment Interrupt Enable
|
2236 |
|
|
#define AT91_RTTC_RTMR_RTTRST (1 << 18) // Timer Reset
|
2237 |
|
|
#define AT91_RTTC_RTAR 0x04 // Real Time Alarm Register
|
2238 |
|
|
#define AT91_RTTC_RTVR 0x08 // Real Time Value Register
|
2239 |
|
|
#define AT91_RTTC_RTSR 0x0C // Real Time Status Register
|
2240 |
|
|
#define AT91_RTTC_RTSR_ALMS (1 << 0) // Alarm Status
|
2241 |
|
|
#define AT91_RTTC_RTSR_RTTINC (1 << 1) // Timer Increment
|
2242 |
|
|
#endif
|
2243 |
|
|
|
2244 |
|
|
//=============================================================================
|
2245 |
|
|
// USB Device Port
|
2246 |
|
|
|
2247 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2248 |
|
|
|
2249 |
|
|
#ifndef AT91_UDP
|
2250 |
|
|
#define AT91_UDP 0xFFFB0000
|
2251 |
|
|
#endif
|
2252 |
|
|
|
2253 |
|
|
#define AT91_UDP_FRM_NUM 0x00 // Frame Number
|
2254 |
|
|
#define AT91_UDP_FRM_ERR (1 << 16) // Frame Error
|
2255 |
|
|
#define AT91_UDP_FRM_OK (1 << 17) // Frame OK
|
2256 |
|
|
#define AT91_UDP_GLB_STATE 0x04 // Global State
|
2257 |
|
|
#define AT91_UDP_GLB_FADDEN (1 << 0) // Function Address Enable
|
2258 |
|
|
#define AT91_UDP_GLB_CONFG (1 << 1) // Configured
|
2259 |
|
|
#define AT91_UDP_GLB_ESR (1 << 2) // Enable Send Resume
|
2260 |
|
|
#define AT91_UDP_GLB_RSMINPR (1 << 3) // A Resume has been seen
|
2261 |
|
|
#define AT91_UDP_GLB_RMWUPE (1 << 4) // Remote Wake Up Enable
|
2262 |
|
|
#define AT91_UDP_FADDR 0x08 // Function Address
|
2263 |
|
|
#define AT91_UDP_FADDR_FEN (1 << 8) // Function Enable
|
2264 |
|
|
#define AT91_UDP_IER 0x10 // Interrupt Enable
|
2265 |
|
|
#define AT91_UDP_EPINT0 (1 << 0) // Endpoint 0 Interrupt
|
2266 |
|
|
#define AT91_UDP_EPINT1 (1 << 1) // Endpoint 1 Interrupt
|
2267 |
|
|
#define AT91_UDP_EPINT2 (1 << 2) // Endpoint 2 Interrupt
|
2268 |
|
|
#define AT91_UDP_EPINT3 (1 << 3) // Endpoint 3 Interrupt
|
2269 |
|
|
#define AT91_UDP_EPINT4 (1 << 4) // Endpoint 4 Interrupt
|
2270 |
|
|
#define AT91_UDP_EPINT5 (1 << 5) // Endpoint 5 Interrupt
|
2271 |
|
|
#define AT91_UDP_EPINT6 (1 << 6) // Endpoint 6 Interrupt
|
2272 |
|
|
#define AT91_UDP_EPINT7 (1 << 7) // Endpoint 7 Interrupt
|
2273 |
|
|
#define AT91_UDP_RXSUSP (1 << 8) // USB Suspend Interrupt
|
2274 |
|
|
#define AT91_UDP_RXRSM (1 << 9) // USB Resume Interrupt
|
2275 |
|
|
#define AT91_UDP_EXTRSM (1 << 10) // USB External Resume Interrupt
|
2276 |
|
|
#define AT91_UDP_SOFINT (1 << 11) // USB start of frame Interrupt
|
2277 |
|
|
#define AT91_UDP_ENDBUSRES (1 << 12) // USB End of Bus Reset Interrupt
|
2278 |
|
|
#define AT91_UDP_WAKEUP (1 << 13) // USB Resume Interrupt
|
2279 |
|
|
#define AT91_UDP_IDR 0x14 // Interrupt Disable
|
2280 |
|
|
#define AT91_UDP_IMR 0x18 // Interrupt Mask
|
2281 |
|
|
#define AT91_UDP_ISR 0x1C // Interrupt Status
|
2282 |
|
|
#define AT91_UDP_ICR 0x20 // Interrupt Clear
|
2283 |
|
|
#define AT91_UDP_RST_EP 0x28 // Reset Endpoint
|
2284 |
|
|
#define AT91_UDP_CSR 0x30 // Endpoint Control and Status
|
2285 |
|
|
#define AT91_UDP_CSR_TXCOMP (1 << 0) // Generates an IN packet
|
2286 |
|
|
#define AT91_UDP_CSR_RX_DATA_BK0 (1 << 1) // Receive Data Bank 0
|
2287 |
|
|
#define AT91_UDP_CSR_RXSETUP (1 << 2) // Sends a STALL to the host
|
2288 |
|
|
#define AT91_UDP_CSR_ISOERROR (1 << 3) // Isochronous error
|
2289 |
|
|
#define AT91_UDP_CSR_TXPKTRDY (1 << 4) // Transmit Packet Ready
|
2290 |
|
|
#define AT91_UDP_CSR_FORCESTALL (1 << 5) // Force Stall
|
2291 |
|
|
#define AT91_UDP_CSR_RX_DATA_BK1 (1 << 6) // Receive Data Bank 1
|
2292 |
|
|
#define AT91_UDP_CSR_DIR (1 << 7) // Transfer Direction
|
2293 |
|
|
#define AT91_UDP_CSR_DIR_OUT (0 << 7) // Transfer Direction OUT
|
2294 |
|
|
#define AT91_UDP_CSR_DIR_IN (1 << 7) // Transfer Direction IN
|
2295 |
|
|
#define AT91_UDP_CSR_EPTYPE_CTRL (0 << 8) // Control
|
2296 |
|
|
#define AT91_UDP_CSR_EPTYPE_ISO_OUT (1 << 8) // Isochronous OUT
|
2297 |
|
|
#define AT91_UDP_CSR_EPTYPE_BULK_OUT (2 << 8) // Bulk OUT
|
2298 |
|
|
#define AT91_UDP_CSR_EPTYPE_INT_OUT (3 << 8) // Interrupt OUT
|
2299 |
|
|
#define AT91_UDP_CSR_EPTYPE_ISO_IN (5 << 8) // Isochronous IN
|
2300 |
|
|
#define AT91_UDP_CSR_EPTYPE_BULK_IN (6 << 8) // Bulk IN
|
2301 |
|
|
#define AT91_UDP_CSR_EPTYPE_INT_IN (7 << 8) // Interrupt IN
|
2302 |
|
|
#define AT91_UDP_CSR_DTGLE (1 << 11) // Data Toggle
|
2303 |
|
|
#define AT91_UDP_CSR_EPEDS (1 << 15) // Endpoint Enable Disable
|
2304 |
|
|
#define AT91_UDP_FDR 0x50 // Endpoint FIFO Data
|
2305 |
|
|
#define AT91_UDP_TXVC 0x74 // Transceiver Control
|
2306 |
|
|
#define AT91_UDP_TXVC_TXVDIS (1 << 8) // Disable Transceiver
|
2307 |
|
|
#define AT91_UDP_TXVC_PUON (1 << 9) // Pull-up ON
|
2308 |
|
|
#endif
|
2309 |
|
|
|
2310 |
|
|
//=============================================================================
|
2311 |
|
|
// Synchronous Serial Controller (SSC)
|
2312 |
|
|
|
2313 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2314 |
|
|
|
2315 |
|
|
#ifndef AT91_SSC
|
2316 |
|
|
#define AT91_SSC 0xFFFD4000
|
2317 |
|
|
#endif
|
2318 |
|
|
|
2319 |
|
|
#define AT91_SSC_CR (0x00)
|
2320 |
|
|
#define AT91_SSC_CR_RXEN (1<<0) //Enable Receiver
|
2321 |
|
|
#define AT91_SSC_CR_RXDIS (1<<1) //Disable Receiver
|
2322 |
|
|
#define AT91_SSC_CR_TXEN (1<<8) //Enable Transmitter
|
2323 |
|
|
#define AT91_SSC_CR_TXDIS (1<<9) //Disable Transmitter
|
2324 |
|
|
#define AT91_SSC_CR_SWRST (1<<15) //Soft Reset
|
2325 |
|
|
#define AT91_SSC_CMR (0x04)
|
2326 |
|
|
#define AT91_SSC_RCMR (0x10)
|
2327 |
|
|
#define AT91_SSC_RCMR_CKS_DIV (0<<0) //Select Divider Clock
|
2328 |
|
|
#define AT91_SSC_RCMR_CKS_TX (1<<0) //Select Transmit Clock
|
2329 |
|
|
#define AT91_SSC_RCMR_CKS_RK (2<<0) //Select Receiver Clock
|
2330 |
|
|
#define AT91_SSC_RCMR_CKO_NONE (0<<2) //No Clock Output
|
2331 |
|
|
#define AT91_SSC_RCMR_CKO_CONT (1<<2) //Continuous Clock Output
|
2332 |
|
|
#define AT91_SSC_RCMR_CKO_TFER (2<<2) //Clock Output During Transfer only
|
2333 |
|
|
#define AT91_SSC_RCMR_CKI (1<<5) //Clock Invert
|
2334 |
|
|
#define AT91_SSC_RCMR_CKG_NONE (0<<6) //No Clock Gating, Continuous Clock
|
2335 |
|
|
#define AT91_SSC_RCMR_CKG_RFLOW (1<<6) //Clock Enabled by RF Low
|
2336 |
|
|
#define AT91_SSC_RCMR_CKG_RFHIGH (2<<6) //Clock Enabled by RF HIGH
|
2337 |
|
|
#define AT91_SSC_RCMR_START_CONT (0<<8) //Start when data in RHR, Continuous
|
2338 |
|
|
#define AT91_SSC_RCMR_START_TX (1<<8) //Start when TX Start
|
2339 |
|
|
#define AT91_SSC_RCMR_START_RFLOW (2<<8) //Start when LOW level on RF
|
2340 |
|
|
#define AT91_SSC_RCMR_START_RFHIGH (3<<8) //Start when HIGH level on RF
|
2341 |
|
|
#define AT91_SSC_RCMR_START_RFFALL (4<<8) //Start when Falling Edge on RF
|
2342 |
|
|
#define AT91_SSC_RCMR_START_RFRISE (5<<8) //Start when Rising Edge on RF
|
2343 |
|
|
#define AT91_SSC_RCMR_START_RFLEVEL (6<<8) //Start when any Level Change on RF
|
2344 |
|
|
#define AT91_SSC_RCMR_START_RFEDGE (7<<8) //Start when any Edge on RF
|
2345 |
|
|
#define AT91_SSC_RCMR_START_CMP0 (8<<8) //Start when Compare 0 match
|
2346 |
|
|
#define AT91_SSC_RCMR_STOP_CMP1 (1<<12) //Stop when Compare 1 Match
|
2347 |
|
|
#define AT91_SSC_RCMR_STTDLY(x) ((x&0xFF)<<16) //Start Delay
|
2348 |
|
|
#define AT91_SSC_RCMR_PERIOD(x) ((x&0xFF)<<24) //Frame Period
|
2349 |
|
|
#define AT91_SSC_RFMR (0x14)
|
2350 |
|
|
#define AT91_SSC_RFMR_DATLEN(x) (x&0x1F) //Data word length
|
2351 |
|
|
#define AT91_SSC_RFMR_LOOP (1<<5) //Loop Mode
|
2352 |
|
|
#define AT91_SSC_RFMR_MSBF (1<<7) //MSB First
|
2353 |
|
|
#define AT91_SSC_RFMR_DATNB(x) ((x&0xf)<<8) //Data Number, # words per frame
|
2354 |
|
|
#define AT91_SSC_RFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length
|
2355 |
|
|
#define AT91_SSC_RFMR_FSOS_NONE (0<<16) //No Frame Synch Output
|
2356 |
|
|
#define AT91_SSC_RFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Sync Output
|
2357 |
|
|
#define AT91_SSC_RFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Sync Output
|
2358 |
|
|
#define AT91_SSC_RFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output
|
2359 |
|
|
#define AT91_SSC_RFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output
|
2360 |
|
|
#define AT91_SSC_RFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output
|
2361 |
|
|
#define AT91_SSC_RFMR_FSEDGE_POS (0<<24) //Intr on +ve edge of Frame Sync
|
2362 |
|
|
#define AT91_SSC_RFMR_FSEDGE_NEG (1<<24) //Intr on -ve edge of Frame Sync
|
2363 |
|
|
#define AT91_SSC_TCMR (0x18)
|
2364 |
|
|
#define AT91_SSC_TCMR_CKS_DIV (0<<0) //Select Divider Clock
|
2365 |
|
|
#define AT91_SSC_TCMR_CKS_RX (1<<0) //Select Receiver Clock
|
2366 |
|
|
#define AT91_SSC_TCMR_CKS_TK (2<<0) //Select Transmit Clock
|
2367 |
|
|
#define AT91_SSC_TCMR_CKO_NONE (0<<2) //No Clock Output
|
2368 |
|
|
#define AT91_SSC_TCMR_CKO_CONT (1<<2) //Continuous Clock Output
|
2369 |
|
|
#define AT91_SSC_TCMR_CKO_TFER (2<<2) //Clock Output During Transfer only
|
2370 |
|
|
#define AT91_SSC_TCMR_CKI (1<<5) //Clock Invert
|
2371 |
|
|
#define AT91_SSC_TCMR_CKG_NONE (0<<6) //No Clock Gating, Continuous Clock
|
2372 |
|
|
#define AT91_SSC_TCMR_CKG_RFLOW (1<<6) //Clock Enabled by RF Low
|
2373 |
|
|
#define AT91_SSC_TCMR_CKG_RFHIGH (2<<6) //Clock Enabled by RF HIGH
|
2374 |
|
|
#define AT91_SSC_TCMR_START_CONT (0<<8) //Start when data in THR, Continuous
|
2375 |
|
|
#define AT91_SSC_TCMR_START_RX (1<<8) //Start when RX Start
|
2376 |
|
|
#define AT91_SSC_TCMR_START_TFLOW (2<<8) //Start when LOW level on TF
|
2377 |
|
|
#define AT91_SSC_TCMR_START_TFHIGH (3<<8) //Start when HIGH level on TF
|
2378 |
|
|
#define AT91_SSC_TCMR_START_TFFALL (4<<8) //Start when Falling Edge on TF
|
2379 |
|
|
#define AT91_SSC_TCMR_START_TFRISE (5<<8) //Start when Rising Edge on TF
|
2380 |
|
|
#define AT91_SSC_TCMR_START_TFLEVEL (6<<8) //Start when any Level Change on TF
|
2381 |
|
|
#define AT91_SSC_TCMR_START_TFEDGE (6<<8) //Start when any Edge on TF
|
2382 |
|
|
#define AT91_SSC_TCMR_STDDLY(x) ((x&0xFF)<<16) //Start Delay
|
2383 |
|
|
#define AT91_SSC_TCMR_PERIOD(x) ((x&0xFF)<<24) //Frame Period
|
2384 |
|
|
#define AT91_SSC_TFMR (0x1C)
|
2385 |
|
|
#define AT91_SSC_TFMR_DATLEN(x) (x&0x1F) //Data word length
|
2386 |
|
|
#define AT91_SSC_TFMR_DATDEF (1<<5) //Default Data is 1's
|
2387 |
|
|
#define AT91_SSC_TFMR_MSBF (1<<7) //MSB First
|
2388 |
|
|
#define AT91_SSC_TFMR_DATNB(x) ((x&0xf)<<8) //Data Number, # words per frame
|
2389 |
|
|
#define AT91_SSC_TFMR_FSLEN(x) ((x&0xf)<<16) //Frame sync length
|
2390 |
|
|
#define AT91_SSC_TFMR_FSOS_NONE (0<<16) //No Frame Synch Output
|
2391 |
|
|
#define AT91_SSC_TFMR_FSOS_NEGPULSE (1<<16) //Negative Pulse Frame Sync Output
|
2392 |
|
|
#define AT91_SSC_TFMR_FSOS_POSPULSE (2<<16) //Positive Pulse Frame Sync Output
|
2393 |
|
|
#define AT91_SSC_TFMR_FSOS_LOW (3<<16) //Low Level Frame Synch Output
|
2394 |
|
|
#define AT91_SSC_TFMR_FSOS_HIGH (4<<16) //High Level Frame Synch Output
|
2395 |
|
|
#define AT91_SSC_TFMR_FSOS_TOGGLE (5<<16) //Toggle Frame Synch Output
|
2396 |
|
|
#define AT91_SSC_TFMR_FSDEN_DEF (0<<23) //Frame Sync is Default Data
|
2397 |
|
|
#define AT91_SSC_TFMR_FSDEN_TSHR (1<<23) //Frame Sync is TSHR Data
|
2398 |
|
|
#define AT91_SSC_TFMR_FSEDGE_POS (0<<24) //Intr on +ve edge of Frame Sync
|
2399 |
|
|
#define AT91_SSC_TFMR_FSEDGE_NEG (1<<24) //Intr on -ve edge of Frame Sync
|
2400 |
|
|
#define AT91_SSC_RHR (0x20)
|
2401 |
|
|
#define AT91_SSC_THR (0x24)
|
2402 |
|
|
#define AT91_SSC_RSHR (0x30)
|
2403 |
|
|
#define AT91_SSC_TSHR (0x34)
|
2404 |
|
|
#define AT91_SSC_RC0R (0x38)
|
2405 |
|
|
#define AT91_SSC_RC1R (0x3C)
|
2406 |
|
|
#define AT91_SSC_SR (0x40)
|
2407 |
|
|
#define AT91_SSC_SR_TXRDY (1<<0) //Transmit Ready
|
2408 |
|
|
#define AT91_SSC_SR_TXEMPTY (1<<1) //Transmit Empty
|
2409 |
|
|
#define AT91_SSC_SR_ENDTX (1<<2) //End of Transmission
|
2410 |
|
|
#define AT91_SSC_SR_TXBUFE (1<<3) //Transmit Buffer Empty
|
2411 |
|
|
#define AT91_SSC_SR_RXRDY (1<<4) //Receiver Ready
|
2412 |
|
|
#define AT91_SSC_SR_OVRUN (1<<5) //Receiver Overrun
|
2413 |
|
|
#define AT91_SSC_SR_ENDRX (1<<6) //End of Reception
|
2414 |
|
|
#define AT91_SSC_SR_RXBUFF (1<<7) //Receive Buffer Full
|
2415 |
|
|
#define AT91_SSC_SR_CP0 (1<<8) //Compare 0 match
|
2416 |
|
|
#define AT91_SSC_SR_CP1 (1<<9) //Compare 1 Match
|
2417 |
|
|
#define AT91_SSC_SR_TXSYN (1<<10) //Transmit Frame Sync
|
2418 |
|
|
#define AT91_SSC_SR_RXSYN (1<<11) //Receive Frame Sync
|
2419 |
|
|
#define AT91_SSC_SR_TXEN (1<<16) //Transmitter Enabled
|
2420 |
|
|
#define AT91_SSC_SR_RXEN (1<<17) //Receiver Enabled
|
2421 |
|
|
#define AT91_SSC_IER (0x44)
|
2422 |
|
|
#define AT91_SSC_IDR (0x48)
|
2423 |
|
|
#define AT91_SSC_IMR (0x4C)
|
2424 |
|
|
|
2425 |
|
|
#define AT91_SSC_RPR 0x100 // Receiver Pointer Register
|
2426 |
|
|
#define AT91_SSC_RCR 0x104 // Receiver Counter Register
|
2427 |
|
|
#define AT91_SSC_TPR 0x108 // Transmit Pointer Register
|
2428 |
|
|
#define AT91_SSC_TCR 0x10c // Transmit Counter Register
|
2429 |
|
|
#define AT91_SSC_RNPR 0x110 // Receiver Next Pointer Register
|
2430 |
|
|
#define AT91_SSC_RNCR 0x114 // Receiver Next Counter Register
|
2431 |
|
|
#define AT91_SSC_TNPR 0x118 // Transmit Next Pointer Register
|
2432 |
|
|
#define AT91_SSC_TNCR 0x11c // Transmit Next Counter Register
|
2433 |
|
|
#define AT91_SSC_PTCR 0x120 // PDC Transfer Control Register
|
2434 |
|
|
#define AT91_SSC_PTSR 0x124 // PDC Transfer Status Register
|
2435 |
|
|
|
2436 |
|
|
#define AT91_SSC_PTCR_RXTEN (1 << 0) //Receive Transfers Enabled
|
2437 |
|
|
#define AT91_SSC_PTCR_RXTDIS (1 << 1) //Receive Transfers Disabled
|
2438 |
|
|
#define AT91_SSC_PTCR_TXTEN (1 << 8) //Transmit Transfers Enabled
|
2439 |
|
|
#define AT91_SSC_PTCR_TXTDIS (1 << 9) //Transmit Transfers Disabled
|
2440 |
|
|
|
2441 |
|
|
#endif
|
2442 |
|
|
|
2443 |
|
|
//=============================================================================
|
2444 |
|
|
// Ethernet Controller (EMAC)
|
2445 |
|
|
|
2446 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7X)
|
2447 |
|
|
|
2448 |
|
|
#ifndef AT91_EMAC
|
2449 |
|
|
#define AT91_EMAC 0xFFFBC000
|
2450 |
|
|
#endif
|
2451 |
|
|
|
2452 |
|
|
#define AT91_EMAC_NCR (0x00) // Network Control
|
2453 |
|
|
#define AT91_EMAC_NCR_LB (1 << 0) // Loopback
|
2454 |
|
|
#define AT91_EMAC_NCR_LBL (1 << 1) // Loopback Local
|
2455 |
|
|
#define AT91_EMAC_NCR_RE (1 << 2) // Receiver Enable
|
2456 |
|
|
#define AT91_EMAC_NCR_TX (1 << 3) // Transmit Enable
|
2457 |
|
|
#define AT91_EMAC_NCR_MPE (1 << 4) // Management Port Enable
|
2458 |
|
|
#define AT91_EMAC_NCR_CSR (1 << 5) // Clear Statistics Registers
|
2459 |
|
|
#define AT91_EMAC_NCR_ISR (1 << 6) // Increment Statistics Registers
|
2460 |
|
|
#define AT91_EMAC_NCR_WES (1 << 7) // Write Enable for Statistics Registers
|
2461 |
|
|
#define AT91_EMAC_NCR_BP (1 << 8) // Back Pressure
|
2462 |
|
|
#define AT91_EMAC_NCR_TSTART (1 << 9) // Start Transmitter
|
2463 |
|
|
#define AT91_EMAC_NCR_THALT (1 << 10) // Halt Transmitter
|
2464 |
|
|
|
2465 |
|
|
#define AT91_EMAC_NCFG (0x04) // Network Configuration
|
2466 |
|
|
#define AT91_EMAC_NCFG_SPD_10Mbps (0 << 0) // 10Mbps line speed
|
2467 |
|
|
#define AT91_EMAC_NCFG_SPD_100Mbps (1 << 0) // 100Mbps line speed
|
2468 |
|
|
#define AT91_EMAC_NCFG_FD (1 << 1) // Full Deplex
|
2469 |
|
|
#define AT91_EMAC_NCFG_BR (1 << 2) // Bit Rate
|
2470 |
|
|
#define AT91_EMAC_NCFG_CAF (1 << 4) // Copy All Frames
|
2471 |
|
|
#define AT91_EMAC_NCFG_NBC (1 << 5) // Don't receiver Broadcasts
|
2472 |
|
|
#define AT91_EMAC_NCFG_MTI (1 << 6) // Multicast Hash Enable
|
2473 |
|
|
#define AT91_EMAC_NCFG_UNI (1 << 7) // Unicast hash enable
|
2474 |
|
|
#define AT91_EMAC_NCFG_BIG (1 << 8) // Receive upto 1522 byte frames
|
2475 |
|
|
#define AT91_EMAC_NCFG_EAE (1 << 9) // External Address match Enable
|
2476 |
|
|
#define AT91_EMAC_NCFG_CLK_HCLK_8 (0 << 10) // HCLK divided by 8
|
2477 |
|
|
#define AT91_EMAC_NCFG_CLK_HCLK_16 (1 << 10) // HCLK divided by 16
|
2478 |
|
|
#define AT91_EMAC_NCFG_CLK_HCLK_32 (2 << 10) // HCLK divided by 32
|
2479 |
|
|
#define AT91_EMAC_NCFG_CLK_HCLK_64 (3 << 10) // HCLK divided by 64
|
2480 |
|
|
#define AT91_EMAC_NCFG_CLK_MASK (3 << 10) // HCLK mask
|
2481 |
|
|
#define AT91_EMAC_NCFG_CLK_RTY (1 << 12) // Retry Test
|
2482 |
|
|
#define AT91_EMAC_NCFG_CLK_RMII (1 << 13) // Enable RMII mode
|
2483 |
|
|
#define AT91_EMAC_NCFG_CLK_MII (0 << 13) // Enable MII mode
|
2484 |
|
|
#define AT91_EMAC_NCFG_RLCE (0 << 16) // Receive Length Check Enable
|
2485 |
|
|
|
2486 |
|
|
#define AT91_EMAC_NSR (0x08) // Network Status
|
2487 |
|
|
#define AT91_EMAC_NSR_MDIO_MASK (1 << 1) // MDIO Pin status
|
2488 |
|
|
#define AT91_EMAC_NSR_IDLE (1 << 2) // PHY logical is idle
|
2489 |
|
|
|
2490 |
|
|
#define AT91_EMAC_TSR (0x14) // Transmit Status
|
2491 |
|
|
#define AT91_EMAC_TSR_OVR (1 << 0) // Overrun
|
2492 |
|
|
#define AT91_EMAC_TSR_COL (1 << 1) // Collision occurred
|
2493 |
|
|
#define AT91_EMAC_TSR_RLE (1 << 2) // Retry Limit Exceeded
|
2494 |
|
|
#define AT91_EMAC_TSR_TXIDLE (1 << 3) // Transmitter Idle
|
2495 |
|
|
#define AT91_EMAC_TSR_BNQ (1 << 4) // Buffer Not Queues
|
2496 |
|
|
#define AT91_EMAC_TSR_COMP (1 << 5) // Transmission Complete
|
2497 |
|
|
#define AT91_EMAC_TSR_UND (1 << 6) // Transmit Underrun
|
2498 |
|
|
|
2499 |
|
|
#define AT91_EMAC_RBQP (0x18) // Receiver Buffer Queue Pointer
|
2500 |
|
|
#define AT91_EMAC_TBQP (0x1c) // Transmit Buffer Queue Pointer
|
2501 |
|
|
|
2502 |
|
|
#define AT91_EMAC_RSR (0x20) // Receiver Status
|
2503 |
|
|
#define AT91_EMAC_RSR_BNA (1 << 0) // Buffer Not Available
|
2504 |
|
|
#define AT91_EMAC_RSR_REC (1 << 1) // Frame Received
|
2505 |
|
|
#define AT91_EMAC_RSR_OVR (1 << 2) // Transmit Buffer Overrun
|
2506 |
|
|
|
2507 |
|
|
#define AT91_EMAC_ISR (0x24) // Interrupt Status
|
2508 |
|
|
#define AT91_EMAC_ISR_DONE (1 << 0) // Management Done
|
2509 |
|
|
#define AT91_EMAC_ISR_RCOM (1 << 1) // Receiver Complete
|
2510 |
|
|
#define AT91_EMAC_ISR_RBNA (1 << 2) // Receiver Buffer Not Available
|
2511 |
|
|
#define AT91_EMAC_ISR_TOVR (1 << 3) // Transmit Buffer Overrun
|
2512 |
|
|
#define AT91_EMAC_ISR_TUND (1 << 4) // Transmit Error: Buffer under run
|
2513 |
|
|
#define AT91_EMAC_ISR_RTRY (1 << 5) // Transmit Error: Retry Limit Exceeded
|
2514 |
|
|
#define AT91_EMAC_ISR_TBRE (1 << 6) // Transmit Buffer Register Empty
|
2515 |
|
|
#define AT91_EMAC_ISR_TCOM (1 << 7) // Transmit Complete
|
2516 |
|
|
#define AT91_EMAC_ISR_TIDLE (1 << 8) // Transmitter Idle
|
2517 |
|
|
#define AT91_EMAC_ISR_LINK (1 << 9) // Link pin changed state
|
2518 |
|
|
#define AT91_EMAC_ISR_ROVR (1 << 10) // Receiver Overrun
|
2519 |
|
|
#define AT91_EMAC_ISR_HRESP (1 << 11) // HRESP not OK
|
2520 |
|
|
#define AT91_EMAC_IER (0x28) // Interrupt Enable
|
2521 |
|
|
#define AT91_EMAC_IDR (0x2c) // Interrupt Disable
|
2522 |
|
|
#define AT91_EMAC_IMR (0x30) // Interrupt Mask
|
2523 |
|
|
|
2524 |
|
|
#define AT91_EMAC_MAN (0x34) // PHY Maintenance
|
2525 |
|
|
#define AT91_EMAC_MAN_DATA_MASK (0xffff<<0) // Data to/from PHY
|
2526 |
|
|
#define AT91_EMAC_MAN_CODE (2<<16) // Code
|
2527 |
|
|
#define AT91_EMAC_MAN_REGA_MASK (0x1f<<18) // Register Address Mask
|
2528 |
|
|
#define AT91_EMAC_MAN_REGA_SHIFT (18) // Register Address Shift
|
2529 |
|
|
#define AT91_EMAC_MAN_PHY_MASK (0x1f<<23) // PHY Address Mask
|
2530 |
|
|
#define AT91_EMAC_MAN_PHY_SHIFT (23) // PHY Address Shift
|
2531 |
|
|
#define AT91_EMAC_MAN_RD (2<<28) // Read operation
|
2532 |
|
|
#define AT91_EMAC_MAN_WR (1<<28) // Write Operation
|
2533 |
|
|
#define AT91_EMAC_MAN_SOF (1<<30) // Must be set to 01
|
2534 |
|
|
#define AT91_EMAC_MAN_PHYA(x) ((x&0x1f)<<23) // Create a PHY Address
|
2535 |
|
|
#define AT91_EMAC_MAN_REGA(x) ((x&0x1f)<<18) // Create a Register Address
|
2536 |
|
|
#define AT91_EMAC_MAN_DATA(x) (x&0xffff) // Create a Data word
|
2537 |
|
|
|
2538 |
|
|
|
2539 |
|
|
#define AT91_EMAC_PTR (0x38) // Pause Time Register
|
2540 |
|
|
#define AT91_EMAC_PFR (0x3C) // Pause Frames Received
|
2541 |
|
|
#define AT91_EMAC_FTO (0x40) // Frames Transmitted OK
|
2542 |
|
|
#define AT91_EMAC_SCF (0x44) // Single Collision Frame
|
2543 |
|
|
#define AT91_EMAC_MCF (0x48) // Multiple Collision Frame
|
2544 |
|
|
#define AT91_EMAC_FRO (0x4c) // Frames Received OK
|
2545 |
|
|
#define AT91_EMAC_FCSE (0x50) // Frame Check Sequence Error
|
2546 |
|
|
#define AT91_EMAC_ALE (0x54) // Alignment Error
|
2547 |
|
|
#define AT91_EMAC_DTR (0x58) // Deferred Transmission Frame
|
2548 |
|
|
#define AT91_EMAC_LCOL (0x5c) // Late Collision
|
2549 |
|
|
#define AT91_EMAC_XCOL (0x60) // Excessive Collisions - ECOL!!
|
2550 |
|
|
#define AT91_EMAC_TUND (0x64) // Transmit Underrun Error
|
2551 |
|
|
#define AT91_EMAC_CSE (0x68) // Carrier Sense Error
|
2552 |
|
|
#define AT91_EMAC_RRE (0x6c) // Receive Resource Errors
|
2553 |
|
|
#define AT91_EMAC_ROV (0x70) // Receive Overrun
|
2554 |
|
|
#define AT91_EMAC_RSE (0x74) // Receiver Symbol erros
|
2555 |
|
|
#define AT91_EMAC_ELE (0x78) // Excessive Length Errors
|
2556 |
|
|
#define AT91_EMAC_RJE (0x7c) // Receive Jabber Errors
|
2557 |
|
|
#define AT91_EMAC_USF (0x80) // Undersize Frame Errors
|
2558 |
|
|
#define AT91_EMAC_STE (0x84) // SQE Test Errors
|
2559 |
|
|
#define AT91_EMAC_RLE (0x88) // Receive Length Field Mismatch
|
2560 |
|
|
|
2561 |
|
|
#define AT91_EMAC_HRB (0x90) // Hash Address Low [31:0]
|
2562 |
|
|
#define AT91_EMAC_HRT (0x94) // Hash Address High [63:32]
|
2563 |
|
|
#define AT91_EMAC_SA1L (0x98) // Specific Address 1 Low, First 4 bytes
|
2564 |
|
|
#define AT91_EMAC_SA1H (0x9c) // Specific Address 1 High, Last 2 bytes
|
2565 |
|
|
#define AT91_EMAC_SA2L (0xa0) // Specific Address 2 Low, First 4 bytes
|
2566 |
|
|
#define AT91_EMAC_SA2H (0xa4) // Specific Address 2 High, Last 2 bytes
|
2567 |
|
|
#define AT91_EMAC_SA3L (0xa8) // Specific Address 3 Low, First 4 bytes
|
2568 |
|
|
#define AT91_EMAC_SA3H (0xac) // Specific Address 3 High, Last 2 bytes
|
2569 |
|
|
#define AT91_EMAC_SA4L (0xb0) // Specific Address 4 Low, First 4 bytes
|
2570 |
|
|
#define AT91_EMAC_SA4H (0xb4) // Specific Address 4 High, Last 2 bytes
|
2571 |
|
|
#define AT91_EMAC_TID (0xb8) // Type ID Checking Register
|
2572 |
|
|
|
2573 |
|
|
#define AT91_EMAC_USRIO (0xc0) // User IO Register
|
2574 |
|
|
#define AT91_EMAC_USRIO_RMII (1<<0) // RMII Mode
|
2575 |
|
|
#define AT91_EMAC_USRIO_CLKEN (1<<1) // Clock Enable
|
2576 |
|
|
|
2577 |
|
|
// Receiver Buffer Descriptor
|
2578 |
|
|
#define AT91_EMAC_RBD_ADDR 0x0 // Address to beginning of buffer
|
2579 |
|
|
#define AT91_EMAC_RBD_ADDR_MASK (0xFFFFFFFC) // Address Mask masking the reserved bits
|
2580 |
|
|
#define AT91_EMAC_RBD_ADDR_OWNER_EMAC (0 << 0) // EMAC owns receiver buffer
|
2581 |
|
|
#define AT91_EMAC_RBD_ADDR_OWNER_SW (1 << 0) // SW owns receiver buffer
|
2582 |
|
|
#define AT91_EMAC_RBD_ADDR_WRAP (1 << 1) // Last receiver buffer
|
2583 |
|
|
#define AT91_EMAC_RBD_SR 0x1 // Buffer Status
|
2584 |
|
|
#define AT91_EMAC_RBD_SR_LEN_MASK (0xfff) // Length of data
|
2585 |
|
|
#define AT91_EMAC_RBD_SR_SOF (1 << 14) // Start of Frame
|
2586 |
|
|
#define AT91_EMAC_RBD_SR_EOF (1 << 15) // End of Frame
|
2587 |
|
|
#define AT91_EMAC_RBD_SR_CFI (1 << 16) // Concatination Format Ind
|
2588 |
|
|
#define AT91_EMAC_RDB_SR_VLAN_SHIFT (17) // VLAN priority tag
|
2589 |
|
|
#define AT91_EMAC_RDB_SR_VLAN_MASK (7 << 17)
|
2590 |
|
|
#define AT91_EMAC_RDB_SR_PRIORTY_TAG (1 << 20) // Priority Tag Detected
|
2591 |
|
|
#define AT91_EMAC_RDB_SR_VLAN_TAG (1 << 21) // Priority Tag Detected
|
2592 |
|
|
#define AT91_EMAC_RBD_SR_TYPE_ID (1 << 22) // Type ID match
|
2593 |
|
|
#define AT91_EMAC_RBD_SR_SA4M (1 << 23) // Specific Address 4 match
|
2594 |
|
|
#define AT91_EMAC_RBD_SR_SA3M (1 << 24) // Specific Address 3 match
|
2595 |
|
|
#define AT91_EMAC_RBD_SR_SA2M (1 << 25) // Specific Address 2 match
|
2596 |
|
|
#define AT91_EMAC_RBD_SR_SA1M (1 << 26) // Specific Address 1 match
|
2597 |
|
|
#define AT91_EMAC_RBD_SR_EXTNM (1 << 28) // External Address match
|
2598 |
|
|
#define AT91_EMAC_RBD_SR_UNICAST (1 << 29) // Unicast hash match
|
2599 |
|
|
#define AT91_EMAC_RBD_SR_MULTICAST (1 << 30) // Multicast hash match
|
2600 |
|
|
#define AT91_EMAC_RBD_SR_BROADCAST (1 << 31) // Broadcast
|
2601 |
|
|
|
2602 |
|
|
// Transmit Buffer Descriptor
|
2603 |
|
|
#define AT91_EMAC_TBD_ADDR 0x0 // Address to beginning of buffer
|
2604 |
|
|
#define AT91_EMAC_TBD_SR 0x1 // Buffer Status
|
2605 |
|
|
#define AT91_EMAC_TBD_SR_LEN_MASK (0xfff) // Length of data
|
2606 |
|
|
#define AT91_EMAC_TBD_SR_EOF (1 << 15) // End of Frame
|
2607 |
|
|
#define AT91_EMAC_TBD_SR_NCRC (1 << 16) // No CRC added by EMAC
|
2608 |
|
|
#define AT91_EMAC_TBD_SR_EXHAUST (1 << 27) // Buffers exhausted
|
2609 |
|
|
#define AT91_EMAC_TBD_SR_TXUNDER (1 << 28) // Transmit Underrun
|
2610 |
|
|
#define AT91_EMAC_TBD_SR_RTRY (1 << 29) // Retry limit exceeded
|
2611 |
|
|
#define AT91_EMAC_TBD_SR_WRAP (1 << 30) // Marks last descriptor
|
2612 |
|
|
#define AT91_EMAC_TBD_SR_USED (1 << 31) // Buffer used
|
2613 |
|
|
|
2614 |
|
|
#endif
|
2615 |
|
|
|
2616 |
|
|
//=============================================================================
|
2617 |
|
|
// Two Wire Interface (TWI)
|
2618 |
|
|
|
2619 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2620 |
|
|
|
2621 |
|
|
#ifndef AT91_TWI
|
2622 |
|
|
#define AT91_TWI 0xFFFB8000
|
2623 |
|
|
#endif
|
2624 |
|
|
|
2625 |
|
|
#define AT91_TWI_CR 0x00 // Control
|
2626 |
|
|
#define AT91_TWI_CR_START (1 << 0) // Send a Start
|
2627 |
|
|
#define AT91_TWI_CR_STOP (1 << 1) // Send a Stop
|
2628 |
|
|
#define AT91_TWI_CR_MSEN (1 << 2) // Master Transfer Enable
|
2629 |
|
|
#define AT91_TWI_CR_MSDIS (1 << 3) // Master Transfer Disable
|
2630 |
|
|
#define AT91_TWI_CR_SVEN (1 << 4) // Slave Transfer Enable
|
2631 |
|
|
#define AT91_TWI_CR_SDIS (1 << 5) // Slave Transfer Disable
|
2632 |
|
|
#define AT91_TWI_CR_SWRST (1 << 7) // Software Reset
|
2633 |
|
|
#define AT91_TWI_MMR 0x04 // Master Mode
|
2634 |
|
|
#define AT91_TWI_MMR_IADRZ_NO (0 << 8) // Internal Device Address size 0Bytes
|
2635 |
|
|
#define AT91_TWI_MMR_IADRZ_1 (1 << 8) // Internal Device Address size 1Byte
|
2636 |
|
|
#define AT91_TWI_MMR_IADRZ_2 (2 << 8) // Internal Device Address size 2Bytes
|
2637 |
|
|
#define AT91_TWI_MMR_IADRZ_3 (3 << 8) // Internal Device Address size 3Bytes
|
2638 |
|
|
#define AT91_TWI_MMR_MWRITE (0 << 12) // Master Write
|
2639 |
|
|
#define AT91_TWI_MMR_MREAD (1 << 12) // Master Read
|
2640 |
|
|
#define AT91_TWI_MMR_DADR_MASK (0x3f << 16) // Device Address Mask
|
2641 |
|
|
#define AT91_TWI_MMR_DADR_SHIFT (16) // Device Address Shift
|
2642 |
|
|
#define AT91_TWI_SMR 0x08 // Slave Mode
|
2643 |
|
|
#define AT91_TWI_SMR_SADR_MASK (0x3f << 16) // Slave Device Address Mask
|
2644 |
|
|
#define AT91_TWI_SMR_SADR_SHIFT (16) // Slave Device Address Shift
|
2645 |
|
|
#define AT91_TWI_IADR 0x0C // Internal Address
|
2646 |
|
|
#define AT91_TWI_CWGR 0x10 // Clock Waveform Generator
|
2647 |
|
|
#define AT91_TWI_CWGR_CLDIV_MASK (0xf << 0) // Clock Low Divider Mask
|
2648 |
|
|
#define AT91_TWI_CWGR_CLDIV_SHIFT (0) // Clock Low Divider Shift
|
2649 |
|
|
#define AT91_TWI_CWGR_CHDIV_MASK (0xf << 8) // Clock High Divider Mask
|
2650 |
|
|
#define AT91_TWI_CWGR_CHDIV_SHIFT (8) // Clock High Divider Shift
|
2651 |
|
|
#define AT91_TWI_CWGR_CKDIV_MASK (0x7 << 16) // Clock Divider Mask
|
2652 |
|
|
#define AT91_TWI_CWGR_CKDIV_SHIFT (16) // Clock Divider Shift
|
2653 |
|
|
#define AT91_TWI_SR 0x20 // Status
|
2654 |
|
|
#define AT91_TWI_SR_TXCOMP (1 << 0) // Transmission Completed
|
2655 |
|
|
#define AT91_TWI_SR_RXRDY (1 << 1) // Receiver Holding Register Ready
|
2656 |
|
|
#define AT91_TWI_SR_TXRDY (1 << 2) // Transmit Holding Register Ready
|
2657 |
|
|
#define AT91_TWI_SR_SVREAD (1 << 3) // Slave Read
|
2658 |
|
|
#define AT91_TWI_SR_SVACC (1 << 4) // Slave Access
|
2659 |
|
|
#define AT91_TWI_SR_GCACC (1 << 5) // General Call Access
|
2660 |
|
|
#define AT91_TWI_SR_OVRE (1 << 6) // Overrun Error
|
2661 |
|
|
#define AT91_TWI_SR_UNRE (1 << 7) // Underrun Error
|
2662 |
|
|
#define AT91_TWI_SR_NACK (1 << 8) // Not Acknowledged
|
2663 |
|
|
#define AT91_TWI_SR_ARBLST (1 << 9) // Arbitration Lost
|
2664 |
|
|
#define AT91_TWI_IER 0x24 // Interrupt Enable
|
2665 |
|
|
#define AT91_TWI_IDR 0x28 // Interrupt Disable
|
2666 |
|
|
#define AT91_TWI_IMR 0x2C // Interrupt Mask
|
2667 |
|
|
#define AT91_TWI_RHR 0x30 // Receiver Holding
|
2668 |
|
|
#define AT91_TWI_THR 0x34 // Transmit Holding
|
2669 |
|
|
#endif
|
2670 |
|
|
|
2671 |
|
|
//=============================================================================
|
2672 |
|
|
// Analog to Digital Convertor (ADC)
|
2673 |
|
|
|
2674 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7) || \
|
2675 |
|
|
defined (CYGHWR_HAL_ARM_AT91_M55800A)
|
2676 |
|
|
|
2677 |
|
|
// AT91SAM7 specifics
|
2678 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2679 |
|
|
#if !defined(AT91_ADC)
|
2680 |
|
|
#define AT91_ADC 0xFFFD8000
|
2681 |
|
|
#endif
|
2682 |
|
|
|
2683 |
|
|
#if !defined(AT91_MAX_ADC_CHAN)
|
2684 |
|
|
#define AT91_MAX_ADC_CHAN 8
|
2685 |
|
|
#endif
|
2686 |
|
|
#endif
|
2687 |
|
|
|
2688 |
|
|
// AT91_M55800A specifics
|
2689 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91_M55800A)
|
2690 |
|
|
#if !defined(AT91_ADC)
|
2691 |
|
|
#define AT91_ADC 0xFFFB0000
|
2692 |
|
|
#endif
|
2693 |
|
|
|
2694 |
|
|
#if !defined(AT91_ADC1)
|
2695 |
|
|
#define AT91_ADC1 0xFFFB4000
|
2696 |
|
|
#endif
|
2697 |
|
|
|
2698 |
|
|
#if !defined(AT91_MAX_ADC_CHAN)
|
2699 |
|
|
#define AT91_MAX_ADC_CHAN 4
|
2700 |
|
|
#endif
|
2701 |
|
|
#endif
|
2702 |
|
|
|
2703 |
|
|
#define AT91_ADC_CR 0x00 // Control
|
2704 |
|
|
#define AT91_ADC_CR_SWRST (1 << 0) // Software Reset
|
2705 |
|
|
#define AT91_ADC_CR_START (1 << 1) // Start Conversion
|
2706 |
|
|
#define AT91_ADC_MR 0x04 // Mode
|
2707 |
|
|
#define AT91_ADC_MR_TRGEN (1 << 0) // Trigger Enable
|
2708 |
|
|
#define AT91_ADC_MR_TRGSEL_TIOA0 (0 << 1) // Trigger = TIAO0
|
2709 |
|
|
#define AT91_ADC_MR_TRGSEL_TIOA1 (1 << 1) // Trigger = TIAO1
|
2710 |
|
|
#define AT91_ADC_MR_TRGSEL_TIOA2 (2 << 1) // Trigger = TIAO2
|
2711 |
|
|
#define AT91_ADC_MR_TRGSEL_TIOA3 (3 << 1) // Trigger = TIAO3
|
2712 |
|
|
#define AT91_ADC_MR_TRGSEL_TIOA4 (4 << 1) // Trigger = TIAO4
|
2713 |
|
|
#define AT91_ADC_MR_TRGSEL_TIOA5 (5 << 1) // Trigger = TIAO5
|
2714 |
|
|
#define AT91_ADC_MR_TRGSEL_EXT (6 << 1) // Trigger = External
|
2715 |
|
|
#define AT91_ADC_MR_LOWREC_10BITS (0 << 4) // 10-bit Resolution
|
2716 |
|
|
#define AT91_ADC_MR_LOWRES_8BITS (1 << 4) // 8-bit resolution
|
2717 |
|
|
#define AT91_ADC_MR_SLEEP_ON (1 << 5) // Sleep mode on
|
2718 |
|
|
#define AT91_ADC_MR_SLEEP_OFF (0 << 5) // Sleep mode off
|
2719 |
|
|
#define AT91_ADC_MR_PRESCAL_MASK (0x3f << 8) // Prescale Mask
|
2720 |
|
|
#define AT91_ADC_MR_PRESCAL_SHIFT (8) // Prescale Shift
|
2721 |
|
|
#define AT91_ADC_MR_STARTUP_MASK (0x0f << 16) // Startup Time Mask
|
2722 |
|
|
#define AT91_ADC_MR_STARTUP_SHIFT (16) // Startup Time Mask
|
2723 |
|
|
#define AT91_ADC_MR_SHTIM_MASK (0x0f << 24) // Sample & Hold Time Mask
|
2724 |
|
|
#define AT91_ADC_MR_SHTIM_SHIFT (24) // Sample & Hold Time Shift
|
2725 |
|
|
#define AT91_ADC_CHER 0x10 // Channel Enable
|
2726 |
|
|
#define AT91_ADC_CHER_CH0 (1 << 0) // Channel 0
|
2727 |
|
|
#define AT91_ADC_CHER_CH1 (1 << 1) // Channel 1
|
2728 |
|
|
#define AT91_ADC_CHER_CH2 (1 << 2) // Channel 2
|
2729 |
|
|
#define AT91_ADC_CHER_CH3 (1 << 3) // Channel 3
|
2730 |
|
|
#define AT91_ADC_CHER_CH4 (1 << 4) // Channel 4
|
2731 |
|
|
#define AT91_ADC_CHER_CH5 (1 << 5) // Channel 5
|
2732 |
|
|
#define AT91_ADC_CHER_CH6 (1 << 6) // Channel 6
|
2733 |
|
|
#define AT91_ADC_CHER_CH7 (1 << 7) // Channel 7
|
2734 |
|
|
#define AT91_ADC_CHDR 0x14 // Channel Disable
|
2735 |
|
|
#define AT91_ADC_CHSR 0x18 // Channel Status
|
2736 |
|
|
#define AT91_ADC_SR 0x1c // Status
|
2737 |
|
|
#define AT91_ADC_CHSR_EOC0 (1 << 0) // Channel 0 End of Conversion
|
2738 |
|
|
#define AT91_ADC_CHSR_EOC1 (1 << 1) // Channel 1 End of Conversion
|
2739 |
|
|
#define AT91_ADC_CHSR_EOC2 (1 << 2) // Channel 2 End of Conversion
|
2740 |
|
|
#define AT91_ADC_CHSR_EOC3 (1 << 3) // Channel 3 End of Conversion
|
2741 |
|
|
#define AT91_ADC_CHSR_EOC4 (1 << 4) // Channel 4 End of Conversion
|
2742 |
|
|
#define AT91_ADC_CHSR_EOC5 (1 << 5) // Channel 5 End of Conversion
|
2743 |
|
|
#define AT91_ADC_CHSR_EOC6 (1 << 6) // Channel 6 End of Conversion
|
2744 |
|
|
#define AT91_ADC_CHSR_EOC7 (1 << 7) // Channel 7 End of Conversion
|
2745 |
|
|
#define AT91_ADC_CHSR_OVRE0 (1 << 8) // Channel 0 Overrun Error
|
2746 |
|
|
#define AT91_ADC_CHSR_OVRE1 (1 << 9) // Channel 1 Overrun Error
|
2747 |
|
|
#define AT91_ADC_CHSR_OVRE2 (1 << 10) // Channel 2 Overrun Error
|
2748 |
|
|
#define AT91_ADC_CHSR_OVRE3 (1 << 11) // Channel 3 Overrun Error
|
2749 |
|
|
#define AT91_ADC_CHSR_OVRE4 (1 << 12) // Channel 4 Overrun Error
|
2750 |
|
|
#define AT91_ADC_CHSR_OVRE5 (1 << 13) // Channel 5 Overrun Error
|
2751 |
|
|
#define AT91_ADC_CHSR_OVRE6 (1 << 14) // Channel 6 Overrun Error
|
2752 |
|
|
#define AT91_ADC_CHSR_OVRE7 (1 << 15) // Channel 7 Overrun Error
|
2753 |
|
|
#define AT91_ADC_CHSR_DRDY (1 << 16) // Data Ready
|
2754 |
|
|
#define AT91_ADC_CHSR_GOVER (1 << 17) // General Overrun
|
2755 |
|
|
#define AT91_ADC_CHSR_EDNRX (1 << 18) // End of Receiver Transfer
|
2756 |
|
|
#define AT91_ADC_CHSR_RXBUFF (1 << 19) // RXBUFFER Interrupt
|
2757 |
|
|
#define AT91_ADC_LCDR 0x20 // Last Converted Data
|
2758 |
|
|
#define AT91_ADC_IER 0x24 // Interrupt Enable
|
2759 |
|
|
#define AT91_ADC_IDR 0x28 // Interrupt Disable
|
2760 |
|
|
#define AT91_ADC_IMR 0x2c // Interrupt Mask
|
2761 |
|
|
#define AT91_ADC_CDR0 0x30 // Channel Data 0
|
2762 |
|
|
#define AT91_ADC_CDR1 0x34 // Channel Data 1
|
2763 |
|
|
#define AT91_ADC_CDR2 0x38 // Channel Data 2
|
2764 |
|
|
#define AT91_ADC_CDR3 0x3c // Channel Data 3
|
2765 |
|
|
#define AT91_ADC_CDR4 0x40 // Channel Data 4
|
2766 |
|
|
#define AT91_ADC_CDR5 0x44 // Channel Data 5
|
2767 |
|
|
#define AT91_ADC_CDR6 0x48 // Channel Data 6
|
2768 |
|
|
#define AT91_ADC_CDR7 0x4c // Channel Data 7
|
2769 |
|
|
#define AT91_ADC_RPR 0x100 // Receive Pointer
|
2770 |
|
|
#define AT91_ADC_RCR 0x104 // Receive Counter
|
2771 |
|
|
#define AT91_ADC_TPR 0x108 // Transmit Pointer
|
2772 |
|
|
#define AT91_ADC_TCR 0x10C // Transmit Counter
|
2773 |
|
|
#define AT91_ADC_RNPR 0x110 // Receive Next Pointer
|
2774 |
|
|
#define AT91_ADC_RNCR 0x114 // Receive Next Counter
|
2775 |
|
|
#define AT91_ADC_TNPR 0x118 // Transmit Next Pointer
|
2776 |
|
|
#define AT91_ADC_TNCR 0x11C // Transmit Next Counter
|
2777 |
|
|
#define AT91_ADC_PTCR 0x120 // PDC Transfer Control
|
2778 |
|
|
#define AT91_ADC_PTCR_RXTEN (1 << 0) //Receive Transfers Enabled
|
2779 |
|
|
#define AT91_ADC_PTCR_RXTDIS (1 << 1) //Receive Transfers Disabled
|
2780 |
|
|
#define AT91_ADC_PTCR_TXTEN (1 << 8) //Receive Transfers Enabled
|
2781 |
|
|
#define AT91_ADC_PTCR_TXTDIS (1 << 9) //Receive Transfers Disabled
|
2782 |
|
|
|
2783 |
|
|
#define AT91_ADC_PTSR 0x124 // PDC Transfer Status
|
2784 |
|
|
|
2785 |
|
|
#endif
|
2786 |
|
|
|
2787 |
|
|
//=============================================================================
|
2788 |
|
|
// Controller Area Network (CAN)
|
2789 |
|
|
|
2790 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7X)
|
2791 |
|
|
|
2792 |
|
|
#ifndef AT91_CAN
|
2793 |
|
|
#define AT91_CAN 0xFFFD8000
|
2794 |
|
|
#endif
|
2795 |
|
|
|
2796 |
|
|
#define AT91_CAN_MR 0x000 // Mode
|
2797 |
|
|
#define AT91_CAN_MR_CANEN (1 << 0) // Enable
|
2798 |
|
|
#define AT91_CAN_MR_LPM (1 << 1) // Enable Low Power Mode
|
2799 |
|
|
#define AT91_CAN_MR_ABM (1 << 2) // Enable Autobaud/Listen mode
|
2800 |
|
|
#define AT91_CAN_MR_OVL (1 << 3) // Enable Overload Frame
|
2801 |
|
|
#define AT91_CAN_MR_TEOF (1 << 4) // Timestamp at End Of Trame
|
2802 |
|
|
#define AT91_CAN_MR_TTM (1 << 5) // Enable Time Triggered Mode
|
2803 |
|
|
#define AT91_CAN_MR_TIMFRZ (1 << 6) // Enable Timer Freeze
|
2804 |
|
|
#define AT91_CAN_MR_DRPT (1 << 7) // Disable Repeat
|
2805 |
|
|
#define AT91_CAN_IER 0x004 // Interrupt Enable
|
2806 |
|
|
#define AT91_CAM_IER_MB0 (1 << 0) // Mailbox 0
|
2807 |
|
|
#define AT91_CAM_IER_MB1 (1 << 1) // Mailbox 1
|
2808 |
|
|
#define AT91_CAM_IER_MB2 (1 << 2) // Mailbox 2
|
2809 |
|
|
#define AT91_CAM_IER_MB3 (1 << 3) // Mailbox 3
|
2810 |
|
|
#define AT91_CAM_IER_MB4 (1 << 4) // Mailbox 4
|
2811 |
|
|
#define AT91_CAM_IER_MB5 (1 << 5) // Mailbox 5
|
2812 |
|
|
#define AT91_CAM_IER_MB6 (1 << 6) // Mailbox 6
|
2813 |
|
|
#define AT91_CAM_IER_MB7 (1 << 7) // Mailbox 7
|
2814 |
|
|
#define AT91_CAM_IER_ERRA (1 << 16) // Error Active Mode
|
2815 |
|
|
#define AT91_CAM_IER_WARN (1 << 17) // Warning Limit
|
2816 |
|
|
#define AT91_CAM_IER_ERRO (1 << 18) // Error Passive Mode
|
2817 |
|
|
#define AT91_CAM_IER_BOFF (1 << 19) // Bus-Off Mode
|
2818 |
|
|
#define AT91_CAM_IER_SLEEP (1 << 20) // Sleep
|
2819 |
|
|
#define AT91_CAM_IER_WAKEUP (1 << 21) // Wakeup
|
2820 |
|
|
#define AT91_CAM_IER_TOVF (1 << 22) // Timer Overflow
|
2821 |
|
|
#define AT91_CAM_IER_TSTP (1 << 23) // TimeStamp
|
2822 |
|
|
#define AT91_CAM_IER_CERR (1 << 24) // CRC Error
|
2823 |
|
|
#define AT91_CAM_IER_SERR (1 << 25) // Stuffing Error
|
2824 |
|
|
#define AT91_CAM_IER_AERR (1 << 26) // Acknowledgement Error
|
2825 |
|
|
#define AT91_CAM_IER_FERR (1 << 27) // Form Error
|
2826 |
|
|
#define AT91_CAM_IER_BERR (1 << 28) // Bit Error
|
2827 |
|
|
#define AT91_CAN_IDR 0x008 // Interrupt Disable
|
2828 |
|
|
#define AT91_CAN_IMR 0x00C // Interrupt Mask
|
2829 |
|
|
#define AT91_CAN_SR 0x010 // Status
|
2830 |
|
|
#define AT91_CAN_SR_RBSY (1 << 29) // Receiver busy
|
2831 |
|
|
#define AT91_CAM_SR_TBSY (1 << 30) // Transmitter busy
|
2832 |
|
|
#define AT91_CAM_IER_OVLSY (1 << 31) // Overload Busy
|
2833 |
|
|
#define AT91_CAN_BR 0x014 // Baudrate
|
2834 |
|
|
#define AT91_CAN_BR_PHASE1_MASK (0x7 << 4) // Phase 1 Segment mask
|
2835 |
|
|
#define AT91_CAN_BR_PHASE1_SHIFT (4) // Phase 1 Segment shift
|
2836 |
|
|
#define AT91_CAN_BR_PHASE2_MASK (0x7 << 0) // Phase 2 Segment mask
|
2837 |
|
|
#define AT91_CAN_BR_PHASE2_SHIFT (0) // Phase 2 Segment shift
|
2838 |
|
|
#define AT91_CAN_BR_PROPAG_MASK (0x7 << 8) // Programming Time Segment mask
|
2839 |
|
|
#define AT91_CAN_BR_PROPAG_SHIFT (8) // Programming Time Segment shift
|
2840 |
|
|
#define AT91_CAN_BR_SJW_MASK (0x3 << 12) // Re-Sync jump width mask
|
2841 |
|
|
#define AT91_CAN_BR_SJW_SHIFT (12) // Re-Sync jump width shift
|
2842 |
|
|
#define AT91_CAN_BR_BRP_MASK (0x7f << 16) // Baudrate Prescaler mask
|
2843 |
|
|
#define AT91_CAN_BR_BRP_SHIFT (16) // Baudrate Prescaler mask
|
2844 |
|
|
#define AT91_CAN_BR_SMP_ONCE (0 << 24) // Sampling once
|
2845 |
|
|
#define AT91_CAN_BR_SMP_THRICE (1 << 24) // Sampling three times
|
2846 |
|
|
#define AT91_CAN_TIM 0x018 // Timer
|
2847 |
|
|
#define AT91_CAN_TIMESTP 0x01c // Timestamp
|
2848 |
|
|
#define AT91_CAN_ECR 0x020 // Error Counter
|
2849 |
|
|
#define AT91_CAN_ECR_REC_MASK (0xf << 0) // Receiver Error Counter mask
|
2850 |
|
|
#define AT91_CAN_ECR_REC_SHIFT (00) // Receiver Error Counter shift
|
2851 |
|
|
#define AT91_CAN_ECR_TEC_MASK (0xf << 16) // Transmit Error Counter mask
|
2852 |
|
|
#define AT91_CAN_ECR_TEC_SHIFT (00) // Transmit Error Counter shift
|
2853 |
|
|
#define AT91_CAN_TCR 0x024 // Transfer Command
|
2854 |
|
|
#define AT91_CAN_TCR_TIMRST (1 << 31) // Timer Reset
|
2855 |
|
|
#define AT91_CAN_ACR 0x028 // Abort Command
|
2856 |
|
|
#define AT91_CAN_MMR0 0x200 // Mailbox 0 Mode
|
2857 |
|
|
#define AT91_CAN_MMR_PRIOR_MASK (0xf << 16) // Priority Mask
|
2858 |
|
|
#define AT91_CAN_MMR_PRIOR_SHIFT (16) // Priority Shift
|
2859 |
|
|
#define AT91_CAN_MMR_MOT_DISABLED (0 << 24) // Mailbox disabled
|
2860 |
|
|
#define AT91_CAN_MMR_MOT_RECEPTION (1 << 24) // Reception Mailbox
|
2861 |
|
|
#define AT91_CAN_MMR_MOT_RECEPTION_OVER (2 << 24) // Reception with Overwrite
|
2862 |
|
|
#define AT91_CAM_MMR_MOT_TRANSMIT (3 << 24) // Transmit Mailbox
|
2863 |
|
|
#define AT91_CAM_MMR_MOT_CONSUMER (4 << 24) // Transmit Mailbox
|
2864 |
|
|
#define AT91_CAM_MMR_MOT_PRODUCER (5 << 24) // Transmit Mailbox
|
2865 |
|
|
#define AT91_CAN_MAM0 0x204 // Mailbox 0 Acceptance Mask
|
2866 |
|
|
#define AT91_CAM_MAM_MIDvB_MASK (0x3ffff << 0) // MIDvB mask
|
2867 |
|
|
#define AT91_CAM_MAM_MIDvB_SHIFT (0) // MIDvB shift
|
2868 |
|
|
#define AT91_CAM_MAM_MIDvA_MASK (0x7ff << 18) // MIDvB mask
|
2869 |
|
|
#define AT91_CAM_MAM_MIDvA_SHIFT (18) // MIDvB shift
|
2870 |
|
|
#define AT91_CAM_MAM_MIDE (1 << 29) // Identifier Version
|
2871 |
|
|
#define AT91_CAN_MID0 0x208 // Mailbox 0 ID
|
2872 |
|
|
#define AT91_CAN_MFID0 0x20C // Mailbox 0 Family ID
|
2873 |
|
|
#define AT91_CAN_MSR0 0x210 // Mailbox 0 Status
|
2874 |
|
|
#define AT91_CAM_MSR_MDLC_MASK (0xf << 16) // Mailbox Data Length Code mask
|
2875 |
|
|
#define AT91_CAM_MSR_MDLC_SHIFT (16) // Mailbox Data Length Code shift
|
2876 |
|
|
#define AT91_CAM_MSR_MRTR (1 << 20) // Mailbox Remote Tx Request
|
2877 |
|
|
#define AT91_CAM_MSR_MABT (1 << 22) // Mailbox Abort
|
2878 |
|
|
#define AT91_CAM_MSR_MRDY (1 << 23) // Mailbox Ready
|
2879 |
|
|
#define AT91_CAM_MSR_MMI (1 << 24) // Mailbox Message Ignored
|
2880 |
|
|
#define AT91_CAN_MDL0 0x214 // Mailbox 0 Data Low
|
2881 |
|
|
#define AT91_CAN_MDH0 0x218 // Mailbox 0 Data High
|
2882 |
|
|
#define AT91_CAN_MCR0 0x21c // Mailbox 0 Control
|
2883 |
|
|
#define AT91_CAM_MCR_MDLC_MASK (0xf << 16) // Mailbox Data Length Code mask
|
2884 |
|
|
#define AT91_CAM_MCR_MDLC_SHIFT (16) // Mailbox Data Length Code shift
|
2885 |
|
|
#define AT91_CAM_MCR_MRTR (1 << 20) // Mailbox Remote Tx Request
|
2886 |
|
|
#define AT91_CAM_MCR_MACR (1 << 22) // Mailbox Abort Request
|
2887 |
|
|
#define AT91_CAM_MCR_MTCR (1 << 23) // Mailbox Transfer Command
|
2888 |
|
|
#define AT91_CAN_MMR1 0x220 // Mailbox 1 Mode
|
2889 |
|
|
#define AT91_CAN_MAM1 0x224 // Mailbox 1 Acceptance Mask
|
2890 |
|
|
#define AT91_CAN_MID1 0x228 // Mailbox 1 ID
|
2891 |
|
|
#define AT91_CAN_MFID1 0x22C // Mailbox 1 Family ID
|
2892 |
|
|
#define AT91_CAN_MSR1 0x230 // Mailbox 1 Status
|
2893 |
|
|
#define AT91_CAN_MDL1 0x234 // Mailbox 1 Data Low
|
2894 |
|
|
#define AT91_CAN_MDH1 0x238 // Mailbox 1 Data High
|
2895 |
|
|
#define AT91_CAN_MCR1 0x23c // Mailbox 1 Control
|
2896 |
|
|
|
2897 |
|
|
#endif
|
2898 |
|
|
|
2899 |
|
|
//=============================================================================
|
2900 |
|
|
// Pulse Width Modulation (PWM)
|
2901 |
|
|
|
2902 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2903 |
|
|
|
2904 |
|
|
#ifndef AT91_PWM
|
2905 |
|
|
#define AT91_PWM 0XFFFCC000
|
2906 |
|
|
#define AT91_PWM_CH0 0xFFFCC200
|
2907 |
|
|
#define AT91_PWM_CH1 0xFFFCC220
|
2908 |
|
|
#define AT91_PWM_CH2 0xFFFCC240
|
2909 |
|
|
#define AT91_PWM_CH3 0xFFFCC260
|
2910 |
|
|
#define AT91_PWM_CH_SIZE 0x20
|
2911 |
|
|
#define AT91_PWM_CH(n) (AT91_PWM_CH0+(n)*AT91_PWM_CH_SIZE)
|
2912 |
|
|
#endif
|
2913 |
|
|
|
2914 |
|
|
#if defined(CYGHWR_HAL_ARM_AT91SAM7)
|
2915 |
|
|
#define AT91_PWM_CHANNELS 4
|
2916 |
|
|
#endif
|
2917 |
|
|
|
2918 |
|
|
#define AT91_PWM_MR (0x00) // Mode
|
2919 |
|
|
#define AT91_PWM_MR_DIVA_MASK (0xff) // CLKA divide factor mask
|
2920 |
|
|
#define AT91_PWM_MR_DIVA_SHIFT (00) // CLKA divide factor shirt
|
2921 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_1 ( 0 << 8) // Prescale A MCLK / 1
|
2922 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_2 ( 1 << 8) // Prescale A MCLK / 2
|
2923 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_4 ( 2 << 8) // Prescale A MCLK / 4
|
2924 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_8 ( 3 << 8) // Prescale A MCLK / 8
|
2925 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_16 ( 4 << 8) // Prescale A MCLK / 16
|
2926 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_32 ( 5 << 8) // Prescale A MCLK / 32
|
2927 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_64 ( 6 << 8) // Prescale A MCLK / 64
|
2928 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_128 ( 7 << 8) // Prescale A MCLK / 128
|
2929 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_256 ( 8 << 8) // Prescale A MCLK / 256
|
2930 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_512 ( 9 << 8) // Prescale A MCLK / 512
|
2931 |
|
|
#define AT91_PWM_MR_PREA_MCK_BY_1024 (10 << 8) // Prescale A MCLK / 1024
|
2932 |
|
|
|
2933 |
|
|
#define AT91_PWM_MR_DIVB_MASK (0xff) // CLKB divide factor mask
|
2934 |
|
|
#define AT91_PWM_MR_DIVB_SHIFT (16) // CLKB divide factor shirt
|
2935 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_1 ( 0 << 24) // Prescale B MCLK / 1
|
2936 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_2 ( 1 << 24) // Prescale B MCLK / 2
|
2937 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_4 ( 2 << 24) // Prescale B MCLK / 4
|
2938 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_8 ( 3 << 24) // Prescale B MCLK / 8
|
2939 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_16 ( 4 << 24) // Prescale B MCLK / 16
|
2940 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_32 ( 5 << 24) // Prescale B MCLK / 32
|
2941 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_64 ( 6 << 24) // Prescale B MCLK / 64
|
2942 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_128 ( 7 << 24) // Prescale B MCLK / 128
|
2943 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_256 ( 8 << 24) // Prescale B MCLK / 256
|
2944 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_512 ( 9 << 24) // Prescale B MCLK / 512
|
2945 |
|
|
#define AT91_PWM_MR_PREB_MCK_BY_1024 (10 << 24) // Prescale B MCLK / 1024
|
2946 |
|
|
#define AT91_PWM_ENA (0x04) // Enable
|
2947 |
|
|
#define AT91_PWM_CHANNEL_ID_0 (0) // Channel ID 0
|
2948 |
|
|
#define AT91_PWM_CHANNEL_ID_1 (1) // Channel ID 1
|
2949 |
|
|
#define AT91_PWM_CHANNEL_ID_2 (2) // Channel ID 2
|
2950 |
|
|
#define AT91_PWM_CHANNEL_ID_3 (3) // Channel ID 3
|
2951 |
|
|
#define AT91_PWM_CHANNEL_ID_4 (4) // Channel ID 4
|
2952 |
|
|
#define AT91_PWM_CHANNEL_ID_5 (5) // Channel ID 5
|
2953 |
|
|
#define AT91_PWM_CHANNEL_ID_6 (6) // Channel ID 6
|
2954 |
|
|
#define AT91_PWM_CHANNEL_ID_7 (7) // Channel ID 7
|
2955 |
|
|
#define AT91_PWM_DIS (0x08) // Disable
|
2956 |
|
|
#define AT91_PWM_SR (0x0c) // Status
|
2957 |
|
|
#define AT91_PWM_IER (0x10) // Interrupt Enable
|
2958 |
|
|
#define AT91_PWM_IDR (0x14) // Interrupt Disable
|
2959 |
|
|
#define AT91_PWM_IMR (0x18) // Interrupt Mask
|
2960 |
|
|
#define AT91_PWM_ISR (0x1c) // Interrupt Status
|
2961 |
|
|
#define AT91_PWM_VR (0xfc) // Version
|
2962 |
|
|
|
2963 |
|
|
// Channel registers.
|
2964 |
|
|
#define AT91_PWM_CMR (0x00) // Channel Mode
|
2965 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_1 0 // Channel Prescale MCL / 1
|
2966 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_2 1 // Channel Prescale MCL / 2
|
2967 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_4 2 // Channel Prescale MCL / 4
|
2968 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_8 3 // Channel Prescale MCL / 8
|
2969 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_16 4 // Channel Prescale MCL / 16
|
2970 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_32 5 // Channel Prescale MCL / 32
|
2971 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_64 6 // Channel Prescale MCL / 64
|
2972 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_128 7 // Channel Prescale MCL / 128
|
2973 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_256 8 // Channel Prescale MCL / 256
|
2974 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_512 9 // Channel Prescale MCL / 512
|
2975 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_BY_1024 10 // Channel Prescale MCL / 1024
|
2976 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_A 11 // Channel MCLK A
|
2977 |
|
|
#define AT91_PWM_CMR_CPRE_MCK_B 12 // Channel MCLK B
|
2978 |
|
|
#define AT91_PWM_CMR_CALG_LEFT (0 << 8) // Left align period
|
2979 |
|
|
#define AT91_PWM_CMR_CALG_CENTER (1 << 8) // Center align period
|
2980 |
|
|
#define AT91_PWM_CMR_CPOL_LOW (0 << 9) // Low to start with
|
2981 |
|
|
#define AT91_PWM_CMR_CPOL_HIGH (1 << 9) // High to start with
|
2982 |
|
|
#define AT91_PWM_CPD_DUTY (0 << 10) // Notify the duty cycle
|
2983 |
|
|
#define AT91_PWM_CPD_PERIOD (1 << 10) // Notify the period
|
2984 |
|
|
#define AT91_PWM_CDTY (0x04) // Channel Duty Cycle
|
2985 |
|
|
#define AT91_PWM_CPRDR (0x08) // Channel Period
|
2986 |
|
|
#define AT91_PWM_CCNTR (0x0C) // Channel Counter
|
2987 |
|
|
#define AT91_PWM_CUPDR (0x10) // Channel Update
|
2988 |
|
|
|
2989 |
|
|
|
2990 |
|
|
#endif
|
2991 |
|
|
|
2992 |
|
|
//=============================================================================
|
2993 |
|
|
// FIQ interrupt vector which is shared by all HAL varients.
|
2994 |
|
|
|
2995 |
|
|
#define CYGNUM_HAL_INTERRUPT_FIQ 0
|
2996 |
|
|
|
2997 |
|
|
//=============================================================================
|
2998 |
|
|
// Macros for access the GPIO lines and configuring peripheral pins
|
2999 |
|
|
|
3000 |
|
|
// Given a pin description, determine which PIO controller it is on
|
3001 |
|
|
#define HAL_ARM_AT91_PIO_CTRL(_pin_) \
|
3002 |
|
|
((_pin_ >> 16) & 0xff)
|
3003 |
|
|
|
3004 |
|
|
// Given a pin description, determine which PIO bit controls this pin
|
3005 |
|
|
#define HAL_ARM_AT91_PIO_BIT(_pin_) \
|
3006 |
|
|
(1 << (_pin_ & 0xff))
|
3007 |
|
|
|
3008 |
|
|
// Evaluate to true if the pin is using peripheral A
|
3009 |
|
|
#define HAL_ARM_AT91_PIO_A(_pin_) \
|
3010 |
|
|
(((_pin_ >> 8) & 0xff) == 0)
|
3011 |
|
|
|
3012 |
|
|
// Configure a peripheral pin on a specific PIO controller.
|
3013 |
|
|
#ifdef AT91_PIO_ASR
|
3014 |
|
|
#define HAL_ARM_AT91_PIOX_CFG(_pin_, _nr_, _pio_base_) \
|
3015 |
|
|
CYG_MACRO_START \
|
3016 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3017 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PDR, \
|
3018 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3019 |
|
|
if (HAL_ARM_AT91_PIO_A(_pin_)) { \
|
3020 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_ASR, \
|
3021 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3022 |
|
|
} else { \
|
3023 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_BSR, \
|
3024 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3025 |
|
|
} \
|
3026 |
|
|
} \
|
3027 |
|
|
CYG_MACRO_END
|
3028 |
|
|
#else // AT91_PIO_ASR
|
3029 |
|
|
#define HAL_ARM_AT91_PIOX_CFG(_pin_, _nr_, _pio_base_) \
|
3030 |
|
|
CYG_MACRO_START \
|
3031 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3032 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PDR, \
|
3033 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3034 |
|
|
} \
|
3035 |
|
|
CYG_MACRO_END
|
3036 |
|
|
#endif // !AT91_PIO_ASR
|
3037 |
|
|
|
3038 |
|
|
// Configure a GPIO pin direction on a specific PIO controller.
|
3039 |
|
|
#define HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, _nr_, _pio_base_) \
|
3040 |
|
|
CYG_MACRO_START \
|
3041 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3042 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PER, \
|
3043 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3044 |
|
|
if ((_dir_) == AT91_PIN_IN) { \
|
3045 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_ODR, \
|
3046 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3047 |
|
|
} else { \
|
3048 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_OER, \
|
3049 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3050 |
|
|
} \
|
3051 |
|
|
} \
|
3052 |
|
|
CYG_MACRO_END
|
3053 |
|
|
|
3054 |
|
|
// Configure a GPIO pin pullup on a specific PIO controller.
|
3055 |
|
|
#define HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, _nr_, _pio_base_) \
|
3056 |
|
|
CYG_MACRO_START \
|
3057 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3058 |
|
|
if (_enable_) { \
|
3059 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PPUER, \
|
3060 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3061 |
|
|
} else { \
|
3062 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_PPUDR, \
|
3063 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3064 |
|
|
} \
|
3065 |
|
|
} \
|
3066 |
|
|
CYG_MACRO_END
|
3067 |
|
|
|
3068 |
|
|
// Configure a GPIO pin MultiDrain on a specific PIO controller.
|
3069 |
|
|
#define HAL_ARM_AT91_GPIOX_CFG_MULTIDRAIN(_pin_, _enable_, _nr_, _pio_base_) \
|
3070 |
|
|
CYG_MACRO_START \
|
3071 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3072 |
|
|
if (_enable_) { \
|
3073 |
|
|
HAL_WRITE_UINT32((_pio_base_)+ AT91_PIO_MDER, \
|
3074 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3075 |
|
|
} else { \
|
3076 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_MDDR, \
|
3077 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3078 |
|
|
} \
|
3079 |
|
|
} \
|
3080 |
|
|
CYG_MACRO_END
|
3081 |
|
|
|
3082 |
|
|
// Set a GPIO pin on a specific PIO controller to generate interrupts
|
3083 |
|
|
#define HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, _nr_, _pio_base_) \
|
3084 |
|
|
CYG_MACRO_START \
|
3085 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3086 |
|
|
if (_enable_) { \
|
3087 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_IER, \
|
3088 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3089 |
|
|
} else { \
|
3090 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_IDR, \
|
3091 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3092 |
|
|
} \
|
3093 |
|
|
} \
|
3094 |
|
|
CYG_MACRO_END
|
3095 |
|
|
|
3096 |
|
|
// Set a GPIO pin on a specific PIO controller.
|
3097 |
|
|
#define HAL_ARM_AT91_GPIOX_SET(_pin_, _nr_, _pio_base_) \
|
3098 |
|
|
CYG_MACRO_START \
|
3099 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3100 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_SODR, \
|
3101 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3102 |
|
|
} \
|
3103 |
|
|
CYG_MACRO_END
|
3104 |
|
|
|
3105 |
|
|
// Reset a GPIO pin on a specific PIO controller.
|
3106 |
|
|
#define HAL_ARM_AT91_GPIOX_RESET(_pin_, _nr_, _pio_base_) \
|
3107 |
|
|
CYG_MACRO_START \
|
3108 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3109 |
|
|
HAL_WRITE_UINT32((_pio_base_)+AT91_PIO_CODR, \
|
3110 |
|
|
HAL_ARM_AT91_PIO_BIT(_pin_)); \
|
3111 |
|
|
} \
|
3112 |
|
|
CYG_MACRO_END
|
3113 |
|
|
|
3114 |
|
|
// Get a GPIO pin on a specific PIO controller.
|
3115 |
|
|
#define HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, _nr_, _pio_base_) \
|
3116 |
|
|
CYG_MACRO_START \
|
3117 |
|
|
cyg_uint32 _pdsr_; \
|
3118 |
|
|
if (HAL_ARM_AT91_PIO_CTRL(_pin_) == (_nr_)) { \
|
3119 |
|
|
HAL_READ_UINT32((_pio_base_)+AT91_PIO_PDSR, _pdsr_); \
|
3120 |
|
|
(_value_) = (_pdsr_ & HAL_ARM_AT91_PIO_BIT(_pin_) ? 1 : 0); \
|
3121 |
|
|
} \
|
3122 |
|
|
CYG_MACRO_END
|
3123 |
|
|
|
3124 |
|
|
#define AT91_PIN_IN 1
|
3125 |
|
|
#define AT91_PIN_OUT 0
|
3126 |
|
|
#define AT91_PIN_PULLUP_ENABLE 1
|
3127 |
|
|
#define AT91_PIN_PULLUP_DISABLE 0
|
3128 |
|
|
#define AT91_PIN_INTERRUPT_ENABLE 1
|
3129 |
|
|
#define AT91_PIN_INTERRUPT_DISABLE 0
|
3130 |
|
|
#define AT91_PIN_MULTIDRAIN_ENABLE 1
|
3131 |
|
|
#define AT91_PIN_MULTIDRAIN_DISABLE 0
|
3132 |
|
|
|
3133 |
|
|
|
3134 |
|
|
#ifndef AT91_PIOB
|
3135 |
|
|
//------------------------
|
3136 |
|
|
// Only one PIO controller
|
3137 |
|
|
//------------------------
|
3138 |
|
|
|
3139 |
|
|
// Configure a peripheral pin for peripheral operation
|
3140 |
|
|
#define HAL_ARM_AT91_PIO_CFG(_pin_) \
|
3141 |
|
|
CYG_MACRO_START \
|
3142 |
|
|
HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
|
3143 |
|
|
CYG_MACRO_END
|
3144 |
|
|
|
3145 |
|
|
// Configure a GPIO pin direction
|
3146 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \
|
3147 |
|
|
CYG_MACRO_START \
|
3148 |
|
|
HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
|
3149 |
|
|
CYG_MACRO_END
|
3150 |
|
|
|
3151 |
|
|
// Configure a GPIO pin pullup resistor
|
3152 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \
|
3153 |
|
|
CYG_MACRO_START \
|
3154 |
|
|
HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
|
3155 |
|
|
CYG_MACRO_END
|
3156 |
|
|
|
3157 |
|
|
// Configure Multi Drain on a GPIO
|
3158 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_MULTIDRAIN(_pin_, _enable_) \
|
3159 |
|
|
CYG_MACRO_START \
|
3160 |
|
|
HAL_ARM_AT91_GPIOX_CFG_MULTIDRAIN(_pin_, _enable_, 0, AT91_PIO); \
|
3161 |
|
|
CYG_MACRO_END
|
3162 |
|
|
|
3163 |
|
|
// Configure a GPIO pin to generate interrupts
|
3164 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \
|
3165 |
|
|
CYG_MACRO_START \
|
3166 |
|
|
HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
|
3167 |
|
|
CYG_MACRO_END
|
3168 |
|
|
|
3169 |
|
|
// Set a GPIO pin to one
|
3170 |
|
|
#define HAL_ARM_AT91_GPIO_SET(_pin_) \
|
3171 |
|
|
CYG_MACRO_START \
|
3172 |
|
|
HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
|
3173 |
|
|
CYG_MACRO_END
|
3174 |
|
|
|
3175 |
|
|
// Reset a GPIO pin to zero
|
3176 |
|
|
#define HAL_ARM_AT91_GPIO_RESET(_pin_) \
|
3177 |
|
|
CYG_MACRO_START \
|
3178 |
|
|
HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
|
3179 |
|
|
CYG_MACRO_END
|
3180 |
|
|
|
3181 |
|
|
// Get the state of a GPIO pin
|
3182 |
|
|
#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \
|
3183 |
|
|
CYG_MACRO_START \
|
3184 |
|
|
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
|
3185 |
|
|
CYG_MACRO_END
|
3186 |
|
|
|
3187 |
|
|
#elif !defined(AT91_PIOC) // !AT91_PIOB
|
3188 |
|
|
//--------------------
|
3189 |
|
|
// Two PIO controllers
|
3190 |
|
|
//--------------------
|
3191 |
|
|
|
3192 |
|
|
// Configure a peripheral pin for peripheral operation
|
3193 |
|
|
#define HAL_ARM_AT91_PIO_CFG(_pin_) \
|
3194 |
|
|
CYG_MACRO_START \
|
3195 |
|
|
HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
|
3196 |
|
|
HAL_ARM_AT91_PIOX_CFG(_pin_, 1, AT91_PIOB); \
|
3197 |
|
|
CYG_MACRO_END
|
3198 |
|
|
|
3199 |
|
|
// Configure a GPIO pin direction
|
3200 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \
|
3201 |
|
|
CYG_MACRO_START \
|
3202 |
|
|
HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
|
3203 |
|
|
HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 1, AT91_PIOB); \
|
3204 |
|
|
CYG_MACRO_END
|
3205 |
|
|
|
3206 |
|
|
// Configure a GPIO pin pullup resistor
|
3207 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \
|
3208 |
|
|
CYG_MACRO_START \
|
3209 |
|
|
HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
|
3210 |
|
|
HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 1, AT91_PIOB); \
|
3211 |
|
|
CYG_MACRO_END
|
3212 |
|
|
|
3213 |
|
|
// Configure Multi Drain on a GPIO
|
3214 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_MULTIDRAIN(_pin_, _enable_) \
|
3215 |
|
|
CYG_MACRO_START \
|
3216 |
|
|
HAL_ARM_AT91_GPIOX_CFG_MULTIDRAIN(_pin_, _enable_, 0, AT91_PIO); \
|
3217 |
|
|
HAL_ARM_AT91_GPIOX_CFG_MULTIDRAIN(_pin_, _enable_, 1, AT91_PIOB); \
|
3218 |
|
|
CYG_MACRO_END
|
3219 |
|
|
|
3220 |
|
|
// Configure a GPIO pin to generate interrupts
|
3221 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \
|
3222 |
|
|
CYG_MACRO_START \
|
3223 |
|
|
HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
|
3224 |
|
|
HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 1, AT91_PIOB); \
|
3225 |
|
|
CYG_MACRO_END
|
3226 |
|
|
|
3227 |
|
|
// Set a GPIO pin to 1
|
3228 |
|
|
#define HAL_ARM_AT91_GPIO_SET(_pin_) \
|
3229 |
|
|
CYG_MACRO_START \
|
3230 |
|
|
HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
|
3231 |
|
|
HAL_ARM_AT91_GPIOX_SET(_pin_, 1, AT91_PIOB); \
|
3232 |
|
|
CYG_MACRO_END
|
3233 |
|
|
|
3234 |
|
|
// Reset a GPIO pin to 0
|
3235 |
|
|
#define HAL_ARM_AT91_GPIO_RESET(_pin_) \
|
3236 |
|
|
CYG_MACRO_START \
|
3237 |
|
|
HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
|
3238 |
|
|
HAL_ARM_AT91_GPIOX_RESET(_pin_, 1, AT91_PIOB); \
|
3239 |
|
|
CYG_MACRO_END
|
3240 |
|
|
|
3241 |
|
|
// Get the state of a GPIO pin
|
3242 |
|
|
#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \
|
3243 |
|
|
CYG_MACRO_START \
|
3244 |
|
|
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
|
3245 |
|
|
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \
|
3246 |
|
|
CYG_MACRO_END
|
3247 |
|
|
#else
|
3248 |
|
|
//----------------------
|
3249 |
|
|
// Three PIO controllers
|
3250 |
|
|
//----------------------
|
3251 |
|
|
|
3252 |
|
|
// Configure a peripheral pin for peripheral operation
|
3253 |
|
|
#define HAL_ARM_AT91_PIO_CFG(_pin_) \
|
3254 |
|
|
CYG_MACRO_START \
|
3255 |
|
|
HAL_ARM_AT91_PIOX_CFG(_pin_, 0, AT91_PIO); \
|
3256 |
|
|
HAL_ARM_AT91_PIOX_CFG(_pin_, 1, AT91_PIOB); \
|
3257 |
|
|
HAL_ARM_AT91_PIOX_CFG(_pin_, 2, AT91_PIOC); \
|
3258 |
|
|
CYG_MACRO_END
|
3259 |
|
|
|
3260 |
|
|
// Configure a GPIO pin direction
|
3261 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_DIRECTION(_pin_, _dir_) \
|
3262 |
|
|
CYG_MACRO_START \
|
3263 |
|
|
HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 0, AT91_PIO); \
|
3264 |
|
|
HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 1, AT91_PIOB); \
|
3265 |
|
|
HAL_ARM_AT91_GPIOX_CFG_DIRECTION(_pin_, _dir_, 2, AT91_PIOC); \
|
3266 |
|
|
CYG_MACRO_END
|
3267 |
|
|
|
3268 |
|
|
// Configure a GPIO pin pullup resistor
|
3269 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_PULLUP(_pin_, _enable_) \
|
3270 |
|
|
CYG_MACRO_START \
|
3271 |
|
|
HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 0, AT91_PIO); \
|
3272 |
|
|
HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 1, AT91_PIOB); \
|
3273 |
|
|
HAL_ARM_AT91_GPIOX_CFG_PULLUP(_pin_, _enable_, 2, AT91_PIOC); \
|
3274 |
|
|
CYG_MACRO_END
|
3275 |
|
|
|
3276 |
|
|
// Configure Multi Drain on a GPIO
|
3277 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_MULTIDRAIN(_pin_, _enable_) \
|
3278 |
|
|
CYG_MACRO_START \
|
3279 |
|
|
HAL_ARM_AT91_GPIOX_CFG_MULTIDRAIN(_pin_, _enable_, 0, AT91_PIO); \
|
3280 |
|
|
HAL_ARM_AT91_GPIOX_CFG_MULTIDRAIN(_pin_, _enable_, 1, AT91_PIOB); \
|
3281 |
|
|
HAL_ARM_AT91_GPIOX_CFG_MULTIDRAIN(_pin_, _enable_, 2, AT91_PIOC); \
|
3282 |
|
|
CYG_MACRO_END
|
3283 |
|
|
|
3284 |
|
|
// Configure a GPIO pin to generate interrupts
|
3285 |
|
|
#define HAL_ARM_AT91_GPIO_CFG_INTERRUPT(_pin_, _enable_) \
|
3286 |
|
|
CYG_MACRO_START \
|
3287 |
|
|
HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 0, AT91_PIO); \
|
3288 |
|
|
HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 1, AT91_PIOB); \
|
3289 |
|
|
HAL_ARM_AT91_GPIOX_CFG_INTERRUPT(_pin_, _enable_, 2, AT91_PIOC); \
|
3290 |
|
|
CYG_MACRO_END
|
3291 |
|
|
|
3292 |
|
|
// Set a GPIO pin to 1
|
3293 |
|
|
#define HAL_ARM_AT91_GPIO_SET(_pin_) \
|
3294 |
|
|
CYG_MACRO_START \
|
3295 |
|
|
HAL_ARM_AT91_GPIOX_SET(_pin_, 0, AT91_PIO); \
|
3296 |
|
|
HAL_ARM_AT91_GPIOX_SET(_pin_, 1, AT91_PIOB); \
|
3297 |
|
|
HAL_ARM_AT91_GPIOX_SET(_pin_, 2, AT91_PIOC); \
|
3298 |
|
|
CYG_MACRO_END
|
3299 |
|
|
|
3300 |
|
|
// Reset a GPIO pin to 0
|
3301 |
|
|
#define HAL_ARM_AT91_GPIO_RESET(_pin_) \
|
3302 |
|
|
CYG_MACRO_START \
|
3303 |
|
|
HAL_ARM_AT91_GPIOX_RESET(_pin_, 0, AT91_PIO); \
|
3304 |
|
|
HAL_ARM_AT91_GPIOX_RESET(_pin_, 1, AT91_PIOB); \
|
3305 |
|
|
HAL_ARM_AT91_GPIOX_RESET(_pin_, 2, AT91_PIOC); \
|
3306 |
|
|
CYG_MACRO_END
|
3307 |
|
|
|
3308 |
|
|
// Get the state of a GPIO pin
|
3309 |
|
|
#define HAL_ARM_AT91_GPIO_GET(_pin_, _value_) \
|
3310 |
|
|
CYG_MACRO_START \
|
3311 |
|
|
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 0, AT91_PIO); \
|
3312 |
|
|
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 1, AT91_PIOB); \
|
3313 |
|
|
HAL_ARM_AT91_GPIOX_GET(_pin_, _value_, 2, AT91_PIOC); \
|
3314 |
|
|
CYG_MACRO_END
|
3315 |
|
|
#endif //!AT91_PIOB
|
3316 |
|
|
|
3317 |
|
|
// Put a GPIO pin to a given state
|
3318 |
|
|
#define HAL_ARM_AT91_GPIO_PUT(_pin_, _state_) \
|
3319 |
|
|
CYG_MACRO_START \
|
3320 |
|
|
if (_state_) { \
|
3321 |
|
|
HAL_ARM_AT91_GPIO_SET(_pin_); \
|
3322 |
|
|
} else { \
|
3323 |
|
|
HAL_ARM_AT91_GPIO_RESET(_pin_); \
|
3324 |
|
|
} \
|
3325 |
|
|
CYG_MACRO_END
|
3326 |
|
|
|
3327 |
|
|
//-----------------------------------------------------------------------------
|
3328 |
|
|
// end of var_io.h
|
3329 |
|
|
#endif // CYGONCE_HAL_VAR_IO_H
|