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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [at91/] [var/] [current/] [src/] [timer_pit.c] - Blame information for rev 786

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1 786 skrzyp
/*==========================================================================
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//
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//      timer_pit.c
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//
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//      HAL timer code using the Periodic Interval Timer
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2006 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    asl, Oliver Munz
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// Contributors: asl, Oliver Munz
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// Date:         2009-06-03
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// Purpose:      Clock support using the PIT
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>         // base types
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#include <cyg/infra/cyg_ass.h>          // assertion macros
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#include <cyg/hal/hal_io.h>             // IO macros
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#include <cyg/hal/hal_platform_ints.h>
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// -------------------------------------------------------------------------
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// Use system clock
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void
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hal_clock_initialize(cyg_uint32 period){
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  cyg_uint32 ir;
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  cyg_uint32 pimr;
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  CYG_ASSERT(CYGNUM_HAL_INTERRUPT_RTC == CYGNUM_HAL_INTERRUPT_PITC,
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             "Invalid timer interrupt");
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  CYG_ASSERT(period <= AT91_PITC_VALUE_MASK,
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             "Invalid timer period");
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  pimr = (period - 1); /* This is what we want */
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  HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIIR, ir); /* Counter */
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  ir = ir & AT91_PITC_VALUE_MASK; /* The current count */
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  do { /* Test if the new PITC-Modulus is overrun by the counter */
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    if (ir > pimr){ /* If the counter is already too high */
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      pimr = (ir + 100) & AT91_PITC_VALUE_MASK; /* Set the comparator ahead */
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      HAL_WRITE_UINT32((AT91_PITC + AT91_PITC_PIMR),
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                       pimr | AT91_PITC_PIMR_PITEN);
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    }
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    if (ir < (period - 1)){ /* If we can try it */
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      pimr = (period - 1); /* This is what we want */
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      /* Set the real Period Interval timer */
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      HAL_WRITE_UINT32((AT91_PITC + AT91_PITC_PIMR),
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                       pimr | AT91_PITC_PIMR_PITEN);
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    }
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    HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIMR, pimr); /* The real value */
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    pimr = pimr & AT91_PITC_VALUE_MASK; /* Value */
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    HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIIR, ir); /* Counter */
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    ir = ir & AT91_PITC_VALUE_MASK; /* The current counts */
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  } while (ir > (period - 1) || pimr != (period - 1)); // Is it correct?
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  /* Enable interrupt */
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  HAL_WRITE_UINT32((AT91_PITC + AT91_PITC_PIMR), (period - 1) |
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                   AT91_PITC_PIMR_PITEN | AT91_PITC_PIMR_PITIEN);
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  /* Read the status register to clear any pending interrupt */
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  HAL_READ_UINT32(AT91_PITC + AT91_PITC_PISR, ir);
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}
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// This routine is called during a clock interrupt.
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void
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hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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{
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  cyg_uint32 reg;
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  cyg_uint32 pimr;
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  CYG_ASSERT(period < AT91_PITC_VALUE_MASK, "Invalid HAL clock configuration");
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  // Check that the PIT has the right period.
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  HAL_READ_UINT32((AT91_PITC + AT91_PITC_PIMR), pimr);
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  if ((pimr & AT91_PITC_VALUE_MASK) != (period - 1)) {
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    HAL_WRITE_UINT32((AT91_PITC + AT91_PITC_PIMR),
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                     (period - 1) |
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                     AT91_PITC_PIMR_PITEN |
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                     AT91_PITC_PIMR_PITIEN);
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  }
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  /* Read the value register so that we clear the interrupt */
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  HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIVR, reg);
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}
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// Read the current value of the clock, returning the number of hardware
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// "ticks" that have occurred (i.e. how far away the current value is from
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// the start)
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void
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hal_clock_read(cyg_uint32 *pvalue)
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{
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  cyg_uint32 ir;
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  cyg_uint32 pimr;
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  // Check that the PIT is running. If not start it.
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  HAL_READ_UINT32((AT91_PITC + AT91_PITC_PIMR),pimr);
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  if (!(pimr & AT91_PITC_PIMR_PITEN)) {
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    HAL_WRITE_UINT32((AT91_PITC + AT91_PITC_PIMR),
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                     AT91_PITC_VALUE_MASK | AT91_PITC_PIMR_PITEN);
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  }
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  HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIIR, ir);
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  *pvalue = ir & AT91_PITC_VALUE_MASK;
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}
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// -------------------------------------------------------------------------
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//
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// Delay for some number of micro-seconds
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// PIT is clocked at MCLK / 16
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//
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void hal_delay_us(cyg_int32 usecs)
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{
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  cyg_int64 ticks;
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  cyg_uint32 val1, val2;
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  cyg_uint32 piv;
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  // Calculate how many PIT ticks the required number of microseconds
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  // equate to. We do this calculation in 64 bit arithmetic to avoid
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  // overflow.
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  ticks = (((cyg_uint64)usecs) *
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           ((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/16/1000000LL;
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  // Calculate the wrap around period.
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  HAL_READ_UINT32(AT91_PITC + AT91_PITC_PIMR, piv);
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  piv = (piv & AT91_PITC_VALUE_MASK) - 1;
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  hal_clock_read(&val1);
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  while (ticks > 0) {
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    hal_clock_read(&val2);
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    if (val2 < val1)
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      ticks -= ((piv + val2) - val1); //overflow occurred
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    else
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      ticks -= (val2 - val1);
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    val1 = val2;
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  }
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}
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// timer_pit.c

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