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skrzyp |
#ifndef CYGONCE_HAL_PLATFORM_INTS_H
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#define CYGONCE_HAL_PLATFORM_INTS_H
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//==========================================================================
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//
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// hal_platform_ints.h
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//
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// HAL Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt
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// Contributors: hmt
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// Date: 1999-04-21
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// Purpose: Define Interrupt support
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// Description: The interrupt details for the EBSA285 are defined here.
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// Usage:
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// #include <cyg/hal/hal_platform_ints.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#define CYGNUM_HAL_INTERRUPT_reserved0 0
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#define CYGNUM_HAL_INTERRUPT_SOFT_IRQ 1
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#define CYGNUM_HAL_INTERRUPT_SERIAL_RX 2
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#define CYGNUM_HAL_INTERRUPT_SERIAL_TX 3
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#define CYGNUM_HAL_INTERRUPT_TIMER_1 4
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#define CYGNUM_HAL_INTERRUPT_TIMER_2 5
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#define CYGNUM_HAL_INTERRUPT_TIMER_3 6
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#define CYGNUM_HAL_INTERRUPT_TIMER_4 7
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#define CYGNUM_HAL_INTERRUPT_IRQ_IN_0 8
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#define CYGNUM_HAL_INTERRUPT_IRQ_IN_1 9
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#define CYGNUM_HAL_INTERRUPT_IRQ_IN_2 10
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#define CYGNUM_HAL_INTERRUPT_IRQ_IN_3 11
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#define CYGNUM_HAL_INTERRUPT_XBUS_CS_0 12
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#define CYGNUM_HAL_INTERRUPT_XBUS_CS_1 13
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#define CYGNUM_HAL_INTERRUPT_XBUS_CS_2 14
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#define CYGNUM_HAL_INTERRUPT_DOORBELL 15
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#define CYGNUM_HAL_INTERRUPT_DMA_1 16
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#define CYGNUM_HAL_INTERRUPT_DMA_2 17
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#define CYGNUM_HAL_INTERRUPT_PCI_IRQ 18
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#define CYGNUM_HAL_INTERRUPT_PMCSR 19
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#define CYGNUM_HAL_INTERRUPT_reserved20 20
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#define CYGNUM_HAL_INTERRUPT_reserved21 21
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#define CYGNUM_HAL_INTERRUPT_BIST 22
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#define CYGNUM_HAL_INTERRUPT_SERR 23
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#define CYGNUM_HAL_INTERRUPT_SDRAM_PARITY 24
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#define CYGNUM_HAL_INTERRUPT_I2O_POST 25
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#define CYGNUM_HAL_INTERRUPT_reserved26 26
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#define CYGNUM_HAL_INTERRUPT_DISCARD_TIMER 27
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#define CYGNUM_HAL_INTERRUPT_PCI_DATA_PARITY 28
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#define CYGNUM_HAL_INTERRUPT_PCI_MASTER_ABORT 29
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#define CYGNUM_HAL_INTERRUPT_PCI_TARGET_ABORT 30
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#define CYGNUM_HAL_INTERRUPT_PCI_PARITY_ERROR 31
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 31
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#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
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// The vector used by the Real time clock
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_3
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//----------------------------------------------------------------------------
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// Reset.
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#include <cyg/hal/hal_ebsa285.h> // registers
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#include <cyg/hal/hal_io.h> // IO macros
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#define HAL_PLATFORM_RESET() \
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CYG_MACRO_START \
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cyg_uint32 ctrl; \
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\
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/* If watchdog is already enabled, writing to timer4 has no effect. */ \
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/* But by disabling interupts and just hanging in the loop below */ \
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/* the timer might run out eventually (not guaranteed). */ \
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HAL_DISABLE_INTERRUPTS(ctrl); \
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\
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/* Set timer4 (must be done before enabling watchdog) */ \
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HAL_WRITE_UINT32(SA110_TIMER4_LOAD, 2); \
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HAL_WRITE_UINT32(SA110_TIMER4_CONTROL, SA110_TIMER_CONTROL_ENABLE); \
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\
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/* Enable watchdog */ \
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HAL_READ_UINT32(SA110_CONTROL, ctrl); \
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ctrl |= SA110_CONTROL_WATCHDOG; \
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HAL_WRITE_UINT32(SA110_CONTROL, ctrl); \
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\
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for(;;); /* wait for it */ \
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CYG_MACRO_END
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#define HAL_PLATFORM_RESET_ENTRY 0x41000000
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#endif // CYGONCE_HAL_PLATFORM_INTS_H
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