OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [integrator/] [current/] [include/] [hal_cache.h] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
#ifndef CYGONCE_HAL_CACHE_H
2
#define CYGONCE_HAL_CACHE_H
3
 
4
//=============================================================================
5
//
6
//      hal_cache.h
7
//
8
//      HAL cache control API
9
//
10
//=============================================================================
11
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
12
// -------------------------------------------                              
13
// This file is part of eCos, the Embedded Configurable Operating System.   
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under    
17
// the terms of the GNU General Public License as published by the Free     
18
// Software Foundation; either version 2 or (at your option) any later      
19
// version.                                                                 
20
//
21
// eCos is distributed in the hope that it will be useful, but WITHOUT      
22
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
24
// for more details.                                                        
25
//
26
// You should have received a copy of the GNU General Public License        
27
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
28
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
29
//
30
// As a special exception, if other files instantiate templates or use      
31
// macros or inline functions from this file, or you compile this file      
32
// and link it with other works to produce a work based on this file,       
33
// this file does not by itself cause the resulting work to be covered by   
34
// the GNU General Public License. However the source code for this file    
35
// must still be made available in accordance with section (3) of the GNU   
36
// General Public License v2.                                               
37
//
38
// This exception does not invalidate any other reasons why a work based    
39
// on this file might be covered by the GNU General Public License.         
40
// -------------------------------------------                              
41
// ####ECOSGPLCOPYRIGHTEND####                                              
42
//=============================================================================
43
//#####DESCRIPTIONBEGIN####
44
//
45
// Author(s):    David A Rusling
46
// Contributors: Philippe Robin
47
// Date:         November 7, 2000
48
// Purpose:      Cache control API
49
// Description:  The macros defined here provide the HAL APIs for handling
50
//               cache control operations.
51
// Usage:
52
//               #include <cyg/hal/hal_cache.h>
53
//               ...
54
//              
55
//
56
//####DESCRIPTIONEND####
57
//
58
//=============================================================================
59
 
60
#include <cyg/infra/cyg_type.h>
61
 
62
//-----------------------------------------------------------------------------
63
// Cache dimensions
64
 
65
// Data cache
66
#define HAL_DCACHE_SIZE                 0    // Size of data cache in bytes
67
#define HAL_DCACHE_LINE_SIZE            0    // Size of a data cache line
68
#define HAL_DCACHE_WAYS                 0    // Associativity of the cache
69
 
70
// Instruction cache
71
#define HAL_ICACHE_SIZE                 0    // Size of cache in bytes
72
#define HAL_ICACHE_LINE_SIZE            0    // Size of a cache line
73
#define HAL_ICACHE_WAYS                 0    // Associativity of the cache
74
 
75
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
76
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
77
 
78
//-----------------------------------------------------------------------------
79
// Global control of data cache
80
 
81
// Enable the data cache
82
#define HAL_DCACHE_ENABLE()
83
 
84
// Disable the data cache
85
#define HAL_DCACHE_DISABLE()
86
 
87
// Invalidate the entire cache
88
#define HAL_DCACHE_INVALIDATE_ALL()
89
 
90
// Synchronize the contents of the cache with memory.
91
#define HAL_DCACHE_SYNC()
92
 
93
// Query the state of the data cache
94
#define HAL_DCACHE_IS_ENABLED(_state_)  0
95
 
96
// Purge contents of data cache
97
#define HAL_DCACHE_PURGE_ALL()
98
 
99
// Set the data cache refill burst size
100
//#define HAL_DCACHE_BURST_SIZE(_size_)
101
 
102
// Set the data cache write mode
103
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
104
 
105
//#define HAL_DCACHE_WRITETHRU_MODE       0
106
//#define HAL_DCACHE_WRITEBACK_MODE       1
107
 
108
// Load the contents of the given address range into the data cache
109
// and then lock the cache so that it stays there.
110
//#define HAL_DCACHE_LOCK(_base_, _size_)
111
 
112
// Undo a previous lock operation
113
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
114
 
115
// Unlock entire cache
116
//#define HAL_DCACHE_UNLOCK_ALL()
117
 
118
//-----------------------------------------------------------------------------
119
// Data cache line control
120
 
121
// Allocate cache lines for the given address range without reading its
122
// contents from memory.
123
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
124
 
125
// Write dirty cache lines to memory and invalidate the cache entries
126
// for the given address range.
127
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
128
 
129
// Invalidate cache lines in the given range without writing to memory.
130
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
131
 
132
// Write dirty cache lines to memory for the given address range.
133
//#define HAL_DCACHE_STORE( _base_ , _size_ )
134
 
135
// Preread the given range into the cache with the intention of reading
136
// from it later.
137
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
138
 
139
// Preread the given range into the cache with the intention of writing
140
// to it later.
141
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
142
 
143
// Allocate and zero the cache lines associated with the given range.
144
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
145
 
146
//-----------------------------------------------------------------------------
147
// Global control of Instruction cache
148
 
149
// Enable the instruction cache
150
#define HAL_ICACHE_ENABLE()
151
 
152
// Disable the instruction cache
153
#define HAL_ICACHE_DISABLE()
154
 
155
// Invalidate the entire cache
156
#define HAL_ICACHE_INVALIDATE_ALL()
157
 
158
// Synchronize the contents of the cache with memory.
159
#define HAL_ICACHE_SYNC()
160
 
161
// Set the instruction cache refill burst size
162
//#define HAL_ICACHE_BURST_SIZE(_size_)
163
 
164
// Load the contents of the given address range into the instruction cache
165
// and then lock the cache so that it stays there.
166
//#define HAL_ICACHE_LOCK(_base_, _size_)
167
 
168
// Undo a previous lock operation
169
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
170
 
171
// Unlock entire cache
172
//#define HAL_ICACHE_UNLOCK_ALL()
173
 
174
//-----------------------------------------------------------------------------
175
// Instruction cache line control
176
 
177
// Invalidate cache lines in the given range without writing to memory.
178
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
179
 
180
//-----------------------------------------------------------------------------
181
#endif // ifndef CYGONCE_HAL_CACHE_H
182
// End of hal_cache.h

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.