OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [lpc24xx/] [ea2468/] [current/] [include/] [pkgconf/] [mlt_arm_lpc24xx_ea2468_rom.h] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
// eCos memory layout - Wed Apr 11 13:49:55 2001
2
 
3
// This is a generated file - do not edit
4
 
5
#ifndef __ASSEMBLER__
6
#include <cyg/infra/cyg_type.h>
7
#include <stddef.h>
8
 
9
#endif
10
#define CYGMEM_REGION_sram (0x40000000)
11
#define CYGMEM_REGION_sram_SIZE (0x00010000)
12
#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
13
 
14
#define CYGMEM_REGION_ram (0xA0000000)
15
#define CYGMEM_REGION_ram_SIZE (0x02000000)
16
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
17
 
18
#define CYGMEM_REGION_rom (0x00000000)
19
#define CYGMEM_REGION_rom_SIZE (0x00080000)
20
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
21
 
22
 
23
#ifndef __ASSEMBLER__
24
extern char CYG_LABEL_NAME (__heap1) [];
25
#endif
26
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
27
#define CYGMEM_SECTION_heap1_SIZE (0xA2000000 - (size_t) CYG_LABEL_NAME (__heap1))
28
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.