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/*==========================================================================
//
//      ea2468_misc.c
//
//      HAL misc board support code for EA LPC2468 OEM board
//
//==========================================================================
// ####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later
// version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License
// along with eCos; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
//
// As a special exception, if other files instantiate templates or use
// macros or inline functions from this file, or you compile this file
// and link it with other works to produce a work based on this file,
// this file does not by itself cause the resulting work to be covered by
// the GNU General Public License. However the source code for this file
// must still be made available in accordance with section (3) of the GNU
// General Public License v2.
//
// This exception does not invalidate any other reasons why a work based
// on this file might be covered by the GNU General Public License.
// -------------------------------------------
// ####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Uwe Kindler
// Contributors: Uwe Kindler
// Date:         2008-06-15
// Purpose:      HAL board support
// Description:  Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
 
//===========================================================================
//                               INCLUDES
//===========================================================================
#include <pkgconf/hal.h>
#include <pkgconf/hal_arm_lpc24xx_ea2468.h>
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_io.h>             // IO macros
 
#include <cyg/infra/cyg_type.h>         // base types
#include <cyg/infra/cyg_ass.h>          // assertion macros
#include <cyg/hal/var_io.h>
#include <cyg/hal/plf_io.h>
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
 
#ifdef CYGPKG_REDBOOT
#include <redboot.h>
#endif
 
 
//===========================================================================
//                               DEFINES
//===========================================================================
#define SCB_BASE   CYGARC_HAL_LPC24XX_REG_SCB_BASE
#define EMC_BASE   CYGARC_HAL_LPC24XX_REG_EMC_BASE
#define PIN_BASE   CYGARC_HAL_LPC24XX_REG_PIN_BASE
#define IO_BASE    CYGARC_HAL_LPC24XX_REG_IO_BASE
#define FIO_BASE   CYGARC_HAL_LPC24XX_REG_FIO_BASE
#define SDRAM_BASE 0xA0000000
 
extern void cyg_hal_plf_serial_init(void);
 
 
//===========================================================================
// Initialize communication channels
//===========================================================================
void cyg_hal_plf_comms_init(void)
{
    static int initialized = 0;
 
    if (initialized)
        return;
    initialized = 1;
 
    cyg_hal_plf_serial_init();
}
 
 
//===========================================================================
// Finalize hardware initialisation of platform
//===========================================================================
void hal_plf_hardware_init(void)
{
 
}
 
 
//===========================================================================
// hal_gpio_init 
//===========================================================================
void hal_gpio_init(void)
{
    //
    // Enable UART0 pins
    //
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL0, 0x00000050);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL1, 0);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL2, 0);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL3, 0);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x30003fff);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL10,0);
 
    HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0DIR, 0);
    HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1DIR, 0);
    HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0SET, 0xffffffff);
    HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1SET, 0xffffffff);
 
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0DIR, 0);
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1DIR, 0);
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2DIR, 0);
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3DIR, 0);
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4DIR, 0);
 
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0SET, 0xffffffff);
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1SET, 0xffffffff);
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2SET, 0xffffffff);
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3SET, 0xffffffff);
    HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4SET, 0xffffffff);
}
 
 
//===========================================================================
// hal_pll_init - initialize pll and all clocks
//===========================================================================
void hal_pll_init(void)
{
    cyg_uint32 regval;
 
    HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
    if (regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC)
    {
        //
        // Enable PLL, disconnected
        //
        HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
                          CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);
        HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
        HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
    }
 
    //
    // Disable PLL, disconnected
        //
        HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,  0x00);
        HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
        HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
 
    //
    // Enables main oscillator and wait until it is usable
    //
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS,
                     CYGARC_HAL_LPC24XX_REG_SCS_OSCEN);
    do
    {
        HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS, regval);
    } while (!(regval & CYGARC_HAL_LPC24XX_REG_SCS_OSCSTAT));
 
    //
    // select main OSC, 12MHz, as the PLL clock source 
    //
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CLKSRCSEL,
                     CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_MAIN);
 
    //
    // Configure PLL multiplier and pre divider according to
    // configuration values
    //                 
    regval = ((CYGNUM_HAL_ARM_LPC24XX_PLL_MUL - 1) |
              (CYGNUM_HAL_ARM_LPC24XX_PLL_DIV - 1) << 16);
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCFG,  regval);
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
        HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
 
    //
    // Enable PLL, disconnected
    //
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
                     CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
 
    //
    // Set CPU clock divider
    //
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,
                     CYGNUM_HAL_ARM_LPC24XX_CPU_CLK_DIV - 1);
 
    //
    // Set USB clock divider
    //
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,
                     CYGNUM_HAL_ARM_LPC24XX_USB_CLK_DIV - 1);
 
    //
    // Check lock bit status
    //
    do
    {
        HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
    } while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLOCK));
 
    //
    // Enable PLL and connect
    //
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
                     CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE |
                     CYGARC_HAL_LPC24XX_REG_PLLCON_PLLC);
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
 
    //
    // Check connect bit status
    //
    do
    {
        HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
    } while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC));
 
    //
    // entry for JTAG debugger- enable this while loop as a stop for
    // the JTAG debugger - the JTAG debugger only works after the PLL is
    // initialized properly
    //
    /*while (1)
    {
    }*/
}
 
 
//===========================================================================
// hal_mem_init - initialize external memory interface
//===========================================================================
void hal_mem_init(void)
{
    volatile unsigned int i;
    volatile unsigned int dummy;
    volatile cyg_uint32   regval;
 
    //
    // Enable external memory interface
    //
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMC_CTRL,
                     CYGARC_HAL_LPC24XX_REG_EMC_CTRL_EN);
    hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_EMC, 1);
 
    //
    // Setup pin functions
    //
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0x50000000);
#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x55010115);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x55555555);
#else
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x05050555);
#endif
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0x55555555);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0x55555555);
    HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0x50555555);
 
#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)  
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP,    1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS,   3);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX,  5);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR,   1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL,   5);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR,    1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC,    5);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC,   5);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR,   5);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD,   1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD,   1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,
                     0x00000202);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
                     0x00005480);
#else
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP,    2);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS,   3);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX,  7);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR,   2);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL,   5);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR,    1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC,    5);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC,   5);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR,   7);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD,   1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD,   2);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,
                     0x00000303);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
                     0x00000680);
#endif
 
    //  
    // Wait 100 ms and then send command: NOP
    //
    HAL_DELAY_US(100000);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
                     0x00000183);
 
    //
    // wait 200 ms and then send command: PRECHARGE-ALL, shortest
    // possible refresh period
    //
    HAL_DELAY_US(200000);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
                     0x00000103);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH,
                     0x00000002);
 
    //
    // wait 128 ABH clock cycles
    //
    for(i = 0; i < 64; i++)
    {
        asm volatile(" nop");
    }
 
    //  
    // Set correct refresh period and the send command MODE
    //
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH, 28);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
                     0x00000083);
 
    //
    // Set mode register in SDRAM
    //
#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
    dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x22 << 11)));
#else
    dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x33 << 12)));
#endif
 
    //
    //Send command: NORMAL, enable buffer and wait for 1 second
    //
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
                     0x00000000);
    HAL_READ_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, regval);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
                     regval | 0x00080000);
    HAL_DELAY_US(1000);
 
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN0, 0x2);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN0, 0x2);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD0,   0x1f);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE0, 0x1f);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR0,   0x1f);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN0, 0xf);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG0,
                     0x00000081);
 
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN1, 0x2);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN1, 0x2);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD1,   0x8);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE1, 0x1f);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR1,   0x8);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN1, 0xf);
    HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG1,
                     0x00000080);
}
 
 
//===========================================================================
// hal_plf_startup
//===========================================================================
void hal_plf_startup(void)
{
    hal_pll_init();
 
    //
    // Set clock speed of all peripherals to reset value (CPU speed / 4)
    //
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL0, 0x00000000);
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL1, 0x00000000);
 
    //
    // Setup memory acceleration module
    //
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMCR, 0);
    HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMTIM, 4);
 
    hal_gpio_init();
    HAL_DELAY_US(20000);
    hal_mem_init();
}
 
 
//===========================================================================
// hal_lpc2xxx_set_leds
//===========================================================================
void hal_lpc24xx_set_leds (int mask)
{
    //
    // implement function for setting diagnostic leds
    //
}
 
 
#ifdef CYGPKG_DEVS_CAN_LPC2XXX
//===========================================================================
// Configure CAN pins
//===========================================================================
void hal_lpc_can_init(cyg_uint8 can_chan_no)
{
    CYG_ASSERT(can_chan_no < 2, "CAN channel number out of bounds");
 
    switch (can_chan_no)
    {
        case 0:
             hal_set_pin_function(0, 0, 1); // RD1
             hal_set_pin_function(0, 1, 1); // TD1
             hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_CAN1, 1);
             break;
 
        case 1:
             hal_set_pin_function(0, 4, 2); // RD2
             hal_set_pin_function(0, 5, 2); // TD2
             hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_CAN2, 1);
             break;
    }
}
#endif // #ifdef CYGPKG_DEVS_CAN_LPC2XXX
 
//--------------------------------------------------------------------------
// EOF ea2468_misc.c

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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [lpc24xx/] [ea2468/] [current/] [src/] [ea2468_misc.c] - Blame information for rev 856

Line No.	Rev	Author	Line
1	786	skrzyp	`/*==========================================================================`
2			`//`
3			`// ea2468_misc.c`
4			`//`
5			`// HAL misc board support code for EA LPC2468 OEM board`
6			`//`
7			`//==========================================================================`
8			`// ####ECOSGPLCOPYRIGHTBEGIN####`
9			`// -------------------------------------------`
10			`// This file is part of eCos, the Embedded Configurable Operating System.`
11			`// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.`
12			`//`
13			`// eCos is free software; you can redistribute it and/or modify it under`
14			`// the terms of the GNU General Public License as published by the Free`
15			`// Software Foundation; either version 2 or (at your option) any later`
16			`// version.`
17			`//`
18			`// eCos is distributed in the hope that it will be useful, but WITHOUT`
19			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
20			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
21			`// for more details.`
22			`//`
23			`// You should have received a copy of the GNU General Public License`
24			`// along with eCos; if not, write to the Free Software Foundation, Inc.,`
25			`// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
26			`//`
27			`// As a special exception, if other files instantiate templates or use`
28			`// macros or inline functions from this file, or you compile this file`
29			`// and link it with other works to produce a work based on this file,`
30			`// this file does not by itself cause the resulting work to be covered by`
31			`// the GNU General Public License. However the source code for this file`
32			`// must still be made available in accordance with section (3) of the GNU`
33			`// General Public License v2.`
34			`//`
35			`// This exception does not invalidate any other reasons why a work based`
36			`// on this file might be covered by the GNU General Public License.`
37			`// -------------------------------------------`
38			`// ####ECOSGPLCOPYRIGHTEND####`
39			`//==========================================================================`
40			`//#####DESCRIPTIONBEGIN####`
41			`//`
42			`// Author(s): Uwe Kindler`
43			`// Contributors: Uwe Kindler`
44			`// Date: 2008-06-15`
45			`// Purpose: HAL board support`
46			`// Description: Implementations of HAL board interfaces`
47			`//`
48			`//####DESCRIPTIONEND####`
49			`//`
50			`//========================================================================*/`
51
52
53			`//===========================================================================`
54			`// INCLUDES`
55			`//===========================================================================`
56			`#include <pkgconf/hal.h>`
57			`#include <pkgconf/hal_arm_lpc24xx_ea2468.h>`
58			`#include <cyg/hal/hal_diag.h>`
59			`#include <cyg/hal/hal_io.h> // IO macros`
60
61			`#include <cyg/infra/cyg_type.h> // base types`
62			`#include <cyg/infra/cyg_ass.h> // assertion macros`
63			`#include <cyg/hal/var_io.h>`
64			`#include <cyg/hal/plf_io.h>`
65			`#include <pkgconf/hal.h>`
66
67			`#include <cyg/hal/hal_arch.h>`
68			`#include <cyg/hal/hal_intr.h>`
69
70			`#ifdef CYGPKG_REDBOOT`
71			`#include <redboot.h>`
72			`#endif`
73
74
75			`//===========================================================================`
76			`// DEFINES`
77			`//===========================================================================`
78			`#define SCB_BASE CYGARC_HAL_LPC24XX_REG_SCB_BASE`
79			`#define EMC_BASE CYGARC_HAL_LPC24XX_REG_EMC_BASE`
80			`#define PIN_BASE CYGARC_HAL_LPC24XX_REG_PIN_BASE`
81			`#define IO_BASE CYGARC_HAL_LPC24XX_REG_IO_BASE`
82			`#define FIO_BASE CYGARC_HAL_LPC24XX_REG_FIO_BASE`
83			`#define SDRAM_BASE 0xA0000000`
84
85			`extern void cyg_hal_plf_serial_init(void);`
86
87
88			`//===========================================================================`
89			`// Initialize communication channels`
90			`//===========================================================================`
91			`void cyg_hal_plf_comms_init(void)`
92			`{`
93			`static int initialized = 0;`
94
95			`if (initialized)`
96			`return;`
97			`initialized = 1;`
98
99			`cyg_hal_plf_serial_init();`
100			`}`
101
102
103			`//===========================================================================`
104			`// Finalize hardware initialisation of platform`
105			`//===========================================================================`
106			`void hal_plf_hardware_init(void)`
107			`{`
108
109			`}`
110
111
112			`//===========================================================================`
113			`// hal_gpio_init`
114			`//===========================================================================`
115			`void hal_gpio_init(void)`
116			`{`
117			`//`
118			`// Enable UART0 pins`
119			`//`
120			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL0, 0x00000050);`
121			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL1, 0);`
122			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL2, 0);`
123			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL3, 0);`
124			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0);`
125			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0);`
126			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0);`
127			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x30003fff);`
128			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0);`
129			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0);`
130			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL10,0);`
131
132			`HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0DIR, 0);`
133			`HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1DIR, 0);`
134			`HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0SET, 0xffffffff);`
135			`HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1SET, 0xffffffff);`
136
137			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0DIR, 0);`
138			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1DIR, 0);`
139			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2DIR, 0);`
140			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3DIR, 0);`
141			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4DIR, 0);`
142
143			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0SET, 0xffffffff);`
144			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1SET, 0xffffffff);`
145			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2SET, 0xffffffff);`
146			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3SET, 0xffffffff);`
147			`HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4SET, 0xffffffff);`
148			`}`
149
150
151			`//===========================================================================`
152			`// hal_pll_init - initialize pll and all clocks`
153			`//===========================================================================`
154			`void hal_pll_init(void)`
155			`{`
156			`cyg_uint32 regval;`
157
158			`HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);`
159			`if (regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC)`
160			`{`
161			`//`
162			`// Enable PLL, disconnected`
163			`//`
164			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,`
165			`CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);`
166			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);`
167			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);`
168			`}`
169
170			`//`
171			`// Disable PLL, disconnected`
172			`//`
173			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON, 0x00);`
174			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);`
175			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);`
176
177			`//`
178			`// Enables main oscillator and wait until it is usable`
179			`//`
180			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS,`
181			`CYGARC_HAL_LPC24XX_REG_SCS_OSCEN);`
182			`do`
183			`{`
184			`HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS, regval);`
185			`} while (!(regval & CYGARC_HAL_LPC24XX_REG_SCS_OSCSTAT));`
186
187			`//`
188			`// select main OSC, 12MHz, as the PLL clock source`
189			`//`
190			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CLKSRCSEL,`
191			`CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_MAIN);`
192
193			`//`
194			`// Configure PLL multiplier and pre divider according to`
195			`// configuration values`
196			`//`
197			`regval = ((CYGNUM_HAL_ARM_LPC24XX_PLL_MUL - 1) \|`
198			`(CYGNUM_HAL_ARM_LPC24XX_PLL_DIV - 1) << 16);`
199			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCFG, regval);`
200			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);`
201			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);`
202
203			`//`
204			`// Enable PLL, disconnected`
205			`//`
206			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,`
207			`CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);`
208			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);`
209			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);`
210
211			`//`
212			`// Set CPU clock divider`
213			`//`
214			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,`
215			`CYGNUM_HAL_ARM_LPC24XX_CPU_CLK_DIV - 1);`
216
217			`//`
218			`// Set USB clock divider`
219			`//`
220			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,`
221			`CYGNUM_HAL_ARM_LPC24XX_USB_CLK_DIV - 1);`
222
223			`//`
224			`// Check lock bit status`
225			`//`
226			`do`
227			`{`
228			`HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);`
229			`} while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLOCK));`
230
231			`//`
232			`// Enable PLL and connect`
233			`//`
234			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,`
235			`CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE \|`
236			`CYGARC_HAL_LPC24XX_REG_PLLCON_PLLC);`
237			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);`
238			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);`
239
240			`//`
241			`// Check connect bit status`
242			`//`
243			`do`
244			`{`
245			`HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);`
246			`} while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC));`
247
248			`//`
249			`// entry for JTAG debugger- enable this while loop as a stop for`
250			`// the JTAG debugger - the JTAG debugger only works after the PLL is`
251			`// initialized properly`
252			`//`
253			`/*while (1)`
254			`{`
255			`}*/`
256			`}`
257
258
259			`//===========================================================================`
260			`// hal_mem_init - initialize external memory interface`
261			`//===========================================================================`
262			`void hal_mem_init(void)`
263			`{`
264			`volatile unsigned int i;`
265			`volatile unsigned int dummy;`
266			`volatile cyg_uint32 regval;`
267
268			`//`
269			`// Enable external memory interface`
270			`//`
271			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMC_CTRL,`
272			`CYGARC_HAL_LPC24XX_REG_EMC_CTRL_EN);`
273			`hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_EMC, 1);`
274
275			`//`
276			`// Setup pin functions`
277			`//`
278			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0x50000000);`
279			`#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)`
280			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x55010115);`
281			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x55555555);`
282			`#else`
283			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x05050555);`
284			`#endif`
285			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0x55555555);`
286			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0x55555555);`
287			`HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0x50555555);`
288
289			`#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)`
290			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 1);`
291			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3);`
292			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 5);`
293			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 1);`
294			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5);`
295			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1);`
296			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5);`
297			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5);`
298			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 5);`
299			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1);`
300			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 1);`
301			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);`
302			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,`
303			`0x00000202);`
304			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,`
305			`0x00005480);`
306			`#else`
307			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 2);`
308			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3);`
309			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 7);`
310			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 2);`
311			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5);`
312			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1);`
313			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5);`
314			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5);`
315			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 7);`
316			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1);`
317			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 2);`
318			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);`
319			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,`
320			`0x00000303);`
321			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,`
322			`0x00000680);`
323			`#endif`
324
325			`//`
326			`// Wait 100 ms and then send command: NOP`
327			`//`
328			`HAL_DELAY_US(100000);`
329			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,`
330			`0x00000183);`
331
332			`//`
333			`// wait 200 ms and then send command: PRECHARGE-ALL, shortest`
334			`// possible refresh period`
335			`//`
336			`HAL_DELAY_US(200000);`
337			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,`
338			`0x00000103);`
339			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH,`
340			`0x00000002);`
341
342			`//`
343			`// wait 128 ABH clock cycles`
344			`//`
345			`for(i = 0; i < 64; i++)`
346			`{`
347			`asm volatile(" nop");`
348			`}`
349
350			`//`
351			`// Set correct refresh period and the send command MODE`
352			`//`
353			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH, 28);`
354			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,`
355			`0x00000083);`
356
357			`//`
358			`// Set mode register in SDRAM`
359			`//`
360			`#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)`
361			`dummy = ((volatile unsigned int)(SDRAM_BASE \| (0x22 << 11)));`
362			`#else`
363			`dummy = ((volatile unsigned int)(SDRAM_BASE \| (0x33 << 12)));`
364			`#endif`
365
366			`//`
367			`//Send command: NORMAL, enable buffer and wait for 1 second`
368			`//`
369			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,`
370			`0x00000000);`
371			`HAL_READ_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, regval);`
372			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,`
373			`regval \| 0x00080000);`
374			`HAL_DELAY_US(1000);`
375
376			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN0, 0x2);`
377			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN0, 0x2);`
378			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD0, 0x1f);`
379			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE0, 0x1f);`
380			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR0, 0x1f);`
381			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN0, 0xf);`
382			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG0,`
383			`0x00000081);`
384
385			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN1, 0x2);`
386			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN1, 0x2);`
387			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD1, 0x8);`
388			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE1, 0x1f);`
389			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR1, 0x8);`
390			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN1, 0xf);`
391			`HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG1,`
392			`0x00000080);`
393			`}`
394
395
396			`//===========================================================================`
397			`// hal_plf_startup`
398			`//===========================================================================`
399			`void hal_plf_startup(void)`
400			`{`
401			`hal_pll_init();`
402
403			`//`
404			`// Set clock speed of all peripherals to reset value (CPU speed / 4)`
405			`//`
406			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL0, 0x00000000);`
407			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL1, 0x00000000);`
408
409			`//`
410			`// Setup memory acceleration module`
411			`//`
412			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMCR, 0);`
413			`HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMTIM, 4);`
414
415			`hal_gpio_init();`
416			`HAL_DELAY_US(20000);`
417			`hal_mem_init();`
418			`}`
419
420
421			`//===========================================================================`
422			`// hal_lpc2xxx_set_leds`
423			`//===========================================================================`
424			`void hal_lpc24xx_set_leds (int mask)`
425			`{`
426			`//`
427			`// implement function for setting diagnostic leds`
428			`//`
429			`}`
430
431
432			`#ifdef CYGPKG_DEVS_CAN_LPC2XXX`
433			`//===========================================================================`
434			`// Configure CAN pins`
435			`//===========================================================================`
436			`void hal_lpc_can_init(cyg_uint8 can_chan_no)`
437			`{`
438			`CYG_ASSERT(can_chan_no < 2, "CAN channel number out of bounds");`
439
440			`switch (can_chan_no)`
441			`{`
442			`case 0:`
443			`hal_set_pin_function(0, 0, 1); // RD1`
444			`hal_set_pin_function(0, 1, 1); // TD1`
445			`hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_CAN1, 1);`
446			`break;`
447
448			`case 1:`
449			`hal_set_pin_function(0, 4, 2); // RD2`
450			`hal_set_pin_function(0, 5, 2); // TD2`
451			`hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_CAN2, 1);`
452			`break;`
453			`}`
454			`}`
455			`#endif // #ifdef CYGPKG_DEVS_CAN_LPC2XXX`
456
457			`//--------------------------------------------------------------------------`
458			`// EOF ea2468_misc.c`