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/*==========================================================================
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//
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// ea2468_misc.c
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//
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// HAL misc board support code for EA LPC2468 OEM board
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Uwe Kindler
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// Contributors: Uwe Kindler
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// Date: 2008-06-15
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// Purpose: HAL board support
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// Description: Implementations of HAL board interfaces
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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//===========================================================================
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// INCLUDES
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//===========================================================================
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#include <pkgconf/hal.h>
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#include <pkgconf/hal_arm_lpc24xx_ea2468.h>
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/hal_io.h> // IO macros
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#include <cyg/infra/cyg_type.h> // base types
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/hal/var_io.h>
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#include <cyg/hal/plf_io.h>
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#include <pkgconf/hal.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/hal_intr.h>
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#ifdef CYGPKG_REDBOOT
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#include <redboot.h>
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#endif
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//===========================================================================
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// DEFINES
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//===========================================================================
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#define SCB_BASE CYGARC_HAL_LPC24XX_REG_SCB_BASE
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#define EMC_BASE CYGARC_HAL_LPC24XX_REG_EMC_BASE
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#define PIN_BASE CYGARC_HAL_LPC24XX_REG_PIN_BASE
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#define IO_BASE CYGARC_HAL_LPC24XX_REG_IO_BASE
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#define FIO_BASE CYGARC_HAL_LPC24XX_REG_FIO_BASE
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#define SDRAM_BASE 0xA0000000
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extern void cyg_hal_plf_serial_init(void);
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//===========================================================================
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// Initialize communication channels
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//===========================================================================
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void cyg_hal_plf_comms_init(void)
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{
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static int initialized = 0;
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if (initialized)
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return;
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initialized = 1;
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cyg_hal_plf_serial_init();
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}
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//===========================================================================
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// Finalize hardware initialisation of platform
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//===========================================================================
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void hal_plf_hardware_init(void)
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{
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}
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//===========================================================================
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// hal_gpio_init
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//===========================================================================
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void hal_gpio_init(void)
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{
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//
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// Enable UART0 pins
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//
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL0, 0x00000050);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL1, 0);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL2, 0);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL3, 0);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x30003fff);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL10,0);
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HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0DIR, 0);
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HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1DIR, 0);
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HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO0SET, 0xffffffff);
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HAL_WRITE_UINT32(IO_BASE + CYGARC_HAL_LPC24XX_REG_IO1SET, 0xffffffff);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0DIR, 0);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1DIR, 0);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2DIR, 0);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3DIR, 0);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4DIR, 0);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO0SET, 0xffffffff);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO1SET, 0xffffffff);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO2SET, 0xffffffff);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO3SET, 0xffffffff);
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HAL_WRITE_UINT32(FIO_BASE + CYGARC_HAL_LPC24XX_REG_FIO4SET, 0xffffffff);
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}
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//===========================================================================
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// hal_pll_init - initialize pll and all clocks
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//===========================================================================
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void hal_pll_init(void)
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{
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cyg_uint32 regval;
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HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
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if (regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC)
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{
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//
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// Enable PLL, disconnected
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//
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
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CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
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}
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//
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// Disable PLL, disconnected
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//
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON, 0x00);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
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//
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// Enables main oscillator and wait until it is usable
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//
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS,
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CYGARC_HAL_LPC24XX_REG_SCS_OSCEN);
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do
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{
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HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_SCS, regval);
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} while (!(regval & CYGARC_HAL_LPC24XX_REG_SCS_OSCSTAT));
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//
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// select main OSC, 12MHz, as the PLL clock source
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//
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CLKSRCSEL,
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CYGARC_HAL_LPC24XX_REG_CLKSRCSEL_MAIN);
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//
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// Configure PLL multiplier and pre divider according to
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// configuration values
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//
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regval = ((CYGNUM_HAL_ARM_LPC24XX_PLL_MUL - 1) |
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(CYGNUM_HAL_ARM_LPC24XX_PLL_DIV - 1) << 16);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCFG, regval);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
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//
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// Enable PLL, disconnected
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//
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
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CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
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//
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// Set CPU clock divider
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//
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,
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CYGNUM_HAL_ARM_LPC24XX_CPU_CLK_DIV - 1);
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//
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// Set USB clock divider
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//
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_CCLKCFG,
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CYGNUM_HAL_ARM_LPC24XX_USB_CLK_DIV - 1);
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//
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// Check lock bit status
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//
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do
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{
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HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
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} while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLOCK));
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//
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// Enable PLL and connect
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//
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLCON,
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CYGARC_HAL_LPC24XX_REG_PLLCON_PLLE |
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CYGARC_HAL_LPC24XX_REG_PLLCON_PLLC);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0xaa);
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HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLFEED, 0x55);
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//
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// Check connect bit status
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//
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do
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{
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HAL_READ_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PLLSTAT, regval);
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} while(!(regval & CYGARC_HAL_LPC24XX_REG_PLLSTAT_PLLC));
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//
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// entry for JTAG debugger- enable this while loop as a stop for
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// the JTAG debugger - the JTAG debugger only works after the PLL is
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// initialized properly
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//
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/*while (1)
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{
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}*/
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}
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//===========================================================================
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// hal_mem_init - initialize external memory interface
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//===========================================================================
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void hal_mem_init(void)
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{
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volatile unsigned int i;
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volatile unsigned int dummy;
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volatile cyg_uint32 regval;
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//
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// Enable external memory interface
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//
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMC_CTRL,
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CYGARC_HAL_LPC24XX_REG_EMC_CTRL_EN);
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hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_EMC, 1);
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//
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// Setup pin functions
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//
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL4, 0x50000000);
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#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x55010115);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL7, 0x55555555);
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#else
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL5, 0x05050555);
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#endif
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL6, 0x55555555);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL8, 0x55555555);
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HAL_WRITE_UINT32(PIN_BASE + CYGARC_HAL_LPC24XX_REG_PINSEL9, 0x50555555);
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#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 1);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 5);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 1);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 5);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 1);
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);
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|
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HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,
|
303 |
|
|
0x00000202);
|
304 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
|
305 |
|
|
0x00005480);
|
306 |
|
|
#else
|
307 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RP, 2);
|
308 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RAS, 3);
|
309 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_SREX, 7);
|
310 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_APR, 2);
|
311 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_DAL, 5);
|
312 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_WR, 1);
|
313 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RC, 5);
|
314 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RFC, 5);
|
315 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_XSR, 7);
|
316 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RRD, 1);
|
317 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_MRD, 2);
|
318 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RDCFG, 1);
|
319 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_RASCAS0,
|
320 |
|
|
0x00000303);
|
321 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
|
322 |
|
|
0x00000680);
|
323 |
|
|
#endif
|
324 |
|
|
|
325 |
|
|
//
|
326 |
|
|
// Wait 100 ms and then send command: NOP
|
327 |
|
|
//
|
328 |
|
|
HAL_DELAY_US(100000);
|
329 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
|
330 |
|
|
0x00000183);
|
331 |
|
|
|
332 |
|
|
//
|
333 |
|
|
// wait 200 ms and then send command: PRECHARGE-ALL, shortest
|
334 |
|
|
// possible refresh period
|
335 |
|
|
//
|
336 |
|
|
HAL_DELAY_US(200000);
|
337 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
|
338 |
|
|
0x00000103);
|
339 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH,
|
340 |
|
|
0x00000002);
|
341 |
|
|
|
342 |
|
|
//
|
343 |
|
|
// wait 128 ABH clock cycles
|
344 |
|
|
//
|
345 |
|
|
for(i = 0; i < 64; i++)
|
346 |
|
|
{
|
347 |
|
|
asm volatile(" nop");
|
348 |
|
|
}
|
349 |
|
|
|
350 |
|
|
//
|
351 |
|
|
// Set correct refresh period and the send command MODE
|
352 |
|
|
//
|
353 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_REFRESH, 28);
|
354 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
|
355 |
|
|
0x00000083);
|
356 |
|
|
|
357 |
|
|
//
|
358 |
|
|
// Set mode register in SDRAM
|
359 |
|
|
//
|
360 |
|
|
#if defined(CYGHWR_HAL_ARM_LPC24XX_EA2468_DATA_BUS_WIDTH_32)
|
361 |
|
|
dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x22 << 11)));
|
362 |
|
|
#else
|
363 |
|
|
dummy = *((volatile unsigned int*)(SDRAM_BASE | (0x33 << 12)));
|
364 |
|
|
#endif
|
365 |
|
|
|
366 |
|
|
//
|
367 |
|
|
//Send command: NORMAL, enable buffer and wait for 1 second
|
368 |
|
|
//
|
369 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONTROL,
|
370 |
|
|
0x00000000);
|
371 |
|
|
HAL_READ_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0, regval);
|
372 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCD_CONFIG0,
|
373 |
|
|
regval | 0x00080000);
|
374 |
|
|
HAL_DELAY_US(1000);
|
375 |
|
|
|
376 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN0, 0x2);
|
377 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN0, 0x2);
|
378 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD0, 0x1f);
|
379 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE0, 0x1f);
|
380 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR0, 0x1f);
|
381 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN0, 0xf);
|
382 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG0,
|
383 |
|
|
0x00000081);
|
384 |
|
|
|
385 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITW_EN1, 0x2);
|
386 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITO_EN1, 0x2);
|
387 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITRD1, 0x8);
|
388 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITPAGE1, 0x1f);
|
389 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITWR1, 0x8);
|
390 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_WAITTURN1, 0xf);
|
391 |
|
|
HAL_WRITE_UINT32(EMC_BASE + CYGARC_HAL_LPC24XX_REG_EMCS_CONFIG1,
|
392 |
|
|
0x00000080);
|
393 |
|
|
}
|
394 |
|
|
|
395 |
|
|
|
396 |
|
|
//===========================================================================
|
397 |
|
|
// hal_plf_startup
|
398 |
|
|
//===========================================================================
|
399 |
|
|
void hal_plf_startup(void)
|
400 |
|
|
{
|
401 |
|
|
hal_pll_init();
|
402 |
|
|
|
403 |
|
|
//
|
404 |
|
|
// Set clock speed of all peripherals to reset value (CPU speed / 4)
|
405 |
|
|
//
|
406 |
|
|
HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL0, 0x00000000);
|
407 |
|
|
HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_PCLKSEL1, 0x00000000);
|
408 |
|
|
|
409 |
|
|
//
|
410 |
|
|
// Setup memory acceleration module
|
411 |
|
|
//
|
412 |
|
|
HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMCR, 0);
|
413 |
|
|
HAL_WRITE_UINT32(SCB_BASE + CYGARC_HAL_LPC24XX_REG_MAMTIM, 4);
|
414 |
|
|
|
415 |
|
|
hal_gpio_init();
|
416 |
|
|
HAL_DELAY_US(20000);
|
417 |
|
|
hal_mem_init();
|
418 |
|
|
}
|
419 |
|
|
|
420 |
|
|
|
421 |
|
|
//===========================================================================
|
422 |
|
|
// hal_lpc2xxx_set_leds
|
423 |
|
|
//===========================================================================
|
424 |
|
|
void hal_lpc24xx_set_leds (int mask)
|
425 |
|
|
{
|
426 |
|
|
//
|
427 |
|
|
// implement function for setting diagnostic leds
|
428 |
|
|
//
|
429 |
|
|
}
|
430 |
|
|
|
431 |
|
|
|
432 |
|
|
#ifdef CYGPKG_DEVS_CAN_LPC2XXX
|
433 |
|
|
//===========================================================================
|
434 |
|
|
// Configure CAN pins
|
435 |
|
|
//===========================================================================
|
436 |
|
|
void hal_lpc_can_init(cyg_uint8 can_chan_no)
|
437 |
|
|
{
|
438 |
|
|
CYG_ASSERT(can_chan_no < 2, "CAN channel number out of bounds");
|
439 |
|
|
|
440 |
|
|
switch (can_chan_no)
|
441 |
|
|
{
|
442 |
|
|
case 0:
|
443 |
|
|
hal_set_pin_function(0, 0, 1); // RD1
|
444 |
|
|
hal_set_pin_function(0, 1, 1); // TD1
|
445 |
|
|
hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_CAN1, 1);
|
446 |
|
|
break;
|
447 |
|
|
|
448 |
|
|
case 1:
|
449 |
|
|
hal_set_pin_function(0, 4, 2); // RD2
|
450 |
|
|
hal_set_pin_function(0, 5, 2); // TD2
|
451 |
|
|
hal_lpc_set_power(CYNUM_HAL_LPC24XX_PCONP_CAN2, 1);
|
452 |
|
|
break;
|
453 |
|
|
}
|
454 |
|
|
}
|
455 |
|
|
#endif // #ifdef CYGPKG_DEVS_CAN_LPC2XXX
|
456 |
|
|
|
457 |
|
|
//--------------------------------------------------------------------------
|
458 |
|
|
// EOF ea2468_misc.c
|