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#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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#define CYGONCE_HAL_PLATFORM_SETUP_H
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/*=============================================================================
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//
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// hal_platform_setup.h
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//
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// Platform specific support for HAL (assembly code)
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Sergei Gavrikov
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// Contributors: Sergei Gavrikov
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// Date: 2008-08-31
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// Purpose: Olimex LPC-E2294 platform specific support routines
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// Description:
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// Usage: #include <cyg/hal/hal_platform_setup.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/system.h>
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#include <cyg/hal/var_io.h>
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// There are no diagnostic leds on the board, but there is a LCD there
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// with BACKLIGHT feature. No way to display some info on LCD here, but
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// we can drive by BACKLIGHT put to a cathode a static signal.
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.macro _led_init
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
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ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0DIR]
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orr r1,r1,#(1<<10)
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0DIR]
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.endm // _led_init
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.macro _led x
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
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ldr r1,=(1<<10)
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0CLR]
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ldr r1,=((\x & 1)<<10)
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0SET]
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.endm // _led
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.macro _pll_init
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
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mov r2,#0xAA
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mov r3,#0x55
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// enable PLL
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mov r1,#1
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]
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mov r1,#(0x20 | (CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL - 1))
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCFG]
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// update PLL registers
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str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
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str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
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// wait for it to lock
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1:
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ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLSTAT]
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ands r1,r1,#(1<<10)
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beq 1b
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// connect PLL
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mov r1,#3
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]
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// update PLL registers
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str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
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str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
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.endm // _pll_init
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.macro _mem_init
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// copy first 64 bytes from ROM to on-chip RAM
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mov r0,#0
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mov r1,#0x40000000
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mov r2,#0x40
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1:
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ldr r3,[r0,#4]!
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str r3,[r1,#4]!
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cmp r0,r2
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bne 1b
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
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mov r1,#2 // interrupt vector table is mapped to RAM
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str r1, [r0,#CYGARC_HAL_LPC2XXX_REG_MEMMAP]
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// flash timings
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mov r1,#4
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_MAMTIM]
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mov r1,#2 // 2, full MAM
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_MAMCR]
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// External memory interface depends on the bank width (32, 16 or 8 bit
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// selected via MW bits in corresponding BCFG register). Furthermore,
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// choice of the memory chip(s) will require an adequate setup of RBLE
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// bit in BCFG register, too. RBLE = 0 in case of 8-bit based external
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// memories, while memory chips capable of accepting 16 or 32 bit wide
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// data will work with RBLE = 1.
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//
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// BANK0: 4M FLASH
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// TE28F320C3BD70 (1024Kx32 x 1, 70nS)
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG0
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ldr r1,= (0x3 << 0) /* IDCY=3, idle timing */\
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| (0x4 << 5) /* WST1=4, read timing */\
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| (0x1 << 10) /* RBLE=1 */\
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| (0x6 << 11) /* WST2=6, write timing */\
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| (0x1 << 28) /* MW=1, 16-bits */
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str r1,[r0]
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// BANK1: 1M RAM
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// K6R4016V1D (512Kx16 x 2, 10nS)
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG1
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// Warning: changed these timings, you can fall dramatically the eCos
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// kernel performance. Check it then using the eCos 'tm_basic' test.
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ldr r1,= (0x0 << 0) /* IDCY=0, idle cycles */\
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| (0x0 << 5) /* WST1=0, read timing */\
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| (0x1 << 10) /* RBLE=1 */\
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| (0x0 << 11) /* WST2=0, write timing */\
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| (0x2 << 28) /* MW=2, 32-bits */
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str r1,[r0]
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// BANK2: Ethernet
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// CS8900A (8-bit, no interrupt driven mode)
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG2
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ldr r1,= (0x1 << 0) /* IDCY=1, idle cycles */\
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| (0x8 << 5) /* WST1=8, read timing */\
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| (0x1 << 10) /* RBLE=1 */\
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| (0x6 << 11) /* WST2=6, write timing */\
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| (0x0 << 28) /* MW=0, 8-bits */
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str r1,[r0]
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.endm // _mem_init
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.macro _gpio_init
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE
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// Configure P0.15:0 as PIO, but UART0, UART1, EINT2 ('B1' button)
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ldr r1,= (0x1 << 0) /* P0.0 as TxD0 */\
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| (0x1 << 2) /* P0.1 as RxD0 */\
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| (0x1 << 16) /* P0.1 as TxD1 */\
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| (0x1 << 18) /* P0.1 as RxD1 */\
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| (0x2 << 30) /* P0.15 as EINT2 */
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL0]
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// Configure P0.30:16 as PIO, but EINT0 ('B2' button)
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ldr r1,= (0x1 << 0) /* P0.16 as EINT0 */
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL1]
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// GPIO P1.25:16, P3.24 are used as PIO
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ldr r1,= (0x1 << 2) /* P1.31:26 Debug port */\
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| (0x2 << 4) /* D31:0,CS0,OE,BLS0-3 */\
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| (0x1 << 8) /* WE enabled */\
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| (0x1 << 11) /* CS1 enabled */\
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| (0x1 << 14) /* CS2 enabled */\
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| (0x1 << 23) /* A0 enabled */\
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| (0x1 << 24) /* A1 enabled */\
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| (0x7 << 25) /* A23:2 enabled */
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL2]
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.endm // _gpio_init
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#define CYGHWR_LED_MACRO _led \x
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#if defined(CYG_HAL_STARTUP_ROM)
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.macro _setup
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_pll_init
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_mem_init
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_gpio_init
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_led_init
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.endm
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#define CYGSEM_HAL_ROM_RESET_USES_JUMP
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#else
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.macro _setup
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.endm
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#endif // CYG_HAL_STARTUP_ROM
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#define PLATFORM_SETUP1 _setup
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#endif // CYGONCE_HAL_PLATFORM_SETUP_H
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