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skrzyp |
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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#define CYGONCE_HAL_PLATFORM_SETUP_H
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/*=============================================================================
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//
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// hal_platform_setup.h
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//
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// Platform specific support for HAL (assembly code)
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Uwe Kindler
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// Contributors: Uwe Kindler
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// Date: 2007-12-02
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// Purpose: phyCORE-LPC229x platform specific support routines
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// Description:
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// Usage: #include <cyg/hal/hal_platform_setup.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/system.h>
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#include <cyg/hal/var_io.h>
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//===========================================================================*/
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#define LINES (0xFE<<16)
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#define LINE (1<<16)
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.macro _line_init
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// set to GPIO
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE
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ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL2]
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bic r1, r1, #8
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL2]
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// set to output
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
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ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1DIR]
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orr r1,r1,#LINE
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1DIR]
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// turn ON
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ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1PIN]
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bic r1,r1,#LINES
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orr r1,r1,#LINE
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1PIN]
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.endm
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//----------------------------------------------------------------------------
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// The phyCORE Carrier Board HD200 offers a programmable LED at
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// D3 for user implementations. This LED can be connected to port pin
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// P0.8 (TxD1) of the phyCORE-LPC2292/94 which is available via
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// signal GPIO0 (JP17 = closed). A low-level at port pin P0.8 causes the
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// LED to illuminate, LED D3 remains off when writing a high-level to
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// P0.8.
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//
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.macro _led_init
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
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ldr r1,=(1<<8) // GPIO0 pins 8 is LED output
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0DIR]
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.endm
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.macro _led x
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
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ldr r1,=(1<<8)
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0CLR]
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ldr r1,=((\x & 1)<<8)
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0SET]
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.endm
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#define CYGHWR_LED_MACRO _led \x
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//----------------------------------------------------------------------------
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// PLL initialisation
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//
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.macro _pll_init
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
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mov r2,#0xAA
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mov r3,#0x55
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mov r1,#(0x20 | (CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL - 1))
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// load the PLL configuration register
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCFG]
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mov r1,#1
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON] // enable PLL
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// perform validation sequence 0XAA followed by 0x55
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str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
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str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
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1:
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ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLSTAT] // wait for it to lock
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ands r1,r1,#(1<<10)
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beq 1b
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mov r1,#3 // connect PLL
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]
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// perform validation sequence 0XAA followed by 0x55
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str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
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str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
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.endm
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//----------------------------------------------------------------------------
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// External memory and bus initialisation
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//
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.macro _mem_init
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//
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// first map the vector table to internal flash - normally this should be
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// the default value after boot - but we go the safe way here and force
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// the mapping to internal flash (the value for
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// CYGARC_HAL_LPC2XXX_REG_MEMMAP is 1)
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//
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
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mov r1,#1
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str r1, [r0,#CYGARC_HAL_LPC2XXX_REG_MEMMAP]
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//
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// Now its is save to copy the first 64 bytes of flash to RAM
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//
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mov r0,#0
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mov r1,#0x40000000
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mov r2,#0x40
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1:
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ldr r3,[r0,#4]!
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str r3,[r1,#4]!
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cmps r0,r2
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bne 1b
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//
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// Now we can map the vector table to internal SRAM because the SRAM no
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// contains a copy of the vector tablefrom flash (the value for
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// CYGARC_HAL_LPC2XXX_REG_MEMMAP is 2 = SRAM)
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//
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
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// User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
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mov r1,#2
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str r1, [r0,#CYGARC_HAL_LPC2XXX_REG_MEMMAP]
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// 4 processor clocks fetch cycle
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mov r1,#4
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_MAMTIM] // flash timings
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mov r1,#2
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_MAMCR] // enable full MAM
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//
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// Set-up external memory - the main task here is to setup the
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// wait states for the external memory properly
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//
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// Bank Configuration Registers 0-3 (BCFG0-3)
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// [0..3] IDCY: Min. number of idle Cycles <0-15>
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// [4] Reserved
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// [5..9] WST1: Wait States 1 <0-31>
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// [10] RBLE: Read Byte Lane Enable
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// [11..15] WST2: Wait States 2 <0-31>
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// [16..23] Reserved
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// [26] WP: Write Protect
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// [27] BM: Burst ROM
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// [28..29] MW: Memory Width <0=8-bit,1=16-bit,2=32-bit,3=Reserved>
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// [30..31] Reserved
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//
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// enable external parallel bus signals
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE
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// A0..1 enabled, CS0..3, OE, WE, BLS0..3, D0..31, A2..23, JTAG Pins
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ldr r1,=0x0FE149E4
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL2]
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// setup external FLASH wait states
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG0
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ldr r1,=0x20003CE3
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str r1, [r0]
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// setup external SRAM wait states
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG1
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ldr r1,=0x020002483
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str r1, [r0]
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// setup Ethernet chip wait states for /CS2 and /CS3
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG2
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ldr r1,=0x020000C23
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str r1, [r0]
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG3
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ldr r1,=0x020000C23
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str r1, [r0]
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.endm
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.macro _gpio_init
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// enable RX and TX on UART0 and UART1
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE
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ldr r1,=0x00050005
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL0]
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// set pin function to EINT0
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE
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ldr r1,=0x00000001
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL1]
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.endm
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.macro _block
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ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
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ldr r1,=(1<<8)
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str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO0CLR]
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2:
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nop
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b 2
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.endm
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#define PLATFORM_BLOCK _block
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//===========================================================================*/
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#if defined(CYG_HAL_STARTUP_ROM)
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.macro _setup
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_line_init
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_led_init
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_led 1
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_pll_init
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_mem_init
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_gpio_init
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.endm
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#define CYGSEM_HAL_ROM_RESET_USES_JUMP
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#else
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.macro _setup
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.endm
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#endif
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#define PLATFORM_SETUP1 _setup
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//-----------------------------------------------------------------------------
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// end of hal_platform_setup.h
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#endif // CYGONCE_HAL_PLATFORM_SETUP_H
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