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#ifndef CYGONCE_HAL_VAR_IO_H
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#define CYGONCE_HAL_VAR_IO_H
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//=============================================================================
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//
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// var_io.h
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//
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// Variant specific registers
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Ilija Koco <ilijak@siva.com.mk>
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// Contributors:
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// Date: 2006-02-03
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// Purpose: MAC7100 variant specific registers
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// Description: based on freescale's mac7100.h
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// Usage: #include <cyg/hal/var_io.h>
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/hal/plf_io.h>
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#if !defined HAL_IO_MACROS_NO_ADDRESS_MUNGING
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#define HAL_IO_MACROS_NO_ADDRESS_MUNGING 1
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#endif // HAL_IO_MACROS_NO_ADDRESS_MUNGING
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// *********************************************************************
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//
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// INTC Module
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//
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// *********************************************************************
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// Interrupt Controller Definitions
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#define MAC7100_INTC_BASE (0xFC048000)
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#define MAC7100_IPRH_OFFSET (0x0000)
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#define MAC7100_IPRL_OFFSET (0x0004)
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#define MAC7100_IMRH_OFFSET (0x0008)
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#define MAC7100_IMRL_OFFSET (0x000C)
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#define MAC7100_INTFRCH_OFFSET (0x0010)
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#define MAC7100_INTFRCL_OFFSET (0x0014)
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#define MAC7100_ICONFIG_OFFSET (0x001B)
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#define MAC7100_SIMR_OFFSET (0x001C)
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#define MAC7100_CIMR_OFFSET (0x001D)
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#define MAC7100_CLMASK_OFFSET (0x001E) // CLMASK - Current Level Mask Register
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#define MAC7100_SLMASK_OFFSET (0x001F) // SLMASK - Saved Level Mask Register
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#define MAC7100_ICR_OFFSET (0x0040)
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#define MAC7100_IRQIACK_OFFSET (0x00EC)
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#define MAC7100_FIQIACK_OFFSET (0x00F0)
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#define MAC7100_INTC_IPRH(intc_base) (intc_base + MAC7100_IPRH_OFFSET)
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#define MAC7100_INTC_IPRL(intc_base) (intc_base + MAC7100_IPRL_OFFSET)
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#define MAC7100_INTC_IMRH(intc_base) (intc_base + MAC7100_IMRH_OFFSET)
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#define MAC7100_INTC_IMRL(intc_base) (intc_base + MAC7100_IMRL_OFFSET)
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#define MAC7100_INTC_INTFRC(intc_base) (intc_base + MAC7100_INTFRCH_OFFSET)
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#define MAC7100_INTC_INTFRCH(intc_base) (intc_base + MAC7100_INTFRCH_OFFSET)
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#define MAC7100_INTC_INTFRCL(intc_base) (intc_base + MAC7100_INTFRCL_OFFSET)
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#define MAC7100_INTC_ICONFIG(intc_base) (intc_base + MAC7100_ICONFIG_OFFSET)
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#define MAC7100_INTC_IRQIACK(intc_base) (intc_base + MAC7100_IRQIACK_OFFSET)
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#define MAC7100_INTC_FIQIACK(intc_base) (intc_base + MAC7100_FIQIACK_OFFSET)
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#define MAC7100_INTC_ICR(intc_base,src) (intc_base + MAC7100_ICR_OFFSET + src)
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#define MAC7100_INTC_SIMR(intc_base) (intc_base + MAC7100_SIMR_OFFSET)
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#define MAC7100_INTC_CIMR(intc_base) (intc_base + MAC7100_CIMR_OFFSET)
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#define MAC7100_INTC_CLMASK(intc_base) (intc_base + MAC7100_CLMASK_OFFSET)
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#define MAC7100_INTC_SLMASK(intc_base) (intc_base + MAC7100_SLMASK_OFFSET)
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#define MAC7100_INTC_INT_LEVEL(lev) (lev)
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// hardware interrupt source vector numbers
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#define MAC7100_EDMA0_IV (0)
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#define MAC7100_EDMA1_IV (1)
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#define MAC7100_EDMA2_IV (2)
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#define MAC7100_EDMA3_IV (3)
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#define MAC7100_EDMA4_IV (4)
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#define MAC7100_EDMA5_IV (5)
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#define MAC7100_EDMA6_IV (6)
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#define MAC7100_EDMA7_IV (7)
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#define MAC7100_EDMA8_IV (8)
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#define MAC7100_EDMA9_IV (9)
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#define MAC7100_EDMA10_IV (10)
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#define MAC7100_EDMA11_IV (11)
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#define MAC7100_EDMA12_IV (12)
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#define MAC7100_EDMA13_IV (13)
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#define MAC7100_EDMA14_IV (14)
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#define MAC7100_EDMA15_IV (15)
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#define MAC7100_EDMA_Error_IV (16)
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#define MAC7100_MCM_SWT_IV (17)
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#define MAC7100_CRG_IV (18)
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#define MAC7100_PIT1_IV (19)
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#define MAC7100_PIT2_IV (20)
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#define MAC7100_PIT3_IV (21)
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#define MAC7100_PIT4_RTI_IV (22)
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#define MAC7100_VREG_IV (23)
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#define MAC7100_CAN_A_MB_IV (24)
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#define MAC7100_CAN_A_MB14_IV (25)
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#define MAC7100_CAN_A_Error_IV (26)
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#define MAC7100_CAN_B_MB_IV (27)
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#define MAC7100_CAN_B_MB14_IV (28)
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#define MAC7100_CAN_B_Error_IV (29)
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#define MAC7100_CAN_C_MB_IV (30)
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#define MAC7100_CAN_C_MB14_IV (31)
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#define MAC7100_CAN_C_Error_IV (32)
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#define MAC7100_CAN_D_MB_IV (33)
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#define MAC7100_CAN_D_MB14_IV (34)
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#define MAC7100_CAN_D_Error_IV (35)
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#define MAC7100_I2C_IV (36)
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#define MAC7100_DSPI_A_IV (37)
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#define MAC7100_DSPI_B_IV (38)
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#define MAC7100_ESCI_A_IV (39)
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#define MAC7100_ESCI_B_IV (40)
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#define MAC7100_ESCI_C_IV (41)
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#define MAC7100_ESCI_D_IV (42)
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#define MAC7100_EMIOS0_IV (43)
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#define MAC7100_EMIOS1_IV (44)
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#define MAC7100_EMIOS2_IV (45)
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#define MAC7100_EMIOS3_IV (46)
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#define MAC7100_EMIOS4_IV (47)
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#define MAC7100_EMIOS5_IV (48)
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#define MAC7100_EMIOS6_IV (49)
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#define MAC7100_EMIOS7_IV (50)
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#define MAC7100_EMIOS8_IV (51)
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#define MAC7100_EMIOS9_IV (52)
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#define MAC7100_EMIOS10_IV (53)
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#define MAC7100_EMIOS11_IV (54)
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#define MAC7100_EMIOS12_IV (55)
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#define MAC7100_EMIOS13_IV (56)
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#define MAC7100_EMIOS14_IV (57)
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#define MAC7100_EMIOS15_IV (58)
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#define MAC7100_ATD_IV (59)
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#define MAC7100_CFM_IV (60)
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#define MAC7100_PIM_IV (61)
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#define MAC7100_IRQ_IV (62)
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#define MAC7100_XIRQ_IV (63)
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#define MAC7100_IRQ_SPURIOUS (-1)
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// *******************************************************************
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//
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// eSCI Module
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// Note: eSCI definitions are in cyg/devs/ser_esci.h
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// *******************************************************************
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#define CYGADDR_IO_SERIAL_FREESCALE_ESCI_A_BASE 0xFC0C4000
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#define CYGNUM_IO_SERIAL_FREESCALE_ESCI_A_INT_VECTOR MAC7100_ESCI_A_IV
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#define CYGADDR_IO_SERIAL_FREESCALE_ESCI_B_BASE 0xFC0C8000
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#define CYGNUM_IO_SERIAL_FREESCALE_ESCI_B_INT_VECTOR MAC7100_ESCI_B_IV
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#define CYGADDR_IO_SERIAL_FREESCALE_ESCI_C_BASE 0xFC0CC000
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#define CYGNUM_IO_SERIAL_FREESCALE_ESCI_C_INT_VECTOR MAC7100_ESCI_C_IV
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#define CYGADDR_IO_SERIAL_FREESCALE_ESCI_D_BASE 0xFC0D0000
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#define CYGNUM_IO_SERIAL_FREESCALE_ESCI_D_INT_VECTOR MAC7100_ESCI_D_IV
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#define CYGNUM_DEV_SER_FREESCALE_ESCI_SYSTEM_CLOCK \
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(CYGNUM_HAL_ARM_MAC7100_CLOCK_SPEED/2)
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#define FREESCALE_ESCI_BAUD(baud_rate) \
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((CYGNUM_DEV_SER_FREESCALE_ESCI_SYSTEM_CLOCK)/(baud_rate*16))
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// *********************************************************************
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//
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// PIT Module
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//
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// *********************************************************************
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// Periodic Interrupt Timer Module Definitions
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#define MAC7100_PIT_BASE (0xFC08C000)
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#define MAC7100_TLVAL0_OFFSET (0x0000)
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#define MAC7100_TVAL0_OFFSET (0x0080)
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#define MAC7100_PIT_TLVAL(pit_base,chan) \
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(pit_base + MAC7100_TLVAL0_OFFSET + (4 * chan))
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#define MAC7100_PIT_TVAL(pit_base,chan) \
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(pit_base + MAC7100_TVAL0_OFFSET + (4 * chan))
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#define MAC7100_PITFLG_OFFSET (0x0100)
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#define MAC7100_PITINTEN_OFFSET (0x0104)
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#define MAC7100_PITINTSEL_OFFSET (0x0108)
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#define MAC7100_PITEN_OFFSET (0x010C)
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#define MAC7100_PITCTRL_OFFSET (0x0110)
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#define MAC7100_PIT_FLAG_RTIF (0x00000001)
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#define MAC7100_PIT_FLAG_TIF(chan) (0x00000001 << chan)
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#define MAC7100_PIT_INTSEL_ISEL(chan) (0x00000001 << chan)
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#define MAC7100_PIT_INTEN_RTIE (0x00000001)
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#define MAC7100_PIT_INTEN_TIE(chan) (0x00000001 << chan)
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#define MAC7100_PIT_EN_RTIEN (0x00000001)
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#define MAC7100_PIT_EN_PEN(chan) (0x00000001 << chan)
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#define MAC7100_PIT_FLG(pit_base) (pit_base + MAC7100_PITFLG_OFFSET)
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#define MAC7100_PIT_INTEN(pit_base) (pit_base + MAC7100_PITINTEN_OFFSET)
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#define MAC7100_PIT_INTSEL(pit_base) (pit_base + MAC7100_PITINTSEL_OFFSET)
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#define MAC7100_PIT_EN(pit_base) (pit_base + MAC7100_PITEN_OFFSET)
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#define MAC7100_PIT_CTRL(pit_base) (pit_base + MAC7100_PITCTRL_OFFSET)
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#define MAC7100_PIT_MDIS (0x01000000)
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// *********************************************************************
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//
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// PIM Module
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//
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// *********************************************************************/
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#define MAC7100_PIM_BASE (0xFC0E8000)
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#define MAC7100_PORT_A_OFFSET (0x000)
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#define MAC7100_PORT_B_OFFSET (0x040)
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#define MAC7100_PORT_C_OFFSET (0x080)
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#define MAC7100_PORT_D_OFFSET (0x0C0)
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#define MAC7100_PORT_E_OFFSET (0x100)
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#define MAC7100_PORT_F_OFFSET (0x140)
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#define MAC7100_PORT_G_OFFSET (0x180)
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#define MAC7100_PORT_H_OFFSET (0x1C0)
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#define MAC7100_PORT_I_OFFSET (0x200)
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// PORT Pin Configuration Registers
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#define MAC7100_PIM_CONFIG(port,pin) (MAC7100_PIM_BASE+port+((pin)*2))
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// Port Wide Interrupt Flag Register
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#define MAC7100_PIM_PORTIFR(port) (MAC7100_PIM_BASE+port+0x20)
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// Port Wide Data Read/Write Register
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#define MAC7100_PIM_PORTDATA(port) (MAC7100_PIM_BASE+port+0x24)
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// Port Wide Input Register
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#define MAC7100_PIM_PORTIR(port) (MAC7100_PIM_BASE+port+0x26)
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// Port Pin Data Registers
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#define MAC7100_PIM_DATA(port,pin) (MAC7100_PIM_BASE+port+0x28+pin)
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// Global Interrupt Status Register
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#define MAC7100_PIM_GLBLINT (MAC7100_PIM_BASE+0x03C0)
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// PIM Configuration Register
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#define MAC7100_PIM_PIMCONFIG (MAC7100_PIM_BASE+0x03C2)
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// TDI Pin Configuration Register
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#define MAC7100_PIM_CONFIG_TDI (MAC7100_PIM_BASE+0x03C4)
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// TDO Pin Configuration Register
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#define MAC7100_PIM_CONFIG_TDO (MAC7100_PIM_BASE+0x03C6)
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// TMS Pin Configuration Register
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#define MAC7100_PIM_CONFIG_TMS (MAC7100_PIM_BASE+0x03C8)
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// TCK Pin Configuration Register
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#define MAC7100_PIM_CONFIG_TCK (MAC7100_PIM_BASE+0x03CA)
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// TA Pin Configuration Register
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#define MAC7100_PIM_CONFIG_TA (MAC7100_PIM_BASE+0x03CC)
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// Bit definitions and macros for PIM_PA_CONFIGn
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// Pin Interrupt Flag Register
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#define MAC7100_PIM_PIFR (0x0001)
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// Pin Interrupt Enable Register
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#define MAC7100_PIM_PIER (0x0002)
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// Pull-up/down Enable Register
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#define MAC7100_PIM_PULL(x) (((x)&0x0003)<<2)
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// Reduced Drive Strength Register
|
287 |
|
|
#define MAC7100_PIM_RDR (0x0010)
|
288 |
|
|
// Open Drain Enable Register
|
289 |
|
|
#define MAC7100_PIM_ODER (0x0020)
|
290 |
|
|
// Data Direction Register
|
291 |
|
|
#define MAC7100_PIM_DDR (0x0040)
|
292 |
|
|
#define MAC7100_PIM_MODE (0x0080)
|
293 |
|
|
#define MAC7100_PIM_MODE_PERIPHERAL MAC7100_PIM_MODE
|
294 |
|
|
|
295 |
|
|
// Bit definitions and macros for PIM_GLBLINT
|
296 |
|
|
// Interrupt Pending
|
297 |
|
|
#define MAC7100_PIM_INT_PENDING(x) (((x)&0x01FF)<<0)
|
298 |
|
|
|
299 |
|
|
// Bit definitions and macros for PIM_PIMCONFIG
|
300 |
|
|
// Clock Enable for the EIM module
|
301 |
|
|
#define MAC7100_PIM_PORTHSEL (0x0001)
|
302 |
|
|
// Port H Select
|
303 |
|
|
#define MAC7100_PIM_EIMCLKEN (0x0002)
|
304 |
|
|
|
305 |
|
|
#define MAC7100_PIM_PORT32IR(port32ir) (MAC7100_PIM_BASE+0x03E0+port32ir)
|
306 |
|
|
|
307 |
|
|
#define MAC7100_PIM_PORT32IR_AB (0x00)
|
308 |
|
|
#define MAC7100_PIM_PORT32IR_CD (0x04)
|
309 |
|
|
#define MAC7100_PIM_PORT32IR_EF (0x08)
|
310 |
|
|
#define MAC7100_PIM_PORT32IR_GH (0x0C)
|
311 |
|
|
#define MAC7100_PIM_PORT32IR_BC (0x10)
|
312 |
|
|
#define MAC7100_PIM_PORT32IR_DE (0x14)
|
313 |
|
|
#define MAC7100_PIM_PORT32IR_FG (0x18)
|
314 |
|
|
#define MAC7100_PIM_PORT32IR_HI (0x1C)
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
// ********************************************************************
|
318 |
|
|
//
|
319 |
|
|
// CRG Module
|
320 |
|
|
//
|
321 |
|
|
// ********************************************************************
|
322 |
|
|
|
323 |
|
|
// Register read/write macros
|
324 |
|
|
#define MAC7100_CRG_BASE 0xFC088000 // SYNR - Synthesizer Register
|
325 |
|
|
#define MAC7100_CRG_SYNR 0xFC088000 // SYNR - Synthesizer Register
|
326 |
|
|
#define MAC7100_CRG_REFDV 0xFC088001 // REFDV - Reference Divider Register
|
327 |
|
|
#define MAC7100_CRG_CTFLG 0xFC088002 // CTFLG - Test Flags Register (reserved)
|
328 |
|
|
#define MAC7100_CRG_CRGFLG 0xFC088003 // CRGFLG - Flags Register
|
329 |
|
|
#define MAC7100_CRG_CRGINT 0xFC088004 // CRGINT - Interrupt Enable Register
|
330 |
|
|
#define MAC7100_CRG_CLKSEL 0xFC088005 // CLKSEL - Clock Select Register
|
331 |
|
|
#define MAC7100_CRG_PLLCTL 0xFC088006 // PLLCTL - PLL Control Register
|
332 |
|
|
#define MAC7100_CRG_SDMCTL 0xFC088007 // SDMCTL - STOP/DOZE Control Register
|
333 |
|
|
#define MAC7100_CRG_BDMCTL 0xFC088008 // BDMCTL - BDM Control Register
|
334 |
|
|
#define MAC7100_CRG_FORBYP 0xFC088009 // FORBYP - Force and Bypass Test
|
335 |
|
|
#define MAC7100_CRG_CTCTL 0xFC08800A // CTCTL - Test Control Register (resvd)
|
336 |
|
|
|
337 |
|
|
// Bit definitions and macros for CRG_SYNR
|
338 |
|
|
#define MAC7100_CRG_SYN(x) (((x)&0x3F)<<0) // Synthesizer Count value
|
339 |
|
|
|
340 |
|
|
// Bit definitions and macros for CRG_REFDV
|
341 |
|
|
#define MAC7100_CRG_REFD(x) (((x)&0x0F)<<0) //Reference divider
|
342 |
|
|
|
343 |
|
|
// Bit definitions and macros for CRG_CRGFLG
|
344 |
|
|
#define MAC7100_CRG_SCM (0x01) //Self Clock Mode Status
|
345 |
|
|
#define MAC7100_CRG_SCMIF (0x02) //Self Clock Mode Interrupt Flag
|
346 |
|
|
#define MAC7100_CRG_TRACK (0x04) //Track Status
|
347 |
|
|
#define MAC7100_CRG_LOCK (0x08) //Lock Status
|
348 |
|
|
#define MAC7100_CRG_LOCKIF (0x10) //PLL Lock Interrupt Flag
|
349 |
|
|
#define MAC7100_CRG_LVRF (0x20) //Low Voltage Reset Flag
|
350 |
|
|
#define MAC7100_CRG_PORF (0x40) //Power on Reset Flag
|
351 |
|
|
#define MAC7100_CRG_STPEF (0x80) //Stop Entry Flag
|
352 |
|
|
|
353 |
|
|
// Bit definitions and macros for CRG_CRGINT
|
354 |
|
|
#define MAC7100_CRG_SCMIE (0x02) //Self Clock Mode Interrupt Enable
|
355 |
|
|
#define MAC7100_CRG_LOCKIE (0x10) //Lock Interrupt Enable
|
356 |
|
|
|
357 |
|
|
// Bit definitions and macros for CRG_CLKSEL
|
358 |
|
|
#define MAC7100_CRG_SWTDOZE (0x01) //SWT stops in Doze Mode
|
359 |
|
|
#define MAC7100_CRG_RTIDOZE (0x02) /* RTI stops in Doze Mode */
|
360 |
|
|
#define MAC7100_CRG_PLLDOZE (0x08) /* PLL stops in Doze Mode */
|
361 |
|
|
#define MAC7100_CRG_DOZE_ROA (0x10) /* Reduced Osc Amp in Doze Mode */
|
362 |
|
|
#define MAC7100_CRG_PSTP (0x40) /* Pseudo Stop */
|
363 |
|
|
#define MAC7100_CRG_PLLSEL (0x80) /* PLL Select */
|
364 |
|
|
|
365 |
|
|
// Bit definitions and macros for CRG_PLLCTL
|
366 |
|
|
#define MAC7100_CRG_SCME (0x01) //Self Clock Mode Enable
|
367 |
|
|
#define MAC7100_CRG_PWE (0x02) //SWT Enable during Pseudo Stop
|
368 |
|
|
#define MAC7100_CRG_PRE (0x04) //RTI Enable during Pseudo Stop
|
369 |
|
|
#define MAC7100_CRG_FSTWKP (0x08) //Fast Wake-up from Full Stop Bit
|
370 |
|
|
#define MAC7100_CRG_ACQ (0x10) //Acquisition
|
371 |
|
|
#define MAC7100_CRG_AUTO (0x20) //Automatic Bandwidth Control
|
372 |
|
|
#define MAC7100_CRG_PLLON (0x40) //Phase Lock Loop On
|
373 |
|
|
#define MAC7100_CRG_CME (0x80) //Clock Monitor Enable
|
374 |
|
|
|
375 |
|
|
// Bit definitions and macros for CRG_SDMCTL
|
376 |
|
|
#define MAC7100_CRG_STOP (0x01) //STOP mode
|
377 |
|
|
#define MAC7100_CRG_DOZE (0x02) //DOZE mode
|
378 |
|
|
|
379 |
|
|
// Bit definitions and macros for CRG_BDMCTL
|
380 |
|
|
#define MAC7100_CRG_RSBCK (0x40) //SWT & RTI stop in Active BDM mode
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
// *********************************************************************
|
384 |
|
|
//
|
385 |
|
|
// MCM Module
|
386 |
|
|
//
|
387 |
|
|
// *********************************************************************
|
388 |
|
|
|
389 |
|
|
// Register read/write macros
|
390 |
|
|
#define MAC7100_MCM_PCT 0xFC040000 //
|
391 |
|
|
#define MAC7100_MCM_REV 0xFC040002 //
|
392 |
|
|
#define MAC7100_MCM_AMC 0xFC040004 //
|
393 |
|
|
#define MAC7100_MCM_ASC 0xFC040006 //
|
394 |
|
|
#define MAC7100_MCM_IMC 0xFC040008 //
|
395 |
|
|
// MRSR - Miscellaneous Reset Status Register
|
396 |
|
|
#define MAC7100_MCM_MRSR 0xFC04000F
|
397 |
|
|
// MWCR - Miscellaneous Wakeup Control Register
|
398 |
|
|
#define MAC7100_MCM_MWCR 0xFC040013
|
399 |
|
|
// MSWTCR - Miscellaneous Software Watchdog Timer Control Register
|
400 |
|
|
#define MAC7100_MCM_MSWTCR 0xFC040016
|
401 |
|
|
// MSWTSR - Miscellaneous Software Watchdog Timer Service Register
|
402 |
|
|
#define MAC7100_MCM_MSWTSR 0xFC04001B
|
403 |
|
|
// MSWTIR - Miscellaneous Software Watchdog Timer Interrupt Register
|
404 |
|
|
#define MAC7100_MCM_MSWTIR 0xFC04001F
|
405 |
|
|
// AAMR - AXBS Address Map Register
|
406 |
|
|
#define MAC7100_MCM_AAMR 0xFC040020
|
407 |
|
|
// CFADR - Core Fault Address Register
|
408 |
|
|
#define MAC7100_MCM_CFADR 0xFC040070
|
409 |
|
|
// CFLOC - Core Fault Location Register
|
410 |
|
|
#define MAC7100_MCM_CFLOC 0xFC040076
|
411 |
|
|
// CFATR - Core Fault Attributes Register
|
412 |
|
|
#define MAC7100_MCM_CFATR 0xFC040077
|
413 |
|
|
// CFDTR - Core Fault Data Register
|
414 |
|
|
#define MAC7100_MCM_CFDTR 0xFC04007C
|
415 |
|
|
|
416 |
|
|
// Bit definitions and macros for MCM_AMC
|
417 |
|
|
|
418 |
|
|
// AXBS Master Configuration
|
419 |
|
|
#define MAC7100_MCM_AXMC(x) (((x)&0x00FF)<<0)
|
420 |
|
|
|
421 |
|
|
// Bit definitions and macros for MCM_ASC
|
422 |
|
|
// AXBS Slave Configuration
|
423 |
|
|
#define MAC7100_MCM_AXSC(x) (((x)&0x00FF)<<0)
|
424 |
|
|
#define MAC7100_MCM_DP64 (0x8000) // 64-bit Datapath
|
425 |
|
|
|
426 |
|
|
// Bit definitions and macros for MCM_MRSR
|
427 |
|
|
#define MAC7100_MCM_SWTR (0x20) // Watchdog Timer Reset
|
428 |
|
|
#define MAC7100_MCM_DIR (0x40) // Device Input Reset
|
429 |
|
|
#define MAC7100_MCM_POR (0x80) // Power-On Reset
|
430 |
|
|
|
431 |
|
|
// Bit definitions and macros for MCM_MWCR
|
432 |
|
|
#define MAC7100_MCM_PRILVL(x) (((x)&0x0F)<<0) // Interrupt Priority Level
|
433 |
|
|
#define MAC7100_MCM_ENBWCR (0x80) // Enable WCR
|
434 |
|
|
|
435 |
|
|
// Bit definitions and macros for MCM_MSWTCR
|
436 |
|
|
#define MAC7100_MCM_SWT(x) (((x)&0x001F)<<0) // Watchdog Time-Out Period
|
437 |
|
|
#define MAC7100_MCM_SWRI(x) (((x)&0x0003)<<5) // Watchdog Reset/Interrupt
|
438 |
|
|
#define MAC7100_MCM_SWE (0x0080) // Watchdog Enable
|
439 |
|
|
#define MAC7100_MCM_SWRWH (0x0100) // Watchdog Run While Halted
|
440 |
|
|
#define MAC7100_MCM_SWCIN16 (0x0200) // Force SWT CarryIn16
|
441 |
|
|
#define MAC7100_MCM_RO (0x8000) // Read-Only
|
442 |
|
|
|
443 |
|
|
// Bit definitions and macros for MCM_MSWTIR
|
444 |
|
|
#define MAC7100_MCM_SWTIC (0x01) // Watchdog Interrupt Flag
|
445 |
|
|
|
446 |
|
|
// Bit definitions and macros for MCM_AAMR
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
// Address 0 Slave Number
|
450 |
|
|
#define MAC7100_MCM_ASLAVE(adr_reg,sl_n) (((sl_n)&0x00000007)<<(adr_reg*4)
|
451 |
|
|
// Enable Address Region 0
|
452 |
|
|
#define MAC7100_MCM_EA(adr_reg) (0x00000008<<(adr_reg*4))
|
453 |
|
|
|
454 |
|
|
// Bit definitions and macros for MCM_CFLOC
|
455 |
|
|
#define MAC7100_MCM_LOCALERR (0x80) // Bus Error Indicator
|
456 |
|
|
|
457 |
|
|
// Bit definitions and macros for MCM_CFATR
|
458 |
|
|
// Protection fault type
|
459 |
|
|
#define MAC7100_MCM_PROTECTION(x) (((x)&0x0F)<<0)
|
460 |
|
|
// 8-16-32-64-bit core access
|
461 |
|
|
#define MAC7100_MCM_SIZE(x) (((x)&0x07)<<4)
|
462 |
|
|
// Core read/write access
|
463 |
|
|
#define MAC7100_MCM_WRITE (0x80)
|
464 |
|
|
|
465 |
|
|
//=============================================================================
|
466 |
|
|
// FIQ interrupt vector which is shared by all HAL variants.
|
467 |
|
|
|
468 |
|
|
#define CYGNUM_HAL_INTERRUPT_FIQ 0
|
469 |
|
|
#endif // CYGONCE_HAL_VAR_IO_H
|
470 |
|
|
//-----------------------------------------------------------------------------
|
471 |
|
|
// end of var_io.h
|