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skrzyp |
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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#define CYGONCE_HAL_PLATFORM_SETUP_H
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/*=============================================================================
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//
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// hal_platform_setup.h
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//
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// Platform specific support for HAL (assembly code)
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors: gthomas, richard.panton@3glab.com
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// Date: 2001-02-24
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// Purpose: Intel SA1110/iPAQ platform specific support routines
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// Description:
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// Usage: #include <cyg/hal/hal_platform_setup.h>
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// Only used by "vectors.S"
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/system.h> // System-wide configuration info
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#include CYGBLD_HAL_VARIANT_H // Variant (SA11x0) specific configuration
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#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
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#include <cyg/hal/hal_sa11x0.h> // Variant specific hardware definitions
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#include <cyg/hal/hal_mmu.h> // MMU definitions
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#include <cyg/hal/ipaq.h> // Platform specific hardware definitions
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#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_Compaq) || defined(CYG_HAL_STARTUP_WinCE)
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#define PLATFORM_SETUP1 _platform_setup1
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#define CYGHWR_HAL_ARM_HAS_MMU
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#define CYGSEM_HAL_ROM_RESET_USES_JUMP
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#if defined(CYG_HAL_STARTUP_WinCE)
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#define UNMAPPED(x) (x)+SA11X0_RAM_BANK0_BASE
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#endif
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#if defined(CYG_HAL_STARTUP_ROM)
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#if (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 59000)
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#define SA11X0_PLL_CLOCK 0x0
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 73700)
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#define SA11X0_PLL_CLOCK 0x1
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 88500)
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#define SA11X0_PLL_CLOCK 0x2
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 103200)
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#define SA11X0_PLL_CLOCK 0x3
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 118000)
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#define SA11X0_PLL_CLOCK 0x4
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 132700)
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#define SA11X0_PLL_CLOCK 0x5
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 147500)
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#define SA11X0_PLL_CLOCK 0x6
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 162200)
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#define SA11X0_PLL_CLOCK 0x7
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 176900)
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#define SA11X0_PLL_CLOCK 0x8
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 191700)
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#define SA11X0_PLL_CLOCK 0x9
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 206400)
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#define SA11X0_PLL_CLOCK 0xA
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#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 221200)
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#define SA11X0_PLL_CLOCK 0xB
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#else
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#error Invalid processor clock speed
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#endif
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#endif
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//#define DEBUG_INIT
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// Special image header - required when run via Parrot loader
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#ifdef CYGSEM_HAL_PARROT_BOOT
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#define PLATFORM_PREAMBLE _platform_preamble
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.macro _platform_preamble
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b 100f
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.org 0x40
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.long 0x43454345 // CECE
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.long 0x8C0B3000 // Unknown magic
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.org 0x1000
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100:
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.endm
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#endif
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.macro InitUART3
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#define EGPIOBase 0x49000000
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#define EGPIO_BITSY_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */
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#define SA1100_UTCR0 0x00
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#define SA1100_UTCR1 0x04
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#define SA1100_UTCR2 0x08
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#define SA1100_UTCR3 0x0C
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#define SA1100_UTDR 0x14
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#define SA1100_UTSR0 0x1c
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#define SA1100_UTSR1 0x20
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#define SA1100_UTCR0_PE (1 << 0) /* parity enable */
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#define SA1100_UTCR0_OES (1 << 1) /* 1 for even parity */
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#define SA1100_UTCR0_2STOP (1 << 2) /* 1 for 2 stop bits */
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#define SA1100_UTCR0_8BIT (1 << 3) /* 1 for 8 bit data */
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#define SA1100_UTCR0_SCE (1 << 4) /* sample clock enable */
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#define SA1100_UTCR0_RCE (1 << 5) /* receive clock edge select */
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#define SA1100_UTCR0_TCE (1 << 6) /* transmit clock edge select */
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#define SA1100_UTCR1_BRDHIMASK 0xF
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#define SA1100_UTCR2_BRDLoMASK 0xFF
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#define SA1100_UTCR3_RXE (1 << 0) /* receiver enable */
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#define SA1100_UTCR3_TXE (1 << 1) /* transmit enable */
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#define SA1100_UTCR3_BRK (1 << 2) /* send a BRK */
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#define SA1100_UTCR3_RIE (1 << 3) /* receive FIFO interrupt enable */
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#define SA1100_UTCR3_TIE (1 << 4) /* transmit FIFO interrupt enable */
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#define SA1100_UTCR3_LBM (1 << 5) /* loopback mode */
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/* [1] 11.11.6 */
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#define SA1100_UTDR_PRE (1 << 8) /* parity error */
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#define SA1100_UTDR_FRE (1 << 9) /* framing error */
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#define SA1100_UTDR_ROR (1 << 10) /* receiver overrun */
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/* [1] 11.11.7 */
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#define SA1100_UTSR0_TFS (1 << 0) /* transmit FIFO service request */
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/* [1] 11.11.8 */
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#define SA1100_UTSR1_TBY (1 << 0) /* transmit FIFO busy */
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#define SA1100_UTSR1_RNE (1 << 1) /* receive FIFO not empty */
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#define SA1100_UTSR1_TNF (1 << 2) /* transmit FIFO not full */
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#define SA1100_UTSR1_PRE (1 << 3) /* parity error */
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#define SA1100_UTSR1_FRE (1 << 4) /* framing error */
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#define SA1100_UTSR1_ROR (1 << 5) /* receiver overrun */
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#define SA1100_UTSR1_ERROR_MASK 0x38
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#define SA1100_UART3BASE 0x80050000
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/*
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;; ********************************************************************
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;; InitUART3 - Initialize Serial Communications
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;; ********************************************************************
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;; Following reset, the UART is disabled. So, we do the following:
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*/
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ldr r1, =SA1100_UART3BASE
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/* disable the UART */
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mov r2, #0x00
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str r2, [r1, #SA1100_UTCR3] /* UART1 Control Reg. 3 */
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/* Now clear all 'sticky' bits in serial I registers, cf. [1] 11.11 */
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mov r2, #0xFF
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str r2, [r1, #SA1100_UTSR0] /* UART1 Status Reg. 0 */
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/* Set the serial port to sensible defaults: no break, no interrupts, */
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/* no parity, 8 databits, 1 stopbit. */
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mov r2, #SA1100_UTCR0_8BIT
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str r2, [r1, #SA1100_UTCR0] /* UART1 Control Reg. 0 */
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/* Set BRD to 1, for a baudrate of 115K2 ([1] 11.11.4.1) */
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/* Set BRD to 3, for a baudrate of 57k6 ([1] 11.11.4.1) */
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/* Set BRD to 5, for a baudrate of 38k4 ([1] 11.11.4.1) */
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/* Set BRD to 23, for a baudrate of 9k6 ([1] 11.11.4.1) */
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mov r2, #0x00
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str r2, [r1, #SA1100_UTCR1]
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mov r2, #SA11X0_UART_BAUD_RATE_DIVISOR(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD)
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str r2, [r1, #SA1100_UTCR2]
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/* enable the UART TX and RX */
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//InitUart3Enable:
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mov r2, #(SA1100_UTCR3_RXE|SA1100_UTCR3_TXE)
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str r2, [r1, #SA1100_UTCR3]
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ldr r3, =EGPIOBase
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mov r2, #EGPIO_BITSY_RS232_ON
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str r2, [r3, #0]
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ldr r2, [r3, #0]
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// Give a little pause to let the thing settle
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ldr r1,=1000000
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10: sub r1,r1,#1
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cmp r1,#0
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bne 10b
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.endm
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.macro PutC c
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ldr r8,=\c
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PutCh r8
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.endm
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.macro PutCh c
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ldr r9,=SA1100_UART3BASE
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str \c,[r9,#SA1100_UTDR]
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77: ldr \c,[r9,#SA1100_UTSR1]
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tst \c,#SA1100_UTSR1_TNF // Tx FIFO not full
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beq 77b
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.endm
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.macro PutNibble n
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and \n,\n,#0x0F
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cmp \n,#0x0A
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blt 78f
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add \n,\n,#'A'-'0'-0x0A
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78: add \n,\n,#'0'
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PutCh \n
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.endm
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.macro PutHex1 h
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mov r0,\h,LSR #4
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PutNibble r0
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PutNibble \h
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| 239 |
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.endm
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| 240 |
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| 241 |
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.macro PutHex2 h
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mov r1,\h,LSR #8
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PutHex1 r1
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| 244 |
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PutHex1 \h
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| 245 |
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.endm
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| 246 |
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| 247 |
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.macro PutHex4 h
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| 248 |
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PutC '0'
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| 249 |
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PutC 'x'
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| 250 |
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mov r2,\h,LSR #16
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| 251 |
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PutHex2 r2
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| 252 |
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PutHex2 \h
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| 253 |
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.endm
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| 254 |
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| 255 |
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// This macro represents the initial startup code for the platform
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| 256 |
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.macro _platform_setup1
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| 257 |
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| 258 |
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#ifdef DEBUG_INIT
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| 259 |
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b 54f
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| 260 |
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// Dump hex memory
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| 261 |
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// R5 - base address
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| 262 |
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// R4 - length
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| 263 |
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// R0..R6 destroyed
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| 264 |
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dump:
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| 265 |
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PutC '\r'
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| 266 |
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PutC '\n'
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| 267 |
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50: mov r6,r5
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| 268 |
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PutHex4 r6
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| 269 |
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PutC ' '
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| 270 |
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ldr r3,=8
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| 271 |
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52: PutC ' '
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| 272 |
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ldr r6,[r5],#4
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| 273 |
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PutHex4 r6
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| 274 |
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sub r3,r3,#1
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| 275 |
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cmp r3,#0
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| 276 |
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bne 52b
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| 277 |
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PutC '\n'
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| 278 |
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PutC '\r'
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| 279 |
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sub r4,r4,#1
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| 280 |
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cmp r4,#0
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| 281 |
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bne 50b
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| 282 |
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mov pc,lr
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| 283 |
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| 284 |
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hexR6:
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| 285 |
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PutHex4 r6
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| 286 |
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PutC ' '
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| 287 |
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mov pc,lr
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| 288 |
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54:
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| 289 |
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#endif // DEBUG_INIT
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| 290 |
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| 291 |
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// Disable all interrupts
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| 292 |
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ldr r1,=SA11X0_ICMR
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| 293 |
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mov r0,#0
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| 294 |
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str r0,[r1]
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| 295 |
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| 296 |
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// Make sure MMU is OFF
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| 297 |
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mov r0,#0xE0000000 // Force cache writeback by reloading
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| 298 |
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add r2,r0,#0x4000 // cache from the zeros bank
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| 299 |
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123: ldr r1,[r0],#32
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| 300 |
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cmp r0, r2
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| 301 |
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bne 123b
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| 302 |
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mov r0,#0
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| 303 |
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mov r1,#0x0070 // MMU Control System bit
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| 304 |
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mcr p15,0,r0,c7,c7,0 // Flush data and instruction cache
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| 305 |
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mcr p15,0,r0,c8,c7,0 // Flush ID TLBs
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| 306 |
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mcr p15,0,r0,c9,c0,0 // Flush Read-Buffer
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| 307 |
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mcr p15,0,r0,c7,c10,4 // Drain write buffer
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| 308 |
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mcr p15,0,r0,c13,c0,0 // Disable virtual ID mapping
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| 309 |
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mcr p15,0,r1,c1,c0,0 // Write MMU control register
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| 310 |
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nop; nop; nop; nop
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| 311 |
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|
| 312 |
|
|
InitUART3
|
| 313 |
|
|
#ifdef DEBUG_INIT
|
| 314 |
|
|
mov r7,#5
|
| 315 |
|
|
05: PutC '\n'
|
| 316 |
|
|
PutC '\r'
|
| 317 |
|
|
sub r7,r7,#1
|
| 318 |
|
|
cmp r7,#0
|
| 319 |
|
|
bne 05b
|
| 320 |
|
|
|
| 321 |
|
|
mrs r6,cpsr
|
| 322 |
|
|
bl hexR6
|
| 323 |
|
|
#endif // DEBUG_INIT
|
| 324 |
|
|
|
| 325 |
|
|
#if 0 // This made no difference
|
| 326 |
|
|
ldr r1,=10f
|
| 327 |
|
|
ldr r2,=SA11X0_RAM_BANK0_BASE
|
| 328 |
|
|
add r1,r1,r2
|
| 329 |
|
|
mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
|
| 330 |
|
|
msr cpsr,r0
|
| 331 |
|
|
msr spsr,r0
|
| 332 |
|
|
movs pc,r1
|
| 333 |
|
|
10:
|
| 334 |
|
|
#else
|
| 335 |
|
|
|
| 336 |
|
|
mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
|
| 337 |
|
|
msr cpsr,r0
|
| 338 |
|
|
#endif
|
| 339 |
|
|
#ifdef DEBUG_INIT
|
| 340 |
|
|
mrs r6,cpsr
|
| 341 |
|
|
bl hexR6
|
| 342 |
|
|
|
| 343 |
|
|
ldr r5,=0x00000000
|
| 344 |
|
|
ldr r4,=0x100/32
|
| 345 |
|
|
bl dump
|
| 346 |
|
|
#endif // DEBUG_INIT
|
| 347 |
|
|
|
| 348 |
|
|
// Initialise extended GPIO
|
| 349 |
|
|
ldr r0,=SA1110_EGPIO
|
| 350 |
|
|
ldr r4,=SA1110_EIO_MIN
|
| 351 |
|
|
|
| 352 |
|
|
// Initialize pin directions
|
| 353 |
|
|
ldr r1,=SA11X0_GPIO_PIN_DIRECTION
|
| 354 |
|
|
ldr r2,=0x0401F3FC
|
| 355 |
|
|
str r2,[r1]
|
| 356 |
|
|
|
| 357 |
|
|
ldr r2,[r1,#4]
|
| 358 |
|
|
tst r2,#0x08000000 // Look for expansion pack
|
| 359 |
|
|
orreq r4,r4,#0x01B0 // Power it up if there
|
| 360 |
|
|
str r4,[r0]
|
| 361 |
|
|
|
| 362 |
|
|
#if defined(CYG_HAL_STARTUP_ROM)
|
| 363 |
|
|
// Disable clock switching
|
| 364 |
|
|
mcr p15,0,r0,\
|
| 365 |
|
|
SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
|
| 366 |
|
|
SA11X0_DISABLE_CLOCK_SWITCHING_RM,\
|
| 367 |
|
|
SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE
|
| 368 |
|
|
|
| 369 |
|
|
// Set up processor clock
|
| 370 |
|
|
ldr r1,=SA11X0_PWR_MGR_PLL_CONFIG
|
| 371 |
|
|
ldr r2,=SA11X0_PLL_CLOCK
|
| 372 |
|
|
str r2,[r1]
|
| 373 |
|
|
|
| 374 |
|
|
// Turn clock switching back on
|
| 375 |
|
|
mcr p15,0,r0,\
|
| 376 |
|
|
SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
|
| 377 |
|
|
SA11X0_ENABLE_CLOCK_SWITCHING_RM,\
|
| 378 |
|
|
SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE
|
| 379 |
|
|
nop
|
| 380 |
|
|
nop
|
| 381 |
|
|
#endif
|
| 382 |
|
|
|
| 383 |
|
|
// Pause
|
| 384 |
|
|
ldr r1,=100000
|
| 385 |
|
|
10: sub r1,r1,#1
|
| 386 |
|
|
cmp r1,#0
|
| 387 |
|
|
bne 10b
|
| 388 |
|
|
|
| 389 |
|
|
#ifdef CYGBLD_HAL_STARTUP_ROM_INIT_DRAM
|
| 390 |
|
|
|
| 391 |
|
|
// Initialize DRAM controller
|
| 392 |
|
|
bl 19f
|
| 393 |
|
|
// DRAM controller initialization
|
| 394 |
|
|
dram_table:
|
| 395 |
|
|
.word SA11X0_DRAM0_CAS_0, 0xAAAAAAA7
|
| 396 |
|
|
.word SA11X0_DRAM0_CAS_1, 0xAAAAAAAA
|
| 397 |
|
|
.word SA11X0_DRAM0_CAS_2, 0xAAAAAAAA
|
| 398 |
|
|
// .word SA11X0_STATIC_CONTROL_0, 0x4B384B38
|
| 399 |
|
|
// .word SA11X0_STATIC_CONTROL_1, 0x22212419
|
| 400 |
|
|
.word SA11X0_EXP_BUS_CONFIGURATION, 0x994A994A // 0x90E790E7
|
| 401 |
|
|
.word SA11X0_REFRESH_CONFIGURATION, 0x00302001
|
| 402 |
|
|
.word SA11X0_DRAM2_CAS_0, 0xAAAAAAA7
|
| 403 |
|
|
.word SA11X0_DRAM2_CAS_1, 0xAAAAAAAA
|
| 404 |
|
|
.word SA11X0_DRAM2_CAS_2, 0xAAAAAAAA
|
| 405 |
|
|
// .word SA11X0_STATIC_CONTROL_2, 0x42194449
|
| 406 |
|
|
.word SA11X0_SMROM_CONFIGURATION, 0x00000000 // 0xAFCCAFCC
|
| 407 |
|
|
.word SA11X0_DRAM_CONFIGURATION, 0x0000F354 // 0x72547254 // Disabled
|
| 408 |
|
|
.word 0, 0
|
| 409 |
|
|
|
| 410 |
|
|
19: mov r1,lr // Points to 'dram_table'
|
| 411 |
|
|
ldr r2,[r1],#4 // First control register
|
| 412 |
|
|
20: ldr r3,[r1],#4
|
| 413 |
|
|
str r3,[r2]
|
| 414 |
|
|
ldr r2,[r1],#4 // Next control register
|
| 415 |
|
|
cmp r2,#0
|
| 416 |
|
|
bne 20b
|
| 417 |
|
|
|
| 418 |
|
|
// Enable UART
|
| 419 |
|
|
ldr r1,=SA1110_GPCLK_CONTROL_0
|
| 420 |
|
|
ldr r2,=SA1110_GPCLK_SUS_UART
|
| 421 |
|
|
str r2,[r1]
|
| 422 |
|
|
|
| 423 |
|
|
// Release DRAM hold (set by RESET)
|
| 424 |
|
|
ldr r1,=SA11X0_PWR_MGR_SLEEP_STATUS
|
| 425 |
|
|
ldr r2,=SA11X0_DRAM_CONTROL_HOLD
|
| 426 |
|
|
str r2,[r1]
|
| 427 |
|
|
|
| 428 |
|
|
// Perform 8 reads from unmapped/unenabled DRAM
|
| 429 |
|
|
ldr r1,=SA11X0_RAM_BANK0_BASE
|
| 430 |
|
|
ldr r2,[r1]
|
| 431 |
|
|
ldr r2,[r1]
|
| 432 |
|
|
ldr r2,[r1]
|
| 433 |
|
|
ldr r2,[r1]
|
| 434 |
|
|
ldr r2,[r1]
|
| 435 |
|
|
ldr r2,[r1]
|
| 436 |
|
|
ldr r2,[r1]
|
| 437 |
|
|
ldr r2,[r1]
|
| 438 |
|
|
|
| 439 |
|
|
// Enable DRAM controller
|
| 440 |
|
|
ldr r1,=SA11X0_DRAM_CONFIGURATION
|
| 441 |
|
|
ldr r2,=0x0000F355 // 0x72547255
|
| 442 |
|
|
str r2,[r1]
|
| 443 |
|
|
|
| 444 |
|
|
#endif // CYGBLD_HAL_STARTUP_ROM_INIT_DRAM
|
| 445 |
|
|
|
| 446 |
|
|
// Release peripheral hold (set by RESET)
|
| 447 |
|
|
ldr r1,=SA11X0_PWR_MGR_SLEEP_STATUS
|
| 448 |
|
|
ldr r2,=SA11X0_PERIPHERAL_CONTROL_HOLD
|
| 449 |
|
|
str r2,[r1]
|
| 450 |
|
|
|
| 451 |
|
|
// Wakeup (via power/resume button)
|
| 452 |
|
|
ldr r1,=SA11X0_RESET_STATUS
|
| 453 |
|
|
ldr r2,[r1]
|
| 454 |
|
|
cmp r2,#SA11X0_SLEEP_MODE_RESET
|
| 455 |
|
|
bne 45f
|
| 456 |
|
|
ldr r1,=SA11X0_PWR_MGR_SCRATCHPAD
|
| 457 |
|
|
ldr r1,[r1]
|
| 458 |
|
|
mov pc,r1
|
| 459 |
|
|
nop
|
| 460 |
|
|
45: nop
|
| 461 |
|
|
|
| 462 |
|
|
// Set up a stack [for calling C code]
|
| 463 |
|
|
ldr r1,=__startup_stack
|
| 464 |
|
|
ldr r2,=SA11X0_RAM_BANK0_BASE
|
| 465 |
|
|
orr sp,r1,r2
|
| 466 |
|
|
|
| 467 |
|
|
#ifdef DEBUG_INIT
|
| 468 |
|
|
mrc p15,0,r6,c1,c0,0
|
| 469 |
|
|
bl hexR6
|
| 470 |
|
|
mrc p15,0,r6,c2,c0,0
|
| 471 |
|
|
bl hexR6
|
| 472 |
|
|
mrc p15,0,r6,c3,c0,0
|
| 473 |
|
|
bl hexR6
|
| 474 |
|
|
|
| 475 |
|
|
mrc p15,0,r5,c2,c0,0
|
| 476 |
|
|
ldr r6,=0xFFFFC000
|
| 477 |
|
|
and r5,r5,r6
|
| 478 |
|
|
ldr r4,=0x100/32
|
| 479 |
|
|
bl dump
|
| 480 |
|
|
#endif // DEBUG_INIT
|
| 481 |
|
|
|
| 482 |
|
|
// Create MMU tables
|
| 483 |
|
|
bl hal_mmu_init
|
| 484 |
|
|
|
| 485 |
|
|
#ifdef DEBUG_INIT
|
| 486 |
|
|
ldr r5,=0x00000000
|
| 487 |
|
|
ldr r4,=0x100/32
|
| 488 |
|
|
bl dump
|
| 489 |
|
|
|
| 490 |
|
|
ldr r5,=0xC0020000
|
| 491 |
|
|
ldr r4,=0x100/32
|
| 492 |
|
|
bl dump
|
| 493 |
|
|
|
| 494 |
|
|
mrc p15,0,r5,c2,c0,0
|
| 495 |
|
|
ldr r6,=0xFFFFC000
|
| 496 |
|
|
and r5,r5,r6
|
| 497 |
|
|
// ldr r4,=0x4000/32
|
| 498 |
|
|
ldr r4,=0x100/32
|
| 499 |
|
|
bl dump
|
| 500 |
|
|
#endif // DEBUG_INIT
|
| 501 |
|
|
|
| 502 |
|
|
// Enable MMU
|
| 503 |
|
|
ldr r2,=10f
|
| 504 |
|
|
ldr r1,=MMU_Control_Init|MMU_Control_M
|
| 505 |
|
|
mcr MMU_CP,0,r1,MMU_Control,c0
|
| 506 |
|
|
mov pc,r2
|
| 507 |
|
|
mcr MMU_CP,0,r0,MMU_InvalidateCache,c7,0 // Flush data and instruction cache
|
| 508 |
|
|
mcr MMU_CP,0,r0,MMU_TLB,c7,0 // Flush ID TLBs
|
| 509 |
|
|
10:
|
| 510 |
|
|
nop
|
| 511 |
|
|
nop
|
| 512 |
|
|
nop
|
| 513 |
|
|
|
| 514 |
|
|
#ifdef DEBUG_INIT
|
| 515 |
|
|
ldr r5,=0x00022000
|
| 516 |
|
|
ldr r4,=0xDEADDEAD
|
| 517 |
|
|
str r4,[r5],#4
|
| 518 |
|
|
str r4,[r5],#4
|
| 519 |
|
|
str r4,[r5],#4
|
| 520 |
|
|
str r4,[r5],#4
|
| 521 |
|
|
|
| 522 |
|
|
ldr r5,=0x00022000
|
| 523 |
|
|
ldr r4,=0x100/32
|
| 524 |
|
|
bl dump
|
| 525 |
|
|
#endif // DEBUG_INIT
|
| 526 |
|
|
|
| 527 |
|
|
// Save shadow copy of BCR
|
| 528 |
|
|
ldr r1,=_ipaq_EGPIO
|
| 529 |
|
|
#ifdef DEGUG_INIT
|
| 530 |
|
|
ldr r4,=SA1110_EIO_MIN
|
| 531 |
|
|
#endif // DEBUG_INIT
|
| 532 |
|
|
str r4,[r1]
|
| 533 |
|
|
.endm
|
| 534 |
|
|
|
| 535 |
|
|
#if defined(CYG_HAL_STARTUP_Compaq)
|
| 536 |
|
|
#define CYG_HAL_STARTUP_ROM
|
| 537 |
|
|
#define CYG_HAL_ROM_RESET_USES_JUMP
|
| 538 |
|
|
#endif
|
| 539 |
|
|
|
| 540 |
|
|
#else // defined(CYG_HAL_STARTUP_ROM)
|
| 541 |
|
|
#define PLATFORM_SETUP1
|
| 542 |
|
|
#endif
|
| 543 |
|
|
|
| 544 |
|
|
#define PLATFORM_VECTORS _platform_vectors
|
| 545 |
|
|
.macro _platform_vectors
|
| 546 |
|
|
.globl _ipaq_EGPIO
|
| 547 |
|
|
_ipaq_EGPIO: .long 0 // Extended GPIO shadow
|
| 548 |
|
|
|
| 549 |
|
|
.globl _ipaq_LCD_params
|
| 550 |
|
|
_ipaq_LCD_params:
|
| 551 |
|
|
.short 0,0,0,0 // Coordinates used by virtual keyboard
|
| 552 |
|
|
.short 0,0,0,0
|
| 553 |
|
|
.short 0 // Checksum of above
|
| 554 |
|
|
.endm
|
| 555 |
|
|
|
| 556 |
|
|
/*---------------------------------------------------------------------------*/
|
| 557 |
|
|
/* end of hal_platform_setup.h */
|
| 558 |
|
|
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
|
