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#ifndef CYGONCE_IPAQ_H
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#define CYGONCE_IPAQ_H
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//=============================================================================
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//
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// ipaq.h
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//
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// Platform specific support (register layout, etc)
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors: gthomas, richard.panton@3glab.com
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// Date: 2001-02-24
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// Purpose: Intel SA1110/iPAQ platform specific support routines
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// Description:
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// Usage: #include <cyg/hal/ipaq.h>
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#ifndef __ASSEMBLER__
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//
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// Extended GPIO
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// Note: This register is write-only. Thus a shadow copy is provided so that
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// it may be safely updated/shared by multiple threads.
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//
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extern unsigned long _ipaq_EGPIO; // Shadow copy
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extern unsigned short _ipaq_LCD_params[(4*2)+1]; // Various LCD parameters
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extern void ipaq_EGPIO(unsigned long mask, unsigned long value);
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#endif
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//
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// Signal assertion levels
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//
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#define _LOGIC_ONE(m) (m & 0xFFFF)
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#define _LOGIC_ZERO(m) (m & 0x0000)
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//
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// iPAQ Extended GPIO definitions
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//
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#define SA1110_EGPIO REG16_PTR(0x49000000)
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#define SA1110_EIO_MIN 0x0080
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#define SA1110_EIO_VPP 0x0001
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# define SA1110_EIO_VPP_OFF _LOGIC_ZERO(SA1110_EIO_VPP)
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# define SA1110_EIO_VPP_ON _LOGIC_ONE(SA1110_EIO_VPP)
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#define SA1110_EIO_CF_RESET 0x0002
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# define SA1110_EIO_CF_RESET_DISABLE _LOGIC_ZERO(SA1110_EIO_CF_RESET)
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# define SA1110_EIO_CF_RESET_ENABLE _LOGIC_ONE(SA1110_EIO_CF_RESET)
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#define SA1110_EIO_OPT_RESET 0x0004
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# define SA1110_EIO_OPT_RESET_DISABLE _LOGIC_ZERO(SA1110_EIO_OPT_RESET)
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# define SA1110_EIO_OPT_RESET_ENABLE _LOGIC_ONE(SA1110_EIO_OPT_RESET)
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#define SA1110_EIO_CODEC_RESET 0x0008 // Active LOW
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# define SA1110_EIO_CODEC_RESET_DISABLE _LOGIC_ONE(SA1110_EIO_CODEC_RESET)
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# define SA1110_EIO_CODEC_RESET_ENABLE _LOGIC_ZERO(SA1110_EIO_CODEC_RESET)
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#define SA1110_EIO_OPT_PWR 0x0010
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# define SA1110_EIO_OPT_PWR_OFF _LOGIC_ZERO(SA1110_EIO_OPT_PWR)
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# define SA1110_EIO_OPT_PWR_ON _LOGIC_ONE(SA1110_EIO_OPT_PWR)
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#define SA1110_EIO_OPT 0x0020
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# define SA1110_EIO_OPT_OFF _LOGIC_ZERO(SA1110_EIO_OPT)
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# define SA1110_EIO_OPT_ON _LOGIC_ONE(SA1110_EIO_OPT)
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#define SA1110_EIO_LCD_3V3 0x0040
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# define SA1110_EIO_LCD_3V3_OFF _LOGIC_ZERO(SA1110_EIO_LCD_3V3)
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# define SA1110_EIO_LCD_3V3_ON _LOGIC_ONE(SA1110_EIO_LCD_3V3)
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#define SA1110_EIO_RS232 0x0080
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# define SA1110_EIO_RS232_OFF _LOGIC_ZERO(SA1110_EIO_RS232)
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# define SA1110_EIO_RS232_ON _LOGIC_ONE(SA1110_EIO_RS232)
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#define SA1110_EIO_LCD_CTRL 0x0100
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# define SA1110_EIO_LCD_CTRL_OFF _LOGIC_ZERO(SA1110_EIO_LCD_CTRL)
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# define SA1110_EIO_LCD_CTRL_ON _LOGIC_ONE(SA1110_EIO_LCD_CTRL)
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#define SA1110_EIO_IR 0x0200
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# define SA1110_EIO_IR_OFF _LOGIC_ZERO(SA1110_EIO_IR)
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# define SA1110_EIO_IR_ON _LOGIC_ONE(SA1110_EIO_IR)
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#define SA1110_EIO_AMP 0x0400
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# define SA1110_EIO_AMP_OFF _LOGIC_ZERO(SA1110_EIO_AMP)
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# define SA1110_EIO_AMP_ON _LOGIC_ONE(SA1110_EIO_AMP)
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#define SA1110_EIO_AUDIO 0x0800
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# define SA1110_EIO_AUDIO_OFF _LOGIC_ZERO(SA1110_EIO_AUDIO)
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# define SA1110_EIO_AUDIO_ON _LOGIC_ONE(SA1110_EIO_AUDIO)
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#define SA1110_EIO_MUTE 0x1000
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# define SA1110_EIO_MUTE_OFF _LOGIC_ZERO(SA1110_EIO_MUTE)
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# define SA1110_EIO_MUTE_ON _LOGIC_ONE(SA1110_EIO_MUTE)
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#define SA1110_EIO_IR_FSEL 0x2000
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# define SA1110_EIO_SIR _LOGIC_ZERO(SA1110_EIO_IR_FSEL)
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# define SA1110_EIO_FIR _LOGIC_ONE(SA1110_EIO_IR_FSEL)
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#define SA1110_EIO_LCD_5V 0x4000
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# define SA1110_EIO_LCD_5V_OFF _LOGIC_ZERO(SA1110_EIO_LCD_5V)
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# define SA1110_EIO_LCD_5V_ON _LOGIC_ONE(SA1110_EIO_LCD_5V)
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#define SA1110_EIO_LCD_VDD 0x8000
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# define SA1110_EIO_LCD_VDD_OFF _LOGIC_ZERO(SA1110_EIO_LCD_VDD)
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# define SA1110_EIO_LCD_VDD_ON _LOGIC_ONE(SA1110_EIO_LCD_VDD)
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//
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// Special purpose GPIO interrupt mappings
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//
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#define SA1110_CF_IRQ CYGNUM_HAL_INTERRUPT_GPIO21
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#define SA1110_CF_DETECT CYGNUM_HAL_INTERRUPT_GPIO17
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//
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// GPIO layout
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//
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#define SA1110_GPIO_CF_DETECT 0x00020000 // 0 = Compact Flash detect
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#define SA1110_GPIO_CF_PRESENT _LOGIC_ZERO(SA1110_GPIO_CF_DETECT)
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#define SA1110_GPIO_CF_ABSENT _LOGIC_ONE(SA1110_GPIO_CF_DETECT)
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#define SA1110_GPIO_CF2_DETECT 0x00000200 // 0 = Second slot on 2-slot sleeve
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#define SA1110_GPIO_CF2_PRESENT _LOGIC_ZERO(SA1110_GPIO_CF2_DETECT)
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#define SA1110_GPIO_CF2_ABSENT _LOGIC_ONE(SA1110_GPIO_CF2_DETECT)
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//
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// PCMCIA controller in external sleeve
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//
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#define IPAQ_CF_CTRL 0x1A000000 // Slot 0 (same as single slot)
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#define IPAQ_CF2_CTRL 0x19000000 // Slot 1
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#define IPAQ_CF_CTRL_V5 0x0001 // 5v power enable
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#define IPAQ_CF_CTRL_V5_ENABLE _LOGIC_ZERO(IPAQ_CF_CTRL_V5)
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#define IPAQ_CF_CTRL_V5_DISABLE _LOGIC_ONE(IPAQ_CF_CTRL_V5)
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#define IPAQ_CF_CTRL_V3 0x0002 // 3v power enable
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#define IPAQ_CF_CTRL_V3_ENABLE _LOGIC_ZERO(IPAQ_CF_CTRL_V3)
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#define IPAQ_CF_CTRL_V3_DISABLE _LOGIC_ONE(IPAQ_CF_CTRL_V3)
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#define IPAQ_CF_CTRL_VCC 0x0004 // Vcc power enable
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#define IPAQ_CF_CTRL_V12 0x0008 // 12v power enable
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#define IPAQ_CF_CTRL_RESET 0x0010 // Reset card
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#define IPAQ_CF_CTRL_RESET_ENABLE _LOGIC_ONE(IPAQ_CF_CTRL_RESET)
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#define IPAQ_CF_CTRL_RESET_DISABLE _LOGIC_ZERO(IPAQ_CF_CTRL_RESET)
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#define IPAQ_CF_CTRL_APOE 0x0020 // Auto power off
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#define IPAQ_CF_CTRL_APOE_ENABLE _LOGIC_ONE(IPAQ_CF_CTRL_APOE)
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#define IPAQ_CF_CTRL_APOE_DISABLE _LOGIC_ZERO(IPAQ_CF_CTRL_APOE)
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#define IPAQ_CF_CTRL_CFE 0x0040 // Compact Flash [addressing] enable
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#define IPAQ_CF_CTRL_SOE 0x0080 // Enable signal outputs
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#define IPAQ_CF_CTRL_SOE_ENABLE _LOGIC_ONE(IPAQ_CF_CTRL_SOE)
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#define IPAQ_CF_CTRL_SOE_DISABLE _LOGIC_ZERO(IPAQ_CF_CTRL_SOE)
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#define IPAQ_CF_CTRL_SSP 0x0100 // Slot polarity; slot0=0, slot1=1
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//
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// LCD Controller
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//
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#define SA1110_LCCR0 SA11X0_REGISTER(0x30100000)
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#define SA1110_LCSR SA11X0_REGISTER(0x30100004)
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#define SA1110_DBAR1 SA11X0_REGISTER(0x30100010)
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#define SA1110_DCAR1 SA11X0_REGISTER(0x30100014)
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#define SA1110_DBAR2 SA11X0_REGISTER(0x30100018)
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#define SA1110_DCAR2 SA11X0_REGISTER(0x3010001C)
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#define SA1110_LCCR1 SA11X0_REGISTER(0x30100020)
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#define SA1110_LCCR2 SA11X0_REGISTER(0x30100024)
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#define SA1110_LCCR3 SA11X0_REGISTER(0x30100028)
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/* end of ipaq.h */
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#endif /* CYGONCE_IPAQ_H */
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