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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [sa11x0/] [nano/] [current/] [include/] [nano.h] - Blame information for rev 786

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1 786 skrzyp
#ifndef CYGONCE_HAL_ARM_SA11X0_NANOENGINE_NANOENGINE_H
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#define CYGONCE_HAL_ARM_SA11X0_NANOENGINE_NANOENGINE_H
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/*=============================================================================
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//
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//      nano.h
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//
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//      Platform specific support (register layout, etc)
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    gthomas
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// Contributors: gthomas,hmt
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// Date:         2001-02-12
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// Purpose:      Intel SA1110/NanoEngine platform specific support routines
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// Description:
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// Usage:        #include <cyg/hal/nano.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/system.h>
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#include CYGHWR_MEMORY_LAYOUT_H
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#include <cyg/hal/hal_sa11x0.h>
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// 
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// Signal assertion levels
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//
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#define SA1110_LOGIC_ONE(m)  (m & 0xFFFFFFFF)
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#define SA1110_LOGIC_ZERO(m) (m & 0x00000000)
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//
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// SA1110/NanoEngine Control Status registers
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//
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//
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// Special purpose GPIO interrupt mappings
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//
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//
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// GPIO layout
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//
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// 0-19 unused
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// 20-27 unused
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// 28-31 not implemented
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//
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// BUT PCI action can make use of GPIO 21 and 22 - but that's all set up in
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// HAL_PCI_INIT() below, as it should be.
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#define SA1110_GPIO_GPDR_DEFAULT_VALUE 0 // No GPIO is used
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#define SA1110_GPIO_GAFR_DEFAULT_VALUE 0 // No alternates
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#define SA1110_GPIO_GRER_DEFAULT_VALUE 0 // No edge detection at all
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#define SA1110_GPIO_GFER_DEFAULT_VALUE 0 // No edge detection at all
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#define SA1110_GPIO_GPOSR_DEFAULT_VALUE 0xffffffff // Set all 1s
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#define SA1110_GPIO_GPOCR_DEFAULT_VALUE 0x00000000 // and leave them set
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// ------------------------------------------------------------------------
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//
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// Interrupt numbers
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//
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#define SA1110_GPIO_INTR_ETH0 0 // CYGNUM_HAL_INTERRUPT_GPIO0
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#define SA1110_GPIO_INTR_ETH1 1 // CYGNUM_HAL_INTERRUPT_GPIO1
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// ------------------------------------------------------------------------
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//
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// PCI stuff
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#ifndef __ASSEMBLER__
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#ifdef CYGPKG_IO_PCI
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#define CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_BASE ((cyg_uint32)(&CYGMEM_SECTION_pci_window[0]))
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#define CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_SIZE ((cyg_uint32)(CYGMEM_SECTION_pci_window_SIZE))
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extern cyg_uint32 cyg_pci_window_real_base;
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#define HAL_PCI_INIT() CYG_MACRO_START                                          \
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    cyg_uint32 t;                                                               \
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    /* Set up the DRAM system so that an alternate master can take control. */  \
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    /* This is described in section 10.8 pp10-67..68 of the SA1110 book.    */  \
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    /* This is how the nanoBridge allows the 82559 ethernet devices to      */  \
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    /* access main memory.  Apparently.  So much for documentation.         */  \
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                                                                                \
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    /* Set GPIO pin direction: 21 out, 22 in.                               */  \
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    t = *SA11X0_GPIO_PIN_DIRECTION;                                             \
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    t |= SA11X0_GPIO_PIN_21;                                                    \
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    t &=~SA11X0_GPIO_PIN_22;                                                    \
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    *SA11X0_GPIO_PIN_DIRECTION = t;                                             \
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                                                                                \
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    /* Set alternate functions for GPIO 21 and 22.                          */  \
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    t = *SA11X0_GPIO_ALTERNATE_FUNCTION;                                        \
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    t |= SA11X0_GPIO_PIN_21 + SA11X0_GPIO_PIN_22;                               \
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    *SA11X0_GPIO_ALTERNATE_FUNCTION = t;                                        \
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                                                                                \
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    /* Set the Test Unit Control Register to enable external memory mastery */  \
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    t = *SA11X0_TUCR;                                                           \
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    t &=~SA11X0_TUCR_RESERVED_BITS;                                             \
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    t |= SA11X0_TUCR_EXTERNAL_MEMORY_MASTER;                                    \
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    *SA11X0_TUCR = t;                                                           \
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                                                                                \
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    /* Set the interrupts on GPIO0 and GPIO1 to be falling-edge */              \
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                                                                                \
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    /* GPIO0 and GPIO1 be inputs: */                                            \
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    t = *SA11X0_GPIO_PIN_DIRECTION;                                             \
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    t &=~(SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1);                               \
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    *SA11X0_GPIO_PIN_DIRECTION = t;                                             \
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    /* no rising edge */                                                        \
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    t = *SA11X0_GPIO_RISING_EDGE_DETECT;                                        \
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    t &=~(SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1);                               \
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    *SA11X0_GPIO_RISING_EDGE_DETECT = t;                                        \
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    /* falling edge on */                                                       \
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    t = *SA11X0_GPIO_FALLING_EDGE_DETECT;                                       \
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    t |= (SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1);                               \
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    *SA11X0_GPIO_FALLING_EDGE_DETECT = t;                                       \
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    /* cancel any pending edges */                                              \
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    t = (SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1);                                \
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    *SA11X0_GPIO_EDGE_DETECT_STATUS = t;                                        \
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                                                                                \
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    /* and disconnect ethernet devices from the PCI bus so that they */         \
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    /* respond to being scanned a second time - because RedBoot will */         \
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    /* likely have enabled one or both of them already.              */         \
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    /* We know that the two ethers are device #1 and #2:             */         \
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    t = 0;                                                                      \
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    HAL_PCI_CFG_WRITE_UINT16( 0, CYG_PCI_DEV_MAKE_DEVFN(1,0),                   \
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                              CYG_PCI_CFG_COMMAND,            t );              \
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    t = 0;                                                                      \
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    HAL_PCI_CFG_WRITE_UINT16( 0, CYG_PCI_DEV_MAKE_DEVFN(2,0),                   \
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                              CYG_PCI_CFG_COMMAND,            t );              \
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CYG_MACRO_END
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// This is nasty in the nanoBridge; it does NOT correctly return -1's for
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// empty config slots, it lies and gives the impression of there being lots
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// of extra nothing devices.  So we have to fake it.
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// Compute address necessary to access PCI config space for the given bus
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// and device.  With faked gaps...
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#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset )                      \
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    ({                                                                          \
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    cyg_uint32 __addr;                                                          \
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    cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn);                            \
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    __addr = (0 == __bus) ? 0x18A00000 : 0xffffffffu;                           \
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    __addr |= (1 == __dev || 2 == __dev) ? (__dev << 16) :  0xffffffffu;        \
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    __addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8;                                 \
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    __addr |= __offset;                                                         \
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    __addr;                                                                     \
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    })
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// Not used.  For experiments, or for a more general PCI bus...
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#define scan_all_HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset )             \
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    ({                                                                          \
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    cyg_uint32 __addr;                                                          \
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    cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn);                            \
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    __addr = (0 == __bus) ? 0x18A00000 : 0xffffffffu;                           \
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    __addr |= __dev << 16;                                                      \
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    __addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8;                                 \
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    __addr |= __offset;                                                         \
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    __addr;                                                                     \
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    })
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#define HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, __action, __type )   \
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{                                                                                       \
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    cyg_uint32 __doaddr = HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset );           \
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    if ( 0xffffffffu == __doaddr )                                                      \
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        __val = (__type)0xffffffffu;                                                    \
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    else {                                                                              \
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        __action( __doaddr, __val );                                                    \
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        /* nasty kludge to detect the absence of a second eth device on nanoEngines     \
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         * rather than commEngines. The vendor should never be 0 or 256. */             \
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        if ( (__offset) == CYG_PCI_CFG_VENDOR && ((__val) == 0 || (__val) == 256) )     \
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            __val = (__type)0xffffffffu;                                                \
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    }                                                                                   \
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}
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// Read/write a value from the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val )   \
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     HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_READ_UINT8  , cyg_uint8  )
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#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val )  \
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     HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_READ_UINT16 , cyg_uint16 )
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#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val )  \
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     HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_READ_UINT32 , cyg_uint32 )
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#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val )  \
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     HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_WRITE_UINT8 , cyg_uint8  )
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#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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     HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_WRITE_UINT16, cyg_uint16 )
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#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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     HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_WRITE_UINT32, cyg_uint32 )
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//-----------------------------------------------------------------------------
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// Resources
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// Map PCI device resources starting from these addresses in PCI space.
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#define HAL_PCI_ALLOC_BASE_MEMORY       (0x00000000)
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#define HAL_PCI_ALLOC_BASE_IO           (0x00000000)
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// This is where the PCI spaces are mapped in the CPU's address space.
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#define HAL_PCI_PHYSICAL_MEMORY_BASE    (0x18620000)
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#define HAL_PCI_PHYSICAL_IO_BASE        (0x18200000)
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// Translate the PCI interrupt requested by the device (INTA#, INTB#,
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// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) {  \
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    cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn);                    \
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    __valid = false;                                                    \
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    if ( 1 == __dev || 2 == __dev ) {                                   \
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        __vec = ( 1 == __dev ) ? SA1110_GPIO_INTR_ETH0                  \
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                               : SA1110_GPIO_INTR_ETH1;                 \
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        __valid = true;                                                 \
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    }                                                                   \
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}
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#endif // CYGPKG_IO_PCI
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#endif // #ifndef __ASSEMBLER__
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// ------------------------------------------------------------------------
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#endif // CYGONCE_HAL_ARM_SA11X0_NANOENGINE_NANOENGINE_H
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// EOF nano.h

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