OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [sa11x0/] [var/] [current/] [cdl/] [hal_arm_sa11x0.cdl] - Blame information for rev 838

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
# ====================================================================
2
#
3
#      hal_arm_sa11x0.cdl
4
#
5
#      ARM SA11x0 architectural HAL package configuration data
6
#
7
# ====================================================================
8
## ####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
12
##
13
## eCos is free software; you can redistribute it and/or modify it under
14
## the terms of the GNU General Public License as published by the Free
15
## Software Foundation; either version 2 or (at your option) any later
16
## version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT
19
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License
24
## along with eCos; if not, write to the Free Software Foundation, Inc.,
25
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
26
##
27
## As a special exception, if other files instantiate templates or use
28
## macros or inline functions from this file, or you compile this file
29
## and link it with other works to produce a work based on this file,
30
## this file does not by itself cause the resulting work to be covered by
31
## the GNU General Public License. However the source code for this file
32
## must still be made available in accordance with section (3) of the GNU
33
## General Public License v2.
34
##
35
## This exception does not invalidate any other reasons why a work based
36
## on this file might be covered by the GNU General Public License.
37
## -------------------------------------------
38
## ####ECOSGPLCOPYRIGHTEND####
39
# ====================================================================
40
######DESCRIPTIONBEGIN####
41
#
42
# Author(s):      gthomas
43
# Original data:  gthomas
44
# Contributors:
45
# Date:           2000-05-08
46
#
47
#####DESCRIPTIONEND####
48
#
49
# ====================================================================
50
cdl_package CYGPKG_HAL_ARM_SA11X0 {
51
    display       "ARM SA11X0 architecture"
52
    parent        CYGPKG_HAL_ARM
53
    hardware
54
    include_dir   cyg/hal
55
    define_header hal_arm_sa11x0.h
56
    description   "
57
        This HAL variant package provides generic
58
        support for the Intel StrongARM SA11x0 processors. It is also
59
        necessary to select a specific target platform HAL
60
        package."
61
 
62
    implements    CYGINT_HAL_ARM_ARCH_STRONGARM
63
    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
64
    implements    CYGINT_PROFILE_HAL_TIMER
65
 
66
    # Let the architectural HAL see this variant's interrupts file -
67
    # the SA11x0 has no variation between targets here.
68
    define_proc {
69
        puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H "
70
        puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
71
 
72
        puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
73
    }
74
 
75
    compile       hal_diag.c sa11x0_misc.c
76
 
77
    cdl_option CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK {
78
        display       "Processor clock rate"
79
        active_if     { CYG_HAL_STARTUP == "ROM" }
80
        flavor        data
81
        legal_values  59000 73700 88500 103200 118000 132700 147500 162200 176900 191700 206400 221200
82
        default_value { CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
83
                        CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 221200}
84
        description   "
85
           The SA-1100 processor can run at various frequencies.
86
           These values are expressed in KHz.  Note that there are
87
           several steppings of the SA-1100 rated to run at different
88
           maximum frequencies.  Check the specs to make sure that your
89
           particular processor can run at the rate you select here."
90
    }
91
 
92
    # Real-time clock/counter specifics
93
    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
94
        display       "Real-time clock constants"
95
        flavor        none
96
        no_define
97
 
98
        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
99
            display       "Real-time clock numerator"
100
            flavor        data
101
            default_value 1000000000
102
        }
103
        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
104
            display       "Real-time clock denominator"
105
            flavor        data
106
            default_value 100
107
            description   "
108
              This option selects the heartbeat rate for the real-time clock.
109
              The rate is specified in ticks per second.  Change this value
110
              with caution - too high and your system will become saturated
111
              just handling clock interrupts, too low and some operations
112
              such as thread scheduling may become sluggish."
113
        }
114
        cdl_option CYGNUM_HAL_RTC_PERIOD {
115
            display       "Real-time clock period"
116
            flavor        data
117
            default_value (3686400/CYGNUM_HAL_RTC_DENOMINATOR)        ;# Clock for OS Timer is 3.6864MHz
118
        }
119
    }
120
 
121
    # Control over hardware layout.
122
    cdl_interface     CYGHWR_HAL_ARM_SA11X0_UART1 {
123
        display   "UART1 available as diagnostic/debug channel"
124
        description "
125
          The SA11x0 chip has multiple serial channels which may be
126
          used for different things on different platforms.  This
127
          interface allows a platform to indicate that the specified
128
          serial port can be used as a diagnostic and/or debug channel."
129
    }
130
 
131
    cdl_interface     CYGHWR_HAL_ARM_SA11X0_UART3 {
132
        display   "UART3 available as diagnostic/debug channel"
133
        description "
134
          The SA11x0 chip has multiple serial channels which may be
135
          used for different things on different platforms.  This
136
          interface allows a platform to indicate that the specified
137
          serial port can be used as a diagnostic and/or debug channel."
138
    }
139
 
140
    cdl_option CYGPKG_HAL_ARM_SA11X0_TESTS {
141
        display "SA11x0 HAL tests"
142
        flavor  data
143
        no_define
144
        calculated { "tests/mmap_test" }
145
        description   "
146
        This option specifies the set of tests for the SA11x0 HAL."
147
    }
148
 
149
 
150
    cdl_component CYGPKG_REDBOOT_HAL_SA11X0_OPTIONS {
151
        display       "Redboot HAL variant options"
152
        flavor        none
153
        no_define
154
        parent        CYGPKG_REDBOOT
155
        active_if     CYGPKG_REDBOOT
156
 
157
        # RedBoot details
158
        requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xc0008000 }
159
        define_proc {
160
            puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
161
        }
162
    }
163
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.