1 |
786 |
skrzyp |
#ifndef CYGONCE_HAL_MM_H
|
2 |
|
|
#define CYGONCE_HAL_MM_H
|
3 |
|
|
|
4 |
|
|
//=============================================================================
|
5 |
|
|
//
|
6 |
|
|
// hal_mm.h
|
7 |
|
|
//
|
8 |
|
|
// ARM SA11x0 MM common definitions
|
9 |
|
|
//
|
10 |
|
|
//=============================================================================
|
11 |
|
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
12 |
|
|
// -------------------------------------------
|
13 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
14 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
15 |
|
|
//
|
16 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
17 |
|
|
// the terms of the GNU General Public License as published by the Free
|
18 |
|
|
// Software Foundation; either version 2 or (at your option) any later
|
19 |
|
|
// version.
|
20 |
|
|
//
|
21 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
22 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
23 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
24 |
|
|
// for more details.
|
25 |
|
|
//
|
26 |
|
|
// You should have received a copy of the GNU General Public License
|
27 |
|
|
// along with eCos; if not, write to the Free Software Foundation, Inc.,
|
28 |
|
|
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
29 |
|
|
//
|
30 |
|
|
// As a special exception, if other files instantiate templates or use
|
31 |
|
|
// macros or inline functions from this file, or you compile this file
|
32 |
|
|
// and link it with other works to produce a work based on this file,
|
33 |
|
|
// this file does not by itself cause the resulting work to be covered by
|
34 |
|
|
// the GNU General Public License. However the source code for this file
|
35 |
|
|
// must still be made available in accordance with section (3) of the GNU
|
36 |
|
|
// General Public License v2.
|
37 |
|
|
//
|
38 |
|
|
// This exception does not invalidate any other reasons why a work based
|
39 |
|
|
// on this file might be covered by the GNU General Public License.
|
40 |
|
|
// -------------------------------------------
|
41 |
|
|
// ####ECOSGPLCOPYRIGHTEND####
|
42 |
|
|
//=============================================================================
|
43 |
|
|
//#####DESCRIPTIONBEGIN####
|
44 |
|
|
//
|
45 |
|
|
// Author(s): gthomas
|
46 |
|
|
// Contributors: hmt
|
47 |
|
|
// Travis C. Furrer <furrer@mit.edu>
|
48 |
|
|
// Date: 2000-12-13
|
49 |
|
|
// Purpose: ARM SA11x0 MM common definitions
|
50 |
|
|
// Description: The macros defined here provide common definitions for
|
51 |
|
|
// memory management initialization.
|
52 |
|
|
// Usage:
|
53 |
|
|
// #include <cyg/hal/hal_mm.h>
|
54 |
|
|
// ...
|
55 |
|
|
//
|
56 |
|
|
//
|
57 |
|
|
//####DESCRIPTIONEND####
|
58 |
|
|
//
|
59 |
|
|
//=============================================================================
|
60 |
|
|
|
61 |
|
|
|
62 |
|
|
// -------------------------------------------------------------------------
|
63 |
|
|
// MMU initialization:
|
64 |
|
|
//
|
65 |
|
|
// These structures are laid down in memory to define the translation
|
66 |
|
|
// table.
|
67 |
|
|
//
|
68 |
|
|
|
69 |
|
|
/*
|
70 |
|
|
* SA-1100 Translation Table Base Bit Masks
|
71 |
|
|
*/
|
72 |
|
|
#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
|
73 |
|
|
|
74 |
|
|
/*
|
75 |
|
|
* SA-1100 Domain Access Control Bit Masks
|
76 |
|
|
*/
|
77 |
|
|
#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
|
78 |
|
|
#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
|
79 |
|
|
#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
|
80 |
|
|
|
81 |
|
|
struct ARM_MMU_FIRST_LEVEL_FAULT {
|
82 |
|
|
unsigned int id : 2;
|
83 |
|
|
unsigned int sbz : 30;
|
84 |
|
|
};
|
85 |
|
|
#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
|
86 |
|
|
|
87 |
|
|
struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
|
88 |
|
|
unsigned int id : 2;
|
89 |
|
|
unsigned int imp : 2;
|
90 |
|
|
unsigned int domain : 4;
|
91 |
|
|
unsigned int sbz : 1;
|
92 |
|
|
unsigned int base_address : 23;
|
93 |
|
|
};
|
94 |
|
|
#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
|
95 |
|
|
|
96 |
|
|
struct ARM_MMU_FIRST_LEVEL_SECTION {
|
97 |
|
|
unsigned int id : 2;
|
98 |
|
|
unsigned int b : 1;
|
99 |
|
|
unsigned int c : 1;
|
100 |
|
|
unsigned int imp : 1;
|
101 |
|
|
unsigned int domain : 4;
|
102 |
|
|
unsigned int sbz0 : 1;
|
103 |
|
|
unsigned int ap : 2;
|
104 |
|
|
unsigned int sbz1 : 8;
|
105 |
|
|
unsigned int base_address : 12;
|
106 |
|
|
};
|
107 |
|
|
#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
|
108 |
|
|
|
109 |
|
|
struct ARM_MMU_FIRST_LEVEL_RESERVED {
|
110 |
|
|
unsigned int id : 2;
|
111 |
|
|
unsigned int sbz : 30;
|
112 |
|
|
};
|
113 |
|
|
#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
|
114 |
|
|
|
115 |
|
|
#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
|
116 |
|
|
(unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
|
117 |
|
|
|
118 |
|
|
#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
|
119 |
|
|
|
120 |
|
|
#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
|
121 |
|
|
cacheable, bufferable, perm) \
|
122 |
|
|
CYG_MACRO_START \
|
123 |
|
|
register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
|
124 |
|
|
\
|
125 |
|
|
desc.word = 0; \
|
126 |
|
|
desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
|
127 |
|
|
desc.section.domain = 0; \
|
128 |
|
|
desc.section.c = (cacheable); \
|
129 |
|
|
desc.section.b = (bufferable); \
|
130 |
|
|
desc.section.ap = (perm); \
|
131 |
|
|
desc.section.base_address = (actual_base); \
|
132 |
|
|
*ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
|
133 |
|
|
= desc.word; \
|
134 |
|
|
CYG_MACRO_END
|
135 |
|
|
|
136 |
|
|
#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
|
137 |
|
|
{ int i; int j = abase; int k = vbase; \
|
138 |
|
|
for (i = size; i > 0 ; i--,j++,k++) \
|
139 |
|
|
{ \
|
140 |
|
|
ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
|
141 |
|
|
} \
|
142 |
|
|
}
|
143 |
|
|
|
144 |
|
|
union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
|
145 |
|
|
unsigned long word;
|
146 |
|
|
struct ARM_MMU_FIRST_LEVEL_FAULT fault;
|
147 |
|
|
struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
|
148 |
|
|
struct ARM_MMU_FIRST_LEVEL_SECTION section;
|
149 |
|
|
struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
|
150 |
|
|
};
|
151 |
|
|
|
152 |
|
|
#define ARM_UNCACHEABLE 0
|
153 |
|
|
#define ARM_CACHEABLE 1
|
154 |
|
|
#define ARM_UNBUFFERABLE 0
|
155 |
|
|
#define ARM_BUFFERABLE 1
|
156 |
|
|
|
157 |
|
|
#define ARM_ACCESS_PERM_NONE_NONE 0
|
158 |
|
|
#define ARM_ACCESS_PERM_RO_NONE 0
|
159 |
|
|
#define ARM_ACCESS_PERM_RO_RO 0
|
160 |
|
|
#define ARM_ACCESS_PERM_RW_NONE 1
|
161 |
|
|
#define ARM_ACCESS_PERM_RW_RO 2
|
162 |
|
|
#define ARM_ACCESS_PERM_RW_RW 3
|
163 |
|
|
|
164 |
|
|
/*
|
165 |
|
|
* Initialization for the Domain Access Control Register
|
166 |
|
|
*/
|
167 |
|
|
#define ARM_ACCESS_DACR_DEFAULT ( \
|
168 |
|
|
ARM_ACCESS_TYPE_MANAGER(0) | \
|
169 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(1) | \
|
170 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(2) | \
|
171 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(3) | \
|
172 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(4) | \
|
173 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(5) | \
|
174 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(6) | \
|
175 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(7) | \
|
176 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(8) | \
|
177 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(9) | \
|
178 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(10) | \
|
179 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(11) | \
|
180 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(12) | \
|
181 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(13) | \
|
182 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(14) | \
|
183 |
|
|
ARM_ACCESS_TYPE_NO_ACCESS(15) )
|
184 |
|
|
|
185 |
|
|
// ------------------------------------------------------------------------
|
186 |
|
|
#endif // ifndef CYGONCE_HAL_MM_H
|
187 |
|
|
// End of hal_mm.h
|
188 |
|
|
|
189 |
|
|
|
190 |
|
|
|
191 |
|
|
|
192 |
|
|
|