OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [snds/] [current/] [cdl/] [hal_arm_snds.cdl] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
#==========================================================================
2
#
3
#      hal_arm_snds.cdl
4
#
5
#
6
#
7
#==========================================================================
8
## ####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
12
##
13
## eCos is free software; you can redistribute it and/or modify it under
14
## the terms of the GNU General Public License as published by the Free
15
## Software Foundation; either version 2 or (at your option) any later
16
## version.
17
##
18
## eCos is distributed in the hope that it will be useful, but WITHOUT
19
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
## for more details.
22
##
23
## You should have received a copy of the GNU General Public License
24
## along with eCos; if not, write to the Free Software Foundation, Inc.,
25
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
26
##
27
## As a special exception, if other files instantiate templates or use
28
## macros or inline functions from this file, or you compile this file
29
## and link it with other works to produce a work based on this file,
30
## this file does not by itself cause the resulting work to be covered by
31
## the GNU General Public License. However the source code for this file
32
## must still be made available in accordance with section (3) of the GNU
33
## General Public License v2.
34
##
35
## This exception does not invalidate any other reasons why a work based
36
## on this file might be covered by the GNU General Public License.
37
## -------------------------------------------
38
## ####ECOSGPLCOPYRIGHTEND####
39
#==========================================================================
40
######DESCRIPTIONBEGIN####
41
#
42
# Author(s):    gthomas
43
# Contributors: gthomas, jskov
44
#               Grant Edwards 
45
# Date:         2001-07-31
46
# Purpose:
47
# Description:
48
#
49
#####DESCRIPTIONEND####
50
#
51
#========================================================================*/
52
 
53
 
54
cdl_package CYGPKG_HAL_ARM_SNDS {
55
    display       "Samsung SNDS Evaluation Board"
56
    parent        CYGPKG_HAL_ARM
57
    define_header hal_arm_snds.h
58
    include_dir   cyg/hal
59
    hardware
60
    description   "
61
        The SNDS  HAL package provides the support needed to run
62
        eCos on a Samsung SNDS Eval board"
63
 
64
    compile       hal_diag.c snds100_misc.c
65
 
66
    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
67
    implements    CYGINT_HAL_DEBUG_GDB_STUBS
68
    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
69
    implements    CYGINT_HAL_ARM_ARCH_ARM7
70
    implements    CYGINT_HAL_ARM_THUMB_ARCH
71
    # FIXME: Add endian option
72
 
73
    define_proc {
74
        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   "
75
        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H "
76
        puts $::cdl_header ""
77
        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"ARM 7TDMI\""
78
        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Samsung SNDS\""
79
        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
80
        puts $::cdl_header ""
81
    }
82
 
83
    cdl_component CYG_HAL_STARTUP {
84
        display       "Startup type"
85
        flavor        data
86
        legal_values  {"RAM" "ROM"}
87
        default_value {"RAM"}
88
        no_define
89
        define -file system.h CYG_HAL_STARTUP
90
        description   "
91
           When targetting the SNDS board it is possible to build
92
           the system for either RAM bootstrap or ROM bootstrap.
93
           RAM bootstrap generally requires that the board
94
           is equipped with ROMs containing a suitable ROM monitor or
95
           equivalent software that allows GDB to download the eCos
96
           application on to the board. The ROM bootstrap typically
97
           requires that the eCos application be blown into EPROMs or
98
           equivalent technology."
99
    }
100
 
101
    cdl_component CYG_HAL_CPUTYPE {
102
        display       "cpu type"
103
        flavor        data
104
        legal_values  {"KS32C5000A" "S3C4510A"}
105
        default_value {"S3C4510A"}
106
        no_define
107
        define -file system.h CYG_HAL_CPUTYPE
108
        description   "Which version of processor is on board."
109
    }
110
 
111
    cdl_component CYGNUM_HAL_CPUCLOCK {
112
        display       "cpu clock"
113
        flavor        data
114
        legal_values  10000000 to 100000000
115
        default_value 50000000
116
        no_define
117
        define -file system.h CYGNUM_HAL_CPUCLOCK
118
        description   "Frequency of cpu clock in Hz."
119
    }
120
 
121
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
122
        display      "Number of diag/debug communication channels on the board"
123
        flavor       data
124
        calculated   2
125
    }
126
 
127
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
128
        display      "Default console channel."
129
        flavor       data
130
        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
131
        calculated   0
132
    }
133
 
134
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
135
        display          "Debug serial port"
136
        flavor data
137
        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
138
        default_value    0
139
        description      "The SNDS board has two diag/debug
140
                          serial ports. This option chooses which port will
141
                          be used to connect to a host running GDB."
142
     }
143
 
144
     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
145
         display          "Diagnostic serial port"
146
         flavor data
147
         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
148
         default_value    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
149
         description      "
150
            The SNDS board has two diag/debug serial ports.  This option
151
            chooses which port will be used for diagnostic output."
152
     }
153
 
154
    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
155
        display       "Console/GDB serial port baud rate"
156
        flavor        data
157
        legal_values  9600 19200 38400 57600 115200
158
        default_value 38400
159
        description   "
160
            This option controls the default baud rate used for the
161
            Console/GDB connection."
162
    }
163
 
164
    # Real-time clock/counter specifics
165
    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
166
        display       "Real-time clock constants"
167
        flavor        none
168
 
169
        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
170
            display       "Real-time clock numerator"
171
            flavor        data
172
            default_value 1000000000
173
        }
174
        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
175
            display       "Real-time clock denominator"
176
            flavor        data
177
            default_value 100
178
        }
179
        cdl_option CYGNUM_HAL_RTC_PERIOD {
180
            display       "Real-time clock period"
181
            flavor        data
182
           default_value (CYGNUM_HAL_CPUCLOCK/CYGNUM_HAL_RTC_DENOMINATOR)
183
        }
184
    }
185
 
186
    cdl_component CYGBLD_GLOBAL_OPTIONS {
187
        display "Global build options"
188
        flavor  none
189
        parent  CYGPKG_NONE
190
        description   "
191
            Global build options including control over
192
            compiler flags, linker flags and choice of toolchain."
193
 
194
        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
195
            display "Global command prefix"
196
            flavor  data
197
            no_define
198
            default_value { "arm-eabi"}
199
            description "
200
                This option specifies the command prefix used when
201
                invoking the build tools."
202
        }
203
 
204
        cdl_option CYGBLD_GLOBAL_CFLAGS {
205
            display "Global compiler flags"
206
            flavor  data
207
            no_define
208
            default_value { CYGBLD_GLOBAL_WARNFLAGS . CYGBLD_ARCH_CFLAGS .
209
                (CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9" ? "-mcpu=arm9" : "-mcpu=arm7tdmi") .
210
                " -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions " }
211
            description   "
212
                This option controls the global compiler flags which are used to
213
                compile all packages by default. Individual packages may define
214
                options which override these global flags."
215
        }
216
 
217
        cdl_option CYGBLD_GLOBAL_LDFLAGS {
218
            display "Global linker flags"
219
            flavor  data
220
            no_define
221
            default_value { CYGBLD_ARCH_LDFLAGS .
222
                            (CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9" ? "-mcpu=arm9" : "-mcpu=arm7tdmi") .
223
                            " -g -nostdlib -Wl,--gc-sections -Wl,-static" }
224
            description   "
225
                This option controls the global linker flags. Individual
226
                packages may define options which override these global flags."
227
        }
228
 
229
        cdl_option CYGBLD_BUILD_GDB_STUBS {
230
            display "Build GDB stub ROM image"
231
            default_value 0
232
            requires { CYG_HAL_STARTUP == "ROM" }
233
            requires CYGSEM_HAL_ROM_MONITOR
234
            requires CYGBLD_BUILD_COMMON_GDB_STUBS
235
            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
236
            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
237
            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
238
            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
239
            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
240
            no_define
241
            description "
242
                This option enables the building of the GDB stubs for the
243
                board. The common HAL controls takes care of most of the
244
                build process, but the final conversion from ELF image to
245
                binary data is handled by the platform CDL, allowing
246
                relocation of the data if necessary."
247
 
248
            make -priority 320 {
249
                /bin/gdb_module.bin : /bin/gdb_module.img
250
                $(OBJCOPY) -O binary $< $@
251
            }
252
        }
253
    }
254
 
255
    cdl_component CYGHWR_MEMORY_LAYOUT {
256
        display "Memory layout"
257
        flavor data
258
        no_define
259
        calculated { CYG_HAL_STARTUP == "RAM" ? "arm_snds_ram" : \
260
                                                "arm_snds_rom" }
261
 
262
        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
263
            display "Memory layout linker script fragment"
264
            flavor data
265
            no_define
266
            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
267
            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
268
                                                    ""}
269
        }
270
 
271
        cdl_option CYGHWR_MEMORY_LAYOUT_H {
272
            display "Memory layout header file"
273
            flavor data
274
            no_define
275
            define -file system.h CYGHWR_MEMORY_LAYOUT_H
276
            calculated { CYG_HAL_STARTUP == "RAM" ? "" : \
277
                                                    ""}
278
        }
279
    }
280
 
281
 
282
    cdl_option CYGSEM_HAL_ROM_MONITOR {
283
        display       "Behave as a ROM monitor"
284
        flavor        bool
285
        default_value 0
286
        parent        CYGPKG_HAL_ROM_MONITOR
287
        requires      { CYG_HAL_STARTUP == "ROM" }
288
        description   "
289
            Enable this option if this program is to be used as a ROM monitor,
290
            i.e. applications will be loaded into RAM on the board, and this
291
            ROM monitor may process exceptions or interrupts generated from the
292
            application. This enables features such as utilizing a separate
293
            interrupt stack when exceptions are generated."
294
    }
295
 
296
    cdl_component CYGPKG_CYGMON_HAL_OPTIONS {
297
        display       "CygMon HAL options"
298
        flavor        none
299
        no_define
300
        parent        CYGPKG_CYGMON
301
        active_if     CYGPKG_CYGMON
302
        requires      CYGPKG_IO_SERIAL_ARM_SNDS
303
        requires      {(CYGDAT_CYGMON_CONSOLE_DEV != "\"/dev/ser0\"") || \
304
                       (CYGPKG_IO_SERIAL_ARM_SNDS_SERIAL0 &&              \
305
                       (CYGNUM_IO_SERIAL_ARM_SNDS_SERIAL0_BUFSIZE == 512))}
306
        requires      {(CYGDAT_CYGMON_CONSOLE_DEV != "\"/dev/ser1\"") || \
307
                       (CYGPKG_IO_SERIAL_ARM_SNDS_SERIAL1 &&              \
308
                       (CYGNUM_IO_SERIAL_ARM_SNDS_SERIAL1_BUFSIZE == 512))}
309
        description   "
310
            This option also lists the target's requirements for a valid CygMon
311
            configuration."
312
 
313
 
314
        cdl_option CYGDAT_CYGMON_CONSOLE_DEV {
315
            display       "Serial port for default console"
316
            flavor data
317
            default_value { "\"/dev/ser0\"" }
318
            description   "
319
                This option selects the physical device to use as the default
320
                console device for CygMon."
321
 
322
        }
323
 
324
        cdl_option CYGBLD_BUILD_CYGMON_BIN {
325
            display       "Build CygMon ROM binary image"
326
            active_if     CYGBLD_BUILD_CYGMON
327
            default_value 1
328
            no_define
329
            description "This option enables the conversion of the CygMon ELF
330
                         image to a binary image suitable for ROM programming."
331
 
332
            make -priority 325 {
333
                /bin/cygmon.bin : /bin/cygmon.elf
334
                $(OBJCOPY) --strip-debug --change-addresses=0xFC060000 $< $(@:.bin=.img)
335
                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
336
                $(OBJCOPY) -O binary $< $@
337
            }
338
        }
339
    }
340
 
341
    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
342
        display       "Redboot HAL options"
343
        flavor        none
344
        no_define
345
        parent        CYGPKG_REDBOOT
346
        active_if     CYGPKG_REDBOOT
347
        description   "
348
            This option lists the target's requirements for a valid Redboot
349
            configuration."
350
 
351
        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
352
            display       "Build Redboot ROM binary image"
353
            active_if     CYGBLD_BUILD_REDBOOT
354
            default_value 1
355
            no_define
356
            description "This option enables the conversion of the Redboot ELF
357
                         image to a binary image suitable for ROM programming."
358
 
359
            make -priority 325 {
360
                /bin/redboot.bin : /bin/redboot.elf
361
                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
362
                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
363
                $(OBJCOPY) -O binary $< $@
364
            }
365
        }
366
    }
367
 
368
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.