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skrzyp |
#ifndef CYGONCE_HAL_CACHE_H
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#define CYGONCE_HAL_CACHE_H
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//=============================================================================
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//
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// hal_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg, gthomas
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// Contributors: nickg, gthomas
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// Date: 1998-09-28
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/plf_io.h>
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//-----------------------------------------------------------------------------
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// Cache dimensions - one unified cache
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#define HAL_CACHE_UNIFIED
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#define HAL_UCACHE_SIZE 0x2000 // Size of cache in bytes
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#define HAL_UCACHE_LINE_SIZE 16 // Size of a cache line
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#define HAL_UCACHE_WAYS 2 // Associativity of the cache
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#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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//-----------------------------------------------------------------------------
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// Global control of cache
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// Enable the cache
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#define HAL_UCACHE_ENABLE() \
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CYG_MACRO_START \
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cyg_uint32 syscfg; \
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HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
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syscfg |= KS32C_SYSCFG_CE; \
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HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); \
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CYG_MACRO_END
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// Disable the cache
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#define HAL_UCACHE_DISABLE() \
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CYG_MACRO_START \
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cyg_uint32 syscfg; \
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HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
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syscfg &= ~KS32C_SYSCFG_CE; \
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HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); \
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CYG_MACRO_END
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// Invalidate the entire cache
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#define HAL_UCACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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register cyg_uint32* tag = (cyg_uint32*)KS32C_CACHE_TAG_ADDR; \
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register int i; \
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for (i = 0; i < HAL_UCACHE_SETS/4; i++) { \
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*tag++ = 0; \
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*tag++ = 0; \
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*tag++ = 0; \
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*tag++ = 0; \
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} \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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// No action necessary. Cache is write-through.
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#define HAL_UCACHE_SYNC()
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// Query the state of the cache
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#define HAL_UCACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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cyg_uint32 syscfg; \
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HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
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(_state_) = (syscfg & KS32C_SYSCFG_CE) ? 1 : 0; \
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CYG_MACRO_END
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// Purge contents of cache
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#define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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// Set the cache refill burst size
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//#define HAL_UCACHE_BURST_SIZE(_size_)
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// Set the cache write mode
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//#define HAL_UCACHE_WRITE_MODE( _mode_ )
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//#define HAL_UCACHE_WRITETHRU_MODE 0
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//#define HAL_UCACHE_WRITEBACK_MODE 1
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// Load the contents of the given address range into the cache
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// and then lock the cache so that it stays there.
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//#define HAL_UCACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_UCACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_UCACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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//#define HAL_UCACHE_FLUSH( _base_ , _size_ )
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// Invalidate cache lines in the given range without writing to memory.
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//#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
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// Write dirty cache lines to memory for the given address range.
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//#define HAL_UCACHE_STORE( _base_ , _size_ )
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// Preread the given range into the cache with the intention of reading
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// from it later.
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//#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
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// Preread the given range into the cache with the intention of writing
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// to it later.
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//#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
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// Allocate and zero the cache lines associated with the given range.
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//#define HAL_UCACHE_ZERO( _base_ , _size_ )
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Data and instruction cache macros map onto the both-cache macros
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//-----------------------------------------------------------------------------
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// Global control of data cache
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#define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
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#define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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#define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
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#define HAL_DCACHE_SETS HAL_UCACHE_SETS
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
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// Disable the data cache
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#define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
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// Invalidate the entire cache
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#define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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// Synchronize the contents of the cache with memory.
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#define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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//#define HAL_DCACHE_WRITETHRU_MODE 0
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//#define HAL_DCACHE_WRITEBACK_MODE 1
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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//#define HAL_DCACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_DCACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_DCACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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// Invalidate cache lines in the given range without writing to memory.
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//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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// Write dirty cache lines to memory for the given address range.
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//#define HAL_DCACHE_STORE( _base_ , _size_ )
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// Preread the given range into the cache with the intention of reading
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// from it later.
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//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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// Preread the given range into the cache with the intention of writing
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// to it later.
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//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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// Allocate and zero the cache lines associated with the given range.
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//#define HAL_DCACHE_ZERO( _base_ , _size_ )
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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#define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
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#define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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#define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
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#define HAL_ICACHE_SETS HAL_UCACHE_SETS
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// Enable the instruction cache
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#define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
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// Disable the instruction cache
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#define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
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// Invalidate the entire cache
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#define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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// Synchronize the contents of the cache with memory.
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#define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
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// Query the state of the instruction cache
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#define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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// Set the instruction cache refill burst size
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//#define HAL_ICACHE_BURST_SIZE(_size_)
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// Load the contents of the given address range into the instruction cache
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// and then lock the cache so that it stays there.
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//#define HAL_ICACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_ICACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_ICACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Instruction cache line control
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// Invalidate cache lines in the given range without writing to memory.
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//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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#endif // ifndef CYGONCE_HAL_CACHE_H
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// End of hal_cache.h
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