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skrzyp |
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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#define CYGONCE_HAL_PLATFORM_SETUP_H
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//==========================================================================
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//
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// hal_platform_setup.h
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//
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//
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors: gthomas, jskov
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// Grant Edwards <grante@visi.com>
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// Date: 2001-07-31
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// Purpose:
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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// does normal DRAM setup, which doesn't fail?!?!
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#include <cyg/hal/plf_io.h>
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#define CYGHWR_LED_MACRO \
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ldr r0,=KS32C_IOPDATA ;\
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mov r1, #((255 & (~(\x)))) ;\
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str r1, [r0] ;
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#if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096
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// Override default to a more sensible value
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#undef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
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#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
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#endif
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// Use relative branch since we are going to switch the address space
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// around.
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#define CYGSEM_HAL_ROM_RESET_USES_JUMP
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#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
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#define PLATFORM_SETUP1 \
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ldr r1,=KS32C_IOPMOD ;\
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ldr r2,=0xff /* set led display to output */ ;\
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str r2,[r1,#0x00] ;\
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LED 0xaa ;\
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;\
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/* Normal DRAM mode */ ;\
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ldr r3, =0x03ffff90 /* cache+wb disabled, regs @ 0x03ff0000 */;\
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ldr r0, =KS32C_SYSCFG ;\
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str r3,[r0] ;\
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ldr lr,=10f ;\
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1: mov r1,pc ;\
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sub r1,r1,#8 ;\
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ldr r0,=1b ;\
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sub r1,r1,r0 ;\
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ldr r0,=30f ;\
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add r0,r0,r1 ;\
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ldmia r0,{r1-r12} ;\
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ldr r0,=KS32C_EXTDBWTH ;\
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stmia r0,{r1-r12} ;\
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mov pc,lr ;\
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10: LED 0x80 ;\
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\
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/* Check that it worked, otherwise try Sync DRAM setup */ ;\
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ldr r1,=0x00000000 ;\
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str r1,[r1] ;\
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ldr r2,[r1] ;\
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cmp r2,r1 ;\
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beq 99f ;\
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\
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/* Sync DRAM mode */ ;\
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LED 0x81 ;\
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ldr r3, =0x83ffff90 /* sdram c+wb disabled, regs @ 0x03ff0000 */;\
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ldr r0, =KS32C_SYSCFG ;\
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str r3,[r0] ;\
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ldr lr,=99f ;\
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1: mov r1,pc ;\
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sub r1,r1,#8 ;\
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ldr r0,=1b ;\
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sub r1,r1,r0 ;\
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ldr r0,=40f ;\
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add r0,r0,r1 ;\
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ldmia r0,{r1-r12} ;\
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ldr r0,=KS32C_EXTDBWTH ;\
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stmia r0,{r1-r12} ;\
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mov pc,lr ;\
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;\
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/* The below are set with a store-multiple instruction */ ;\
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;\
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/* Normal DRAM setup */ ;\
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/* Flash is 16 bit, everything else 32 bit */ ;\
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/* .long KS32C_EXTDBWTH */ ;\
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30: .long ( (KS32C_EXTDBWTH_16BIT<<KS32C_EXTDBWTH_DSR0_shift) \
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|(KS32C_EXTDBWTH_16BIT<<KS32C_EXTDBWTH_DSR1_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR2_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR3_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR4_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR5_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD0_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD1_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD2_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD3_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX0_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX1_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX2_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX3_shift) ) ;\
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/* Flash at 0x01800000-0x01880000, 5 cycles, 7 cycles */ ;\
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/* .long KS32C_ROMCON0 */ ;\
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.long ( (KS32C_ROMCON_PMC_ROM) \
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|(KS32C_ROMCON_TPA_5C) \
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|(KS32C_ROMCON_TACC_7C) \
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|((0x01800000 >> 16) << KS32C_ROMCON_BASE_shift) \
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|((0x01880000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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/* .long KS32C_ROMCON1 */ ;\
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.long ( (KS32C_ROMCON_PMC_ROM) \
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|(KS32C_ROMCON_TPA_5C) \
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|(KS32C_ROMCON_TACC_5C) \
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|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
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|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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/* .long KS32C_ROMCON2 */ ;\
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.long ( (KS32C_ROMCON_PMC_ROM) \
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|(KS32C_ROMCON_TPA_5C) \
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|(KS32C_ROMCON_TACC_5C) \
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|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
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|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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/* .long KS32C_ROMCON3 */ ;\
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.long ( (KS32C_ROMCON_PMC_ROM) \
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|(KS32C_ROMCON_TPA_5C) \
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|(KS32C_ROMCON_TACC_3C) \
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|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
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|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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/* .long KS32C_ROMCON4 */ ;\
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.long ( (KS32C_ROMCON_PMC_ROM) \
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|(KS32C_ROMCON_TPA_5C) \
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|(KS32C_ROMCON_TACC_5C) \
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|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
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|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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/* .long KS32C_ROMCON5 */ ;\
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.long ( (KS32C_ROMCON_PMC_ROM) \
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|(KS32C_ROMCON_TPA_5C) \
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|(KS32C_ROMCON_TACC_5C) \
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|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
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|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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/* .long KS32C_DRAMCON0 */ ;\
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.long ( (KS32C_DRAMCON_RESERVED) \
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|(KS32C_DRAMCON_CAN_10) \
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|(KS32C_DRAMCON_TRP_3C) \
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|(KS32C_DRAMCON_TRC_1C) \
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|(KS32C_DRAMCON_TCP_1C) \
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|(KS32C_DRAMCON_TCS_2C) \
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|(KS32C_DRAMCON_EDO) \
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|((0x00000000 >> 16) << KS32C_DRAMCON_BASE_shift) \
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|((0x00400000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
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/* .long KS32C_DRAMCON1 */ ;\
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.long ( (KS32C_DRAMCON_RESERVED) \
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|(KS32C_DRAMCON_CAN_10) \
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|(KS32C_DRAMCON_TRP_1C) \
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|(KS32C_DRAMCON_TRC_1C) \
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|(KS32C_DRAMCON_TCP_1C) \
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|(KS32C_DRAMCON_TCS_2C) \
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|(KS32C_DRAMCON_EDO) \
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|((0x00400000 >> 16) << KS32C_DRAMCON_BASE_shift) \
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|((0x00800000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
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/* .long KS32C_DRAMCON2 */ ;\
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.long ( (KS32C_DRAMCON_RESERVED) \
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|(KS32C_DRAMCON_CAN_10) \
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|(KS32C_DRAMCON_TRP_1C) \
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|(KS32C_DRAMCON_TRC_1C) \
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|(KS32C_DRAMCON_TCP_1C) \
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|(KS32C_DRAMCON_TCS_2C) \
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|((0x00800000 >> 16) << KS32C_DRAMCON_BASE_shift) \
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|((0x00c00000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
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/* .long KS32C_DRAMCON3 */ ;\
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.long ( (KS32C_DRAMCON_RESERVED) \
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|(KS32C_DRAMCON_CAN_10) \
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|(KS32C_DRAMCON_TRP_1C) \
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|(KS32C_DRAMCON_TRC_1C) \
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|(KS32C_DRAMCON_TCP_1C) \
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|(KS32C_DRAMCON_TCS_2C) \
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|((0x00c00000 >> 16) << KS32C_DRAMCON_BASE_shift) \
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|((0x01000000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
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/* .long KS32C_REFEXTCON */ ;\
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.long (((2048+1-(16*CYGNUM_HAL_CPUCLOCK/1000000)) << KS32C_REFEXTCON_RCV_shift) \
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|(KS32C_REFEXTCON_TCSR_1C) \
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|(KS32C_REFEXTCON_TCHR_1C) \
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|(KS32C_REFEXTCON_REN) \
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|(KS32C_REFEXTCON_VSF) \
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|(KS32C_REFEXTCON_BASE)) ;\
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;\
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/* Sync DRAM setup */ ;\
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/* Flash is 16 bit, everything else 32 bit */ ;\
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/* .long KS32C_EXTDBWTH */ ;\
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40: .long ( (KS32C_EXTDBWTH_16BIT<<KS32C_EXTDBWTH_DSR0_shift) \
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| 228 |
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|(KS32C_EXTDBWTH_16BIT<<KS32C_EXTDBWTH_DSR1_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR2_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR3_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR4_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR5_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD0_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD1_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD2_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD3_shift) \
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| 237 |
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX0_shift) \
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| 238 |
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX1_shift) \
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX2_shift) \
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| 240 |
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|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX3_shift) ) ;\
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/* Flash at 0x01800000-0x01880000, 5 cycles, 7 cycles */ ;\
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| 242 |
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/* .long KS32C_ROMCON0 */ ;\
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| 243 |
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.long ( (KS32C_ROMCON_PMC_ROM) \
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| 244 |
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|(KS32C_ROMCON_TPA_5C) \
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| 245 |
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|(KS32C_ROMCON_TACC_7C) \
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| 246 |
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|((0x01800000 >> 16) << KS32C_ROMCON_BASE_shift) \
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| 247 |
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|((0x01880000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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| 248 |
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/* .long KS32C_ROMCON1 */ ;\
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| 249 |
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.long ( (KS32C_ROMCON_PMC_ROM) \
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| 250 |
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|(KS32C_ROMCON_TPA_5C) \
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| 251 |
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|(KS32C_ROMCON_TACC_5C) \
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| 252 |
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|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
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| 253 |
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|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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| 254 |
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/* .long KS32C_ROMCON2 */ ;\
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| 255 |
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.long ( (KS32C_ROMCON_PMC_ROM) \
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| 256 |
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|(KS32C_ROMCON_TPA_5C) \
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| 257 |
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|(KS32C_ROMCON_TACC_5C) \
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| 258 |
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|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
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| 259 |
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|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
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| 260 |
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/* .long KS32C_ROMCON3 */ ;\
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| 261 |
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.long ( (KS32C_ROMCON_PMC_ROM) \
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| 262 |
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|(KS32C_ROMCON_TPA_5C) \
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| 263 |
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|(KS32C_ROMCON_TACC_5C) \
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| 264 |
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|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|
| 265 |
|
|
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
|
| 266 |
|
|
/* .long KS32C_ROMCON4 */ ;\
|
| 267 |
|
|
.long ( (KS32C_ROMCON_PMC_ROM) \
|
| 268 |
|
|
|(KS32C_ROMCON_TPA_5C) \
|
| 269 |
|
|
|(KS32C_ROMCON_TACC_5C) \
|
| 270 |
|
|
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|
| 271 |
|
|
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
|
| 272 |
|
|
/* .long KS32C_ROMCON5 */ ;\
|
| 273 |
|
|
.long ( (KS32C_ROMCON_PMC_ROM) \
|
| 274 |
|
|
|(KS32C_ROMCON_TPA_5C) \
|
| 275 |
|
|
|(KS32C_ROMCON_TACC_5C) \
|
| 276 |
|
|
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|
| 277 |
|
|
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
|
| 278 |
|
|
/* .long KS32C_DRAMCON0 */ ;\
|
| 279 |
|
|
.long ( (KS32C_DRAMCON_RESERVED) \
|
| 280 |
|
|
|(KS32C_DRAMCON_CAN_8) \
|
| 281 |
|
|
|(KS32C_DRAMCON_TRP_4C) \
|
| 282 |
|
|
|(KS32C_DRAMCON_TRC_2C) \
|
| 283 |
|
|
|((0x00000000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|
| 284 |
|
|
|((0x00400000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
|
| 285 |
|
|
/* .long KS32C_DRAMCON1 */ ;\
|
| 286 |
|
|
.long ( (KS32C_DRAMCON_RESERVED) \
|
| 287 |
|
|
|(KS32C_DRAMCON_CAN_8) \
|
| 288 |
|
|
|(KS32C_DRAMCON_TRP_2C) \
|
| 289 |
|
|
|(KS32C_DRAMCON_TRC_2C) \
|
| 290 |
|
|
|((0x00400000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|
| 291 |
|
|
|((0x00800000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
|
| 292 |
|
|
/* .long KS32C_DRAMCON2 */ ;\
|
| 293 |
|
|
.long ( (KS32C_DRAMCON_RESERVED) \
|
| 294 |
|
|
|(KS32C_DRAMCON_CAN_8) \
|
| 295 |
|
|
|(KS32C_DRAMCON_TRP_2C) \
|
| 296 |
|
|
|(KS32C_DRAMCON_TRC_2C) \
|
| 297 |
|
|
|((0x00800000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|
| 298 |
|
|
|((0x00c00000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
|
| 299 |
|
|
/* .long KS32C_DRAMCON3 */ ;\
|
| 300 |
|
|
.long ( (KS32C_DRAMCON_RESERVED) \
|
| 301 |
|
|
|(KS32C_DRAMCON_CAN_8) \
|
| 302 |
|
|
|(KS32C_DRAMCON_TRP_2C) \
|
| 303 |
|
|
|(KS32C_DRAMCON_TRC_2C) \
|
| 304 |
|
|
|((0x00c00000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|
| 305 |
|
|
|((0x01000000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
|
| 306 |
|
|
/* .long KS32C_REFEXTCON */ ;\
|
| 307 |
|
|
.long (((2048+1-(8*CYGNUM_HAL_CPUCLOCK/1000000)) << KS32C_REFEXTCON_RCV_shift) \
|
| 308 |
|
|
|(KS32C_REFEXTCON_TRC_4C) \
|
| 309 |
|
|
|(KS32C_REFEXTCON_REN) \
|
| 310 |
|
|
|(KS32C_REFEXTCON_VSF) \
|
| 311 |
|
|
|(KS32C_REFEXTCON_BASE)) ;\
|
| 312 |
|
|
99: LED 0x82 ;\
|
| 313 |
|
|
ldr r3,=0x00000000 ;\
|
| 314 |
|
|
str r3,[r3] ;\
|
| 315 |
|
|
ldr r4,[r3] ;\
|
| 316 |
|
|
cmp r4,r3 ;\
|
| 317 |
|
|
beq 15f ;\
|
| 318 |
|
|
11: LED 0x83 ;\
|
| 319 |
|
|
b 11b ;\
|
| 320 |
|
|
15: LED 0x84
|
| 321 |
|
|
#else
|
| 322 |
|
|
#define PLATFORM_SETUP1
|
| 323 |
|
|
#endif
|
| 324 |
|
|
|
| 325 |
|
|
//-----------------------------------------------------------------------------
|
| 326 |
|
|
// end of hal_platform_setup.h
|
| 327 |
|
|
#endif // CYGONCE_HAL_PLATFORM_SETUP_H
|
