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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [arm/] [xscale/] [cores/] [current/] [include/] [hal_xscale.h] - Blame information for rev 786

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1 786 skrzyp
/*=============================================================================
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//
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//      hal_xscale.h
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//
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//      XScale Core I/O module support.
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    msalter
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// Contributors: msalter
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// Date:         2002-10-18
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// Purpose:
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// Description:  XScale core I/O modules support.
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// Usage:        #include <cyg/hal/hal_xscale.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#ifndef CYGONCE_HAL_ARM_XSCALE_HAL_XSCALE_H
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#define CYGONCE_HAL_ARM_XSCALE_HAL_XSCALE_H
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#include <pkgconf/system.h>
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#include <pkgconf/hal_arm_xscale_core.h>
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#ifdef __ASSEMBLER__
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        // Useful CPU macros
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        // Delay a bit
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        .macro DELAY_FOR cycles, reg0
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        ldr     \reg0, =\cycles
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        subs    \reg0, \reg0, #1
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        subne   pc,  pc, #0xc
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        .endm
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        // wait for coprocessor write complete
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        .macro CPWAIT reg
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        mrc  p15,0,\reg,c2,c0,0
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        mov  \reg,\reg
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        sub  pc,pc,#4
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        .endm
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        // Enable the BTB
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        .macro BTB_INIT reg
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        mrc     p15, 0, \reg, c1, c0, 0
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#ifdef CYGSEM_HAL_ARM_XSCALE_BTB
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        orr     \reg, \reg, #MMU_Control_BTB
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#else
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        bic     \reg, \reg, #MMU_Control_BTB
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#endif
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        mcr     p15, 0, \reg, c1, c0, 0
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        CPWAIT  \reg
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        .endm
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#else
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static inline void CPWAIT(void) {
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    cyg_uint32 tmp;
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    asm volatile ("mrc  p15,0,%0,c2,c0,0\n"
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                  "mov  %0,%0\n"
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                  "sub  pc,pc,#4" : "=r" (tmp));
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}
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#endif
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#define __CYGARC_GET_CTLREG \
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              "   mrc p15,0,r0,c1,c0,0\n"
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#define __CYGARC_CLR_MMU_BITS \
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              "   bic r0,r0,#0x05\n"
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#ifdef CYGHWR_HAL_ARM_BIGENDIAN
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#define __CYGARC_CLR_MMU_BITS_X \
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              "   bic r0,r0,#0x85\n"
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#else
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#define __CYGARC_CLR_MMU_BITS_X \
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              "   bic r0,r0,#0x05\n"         \
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              "   orr r0,r0,#0x80\n"
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#endif
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#define __CYGARC_SET_CTLREG(__paddr__) \
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              "   b 99f\n"                   \
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              "   .p2align 5\n"              \
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              "99:\n"                        \
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              "   mcr p15,0,r0,c1,c0,0\n"    \
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              "   mrc p15,0,r0,c2,c0,0\n"    \
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              "   mov r0,r0\n"               \
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              "   sub pc,pc,#4\n"            \
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              "   mov pc," #__paddr__ "\n"
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// Override the default MMU off code. This is intended
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// to be included in an inline asm statement.
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#define CYGARC_HAL_MMU_OFF(__paddr__)        \
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    __CYGARC_GET_CTLREG                      \
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    __CYGARC_CLR_MMU_BITS                    \
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    __CYGARC_SET_CTLREG(__paddr__)
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#define CYGARC_HAL_MMU_OFF_X(__paddr__)      \
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    __CYGARC_GET_CTLREG                      \
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    __CYGARC_CLR_MMU_BITS_X                  \
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    __CYGARC_SET_CTLREG(__paddr__)
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#ifdef __ASSEMBLER__
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#define REG8(a,b)  (b)
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#define REG16(a,b) (b)
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#define REG32(a,b) (b)
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#else /* __ASSEMBLER__ */
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#define REG8(a,b)  ((volatile unsigned char *)((a)+(b)))
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#define REG16(a,b) ((volatile unsigned short *)((a)+(b)))
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#define REG32(a,b) ((volatile unsigned int *)((a)+(b)))
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extern void hal_xscale_core_init(void);
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#endif /* __ASSEMBLER__ */
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//--------------------------------------------------------------
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#endif // CYGONCE_HAL_ARM_XSCALE_HAL_XSCALE_H
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// EOF hal_xscale.h

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