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#ifndef CYGONCE_HAL_ARM_XSCALE_GRG_GRG_H
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#define CYGONCE_HAL_ARM_XSCALE_GRG_GRG_H
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/*=============================================================================
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//
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// grg.h
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//
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// Platform specific support (register layout, etc)
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): msalter
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// Contributors: msalter
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// Date: 2003-02-05
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// Purpose: Intel GRG specific support routines
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// Description:
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// Usage: #include <cyg/hal/grg.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/system.h>
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#include CYGHWR_MEMORY_LAYOUT_H
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#include <pkgconf/hal_arm_xscale_grg.h>
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#include <cyg/hal/hal_ixp425.h>
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// These must match setup in the page table in hal_platform_extras.h
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#define SDRAM_PHYS_BASE 0x00000000
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#define SDRAM_BASE 0x00000000
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#define SDRAM_ALIAS_BASE 0x10000000
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#define SDRAM_UNCACHED_BASE 0x20000000
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#define SDRAM_DC_BASE 0x30000000
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#define SDRAM_SIZE 0x02000000 // 32MB
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#define IXDP_FLASH_BASE 0x50000000
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#define IXDP_FLASH_SIZE 0x01000000
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#define IXDP_FLASH_DC_BASE 0xA0000000
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// CS0 (flash optimum timing)
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#define IXP425_EXP_CS0_INIT \
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(EXP_ADDR_T(3) | EXP_SETUP_T(3) | EXP_STROBE_T(15) | EXP_HOLD_T(3) | \
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EXP_RECOVERY_T(15) | EXP_SZ_16M | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN)
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#define IXP425_SDRAM_CONFIG_INIT (SDRAM_CONFIG_CAS_3 | SDRAM_CONFIG_2x8Mx16)
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#define IXP425_SDRAM_REFRESH_CNT 0x81A
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#define IXP425_SDRAM_SET_MODE_CMD SDRAM_IR_MODE_SET_CAS3
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// ------------------------------------------------------------------------
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// GPIO lines
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//
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#define GPIO_PWR_FAIL_IRQ_N 0
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#define GPIO_DSL_IRQ_N 1
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#define GPIO_SLIC_A_IRQ_N 2
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#define GPIO_SLIC_B_IRQ_N 3
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#define GPIO_DSP_IRQ_N 4
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#define GPIO_IDE_IRQ_N 5
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// GPIO lines used for SPI bus
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#define GPIO_SPI_CS1_N 7
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#define GPIO_SPI_CS0_N 8
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#define GPIO_SPI_SCK 9
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#define GPIO_SPI_SDI 10
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#define GPIO_SPI_SDO 13
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#define GPIO_IO_RESET_N 12
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// ------------------------------------------------------------------------
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// No Hex Display
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//
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#ifdef __ASSEMBLER__
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// Display hex digits in 'value' not masked by 'mask'.
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.macro DISPLAY value, reg0, reg1
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.endm
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#else
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static inline void HEX_DISPLAY(int value)
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{
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}
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#endif // __ASSEMBLER__
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// ------------------------------------------------------------------------
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#endif // CYGONCE_HAL_ARM_XSCALE_GRG_GRG_H
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// EOF grg.h
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