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#ifndef CYGONCE_HAL_PLATFORM_EXTRAS_H
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#define CYGONCE_HAL_PLATFORM_EXTRAS_H
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/*=============================================================================
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//
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// hal_platform_extras.h
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//
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// Platform specific MMU table.
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): msalter
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// Contributors: msalter
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// Date: 2001-12-03
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// Purpose: Intel XScale IQ80321 platform specific mmu table
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// Description:
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// Usage: #include <cyg/hal/hal_platform_extras.h>
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// Only used by "vectors.S"
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#if defined(CYG_HAL_STARTUP_ROM)
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.section .mmu_tables, "a"
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#ifdef CYG_HAL_MEMORY_MAP_NORMAL
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mmu_table:
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// This page table sets up the preferred mapping:
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//
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// Virtual Address Physical Address Size (MB) Description
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// --------------- ---------------- --------- -----------
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// 0x00000000 0xA0000000 512 DRAM
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// 0x20000000 0x00000000 2048 ATU Outbound Direct
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// 0xA0000000 0x80000000 257 ATU Outbound Xlate
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// 0xB0100000 0x90100000 255 Unused
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// 0xC0000000 0xA0000000 512 Uncached DRAM alias
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// 0xE0000000 0xE0000000 1 Cache Flush
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// 0xE0100000 0xE0100000 255 Unused
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// 0xF0000000 0xF0000000 8 FLASH (PBIU CS0)
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// 0xF0800000 0xF0800000 224 Unused
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// 0xFE800000 0xFE800000 1 PBIU CS1-CS5
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// 0xFE900000 0xFE900000 22 Unused
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// 0xFFF00000 0xFFF00000 1 Verde PMMR
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// 512MB ECC DRAM
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// In flash based table: X=1, C=1, B=1, ECC
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.set __base,0xA00
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.rept 0x200 - 0x000
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FL_SECTION_ENTRY __base,1,3,1,0,1,1
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.set __base,__base+1
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.endr
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// 2048MB ATU Outbound direct
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// X=0, Non-cacheable, Non-bufferable
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.set __base,0x000
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.rept 0xA00 - 0x200
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FL_SECTION_ENTRY __base,0,3,0,0,0,0
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.set __base,__base+1
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.endr
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// 257MB ATU Outbound translation
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// X=0, Non-cacheable, Non-bufferable
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.rept 0xB01 - 0xA00
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FL_SECTION_ENTRY __base,0,3,0,0,0,0
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.set __base,__base+1
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.endr
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// Nothing here
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.rept 0xC00 - 0xB01
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FL_SECTION_ENTRY __base,0,0,0,0,0,0
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.set __base,__base+1
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.endr
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// Uncached/unbuffered alias for 512MB ECC DRAM
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.set __base,0xA00
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.rept 0xE00 - 0xC00
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FL_SECTION_ENTRY __base,0,3,1,0,0,0
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.set __base,__base+1
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.endr
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// Cache flush region.
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// Don't need physical memory, just a cached area.
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.set __base,0xE00
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.rept 0xE01 - 0xE00
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FL_SECTION_ENTRY __base,1,3,0,0,1,1
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.set __base,__base+1
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.endr
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// Nothing here
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.rept 0xF00 - 0xE01
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FL_SECTION_ENTRY __base,0,0,0,0,0,0
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.set __base,__base+1
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.endr
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// 8MB of FLASH
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// X=0, Cacheable, Non-bufferable
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.rept 0xF08 - 0xF00
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FL_SECTION_ENTRY __base,0,3,0,0,1,0
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.set __base,__base+1
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.endr
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// Nothing here
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.rept 0xFE8 - 0xF08
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FL_SECTION_ENTRY __base,0,0,0,0,0,0
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.set __base,__base+1
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.endr
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// PBIU CS1 - CS5
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// X=0, Non-cacheable, Non-bufferable
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.rept 0xFE9 - 0xFE8
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FL_SECTION_ENTRY __base,0,3,0,0,0,0
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.set __base,__base+1
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.endr
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// Nothing here
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.rept 0xFFF - 0xFE9
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FL_SECTION_ENTRY __base,0,0,0,0,0,0
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.set __base,__base+1
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.endr
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// Verde PMMR
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// X=0, Non-cacheable, Non-bufferable
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.rept 0x1000 - 0xFFF
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FL_SECTION_ENTRY __base,0,3,0,0,0,0
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.set __base,__base+1
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.endr
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#else /* CYG_HAL_MEMORY_MAP_NORMAL */
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mmu_table:
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// This page table sets up an alternate mapping:
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//
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// Virtual Address Physical Address Size (MB) Description
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// --------------- ---------------- --------- -----------
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// 0x00000000 0xA0000000 1 DRAM
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// 0x00100000 0x00100000 2047 ATU Outbound Direct
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// 0x80000000 0x80000000 257 ATU Outbound Xlate
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// 0x90100000 0x90100000 255 Invalid
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// 0xA0000000 0xA0000000 512 DRAM
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// 0xC0000000 0xA0000000 512 Uncached DRAM alias
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// 0xE0000000 0xE0000000 1 Cache Flush
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// 0xE0100000 0xE0100000 255 Invalid
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// 0xF0000000 0xF0000000 8 FLASH (PBIU CS0)
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// 0xF0800000 0xF0800000 224 Invalid
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// 0xFE800000 0xFE800000 1 PBIU CS1-CS5
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// 0xFE900000 0xFE900000 22 Invalid
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// 0xFFF00000 0xFFF00000 1 Verde PMMR
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// 1MB ECC DRAM
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// This is a duplicate mapping of the first MB of RAM. It is mapped
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// here for CPU exception vectors.
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.set __base,0xA00
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.rept 0x001 - 0x000
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FL_SECTION_ENTRY __base,1,3,1,0,1,1
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.set __base,__base+1
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.endr
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.set __base,0x001
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// 2047MB ATU Outbound direct
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// X=0, Non-cacheable, Non-bufferable
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.rept 0x800 - 0x001
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FL_SECTION_ENTRY __base,0,3,0,0,0,0
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.set __base,__base+1
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.endr
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// 257MB ATU Outbound translation
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// X=0, Non-cacheable, Non-bufferable
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.rept 0x901 - 0x800
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FL_SECTION_ENTRY __base,0,3,0,0,0,0
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.set __base,__base+1
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.endr
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// Nothing here. Invalid.
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.rept 0xA00 - 0x901
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FL_SECTION_ENTRY __base,0,0,0,0,0,0
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.set __base,__base+1
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.endr
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// 512MB ECC DRAM
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// X=1, C=1, B=1, ECC
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.rept 0xC00 - 0xA00
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FL_SECTION_ENTRY __base,1,3,1,0,1,1
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.set __base,__base+1
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.endr
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// Uncached/unbuffered alias for 512MB ECC DRAM
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.set __base,0xA00
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.rept 0xE00 - 0xC00
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FL_SECTION_ENTRY __base,0,3,1,0,0,0
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.set __base,__base+1
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.endr
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// Cache flush region.
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// Don't need physical memory, just a cached area.
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.set __base,0xE00
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.rept 0xE01 - 0xE00
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FL_SECTION_ENTRY __base,1,3,0,0,1,1
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.set __base,__base+1
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.endr
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// Nothing here
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.rept 0xF00 - 0xE01
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FL_SECTION_ENTRY __base,0,0,0,0,0,0
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.set __base,__base+1
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.endr
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// 8MB of FLASH
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// X=0, Cacheable, Non-bufferable
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.rept 0xF08 - 0xF00
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FL_SECTION_ENTRY __base,0,3,0,0,1,0
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.set __base,__base+1
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.endr
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// Nothing here
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.rept 0xFE8 - 0xF08
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FL_SECTION_ENTRY __base,0,0,0,0,0,0
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.set __base,__base+1
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.endr
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// PBIU CS1 - CS5
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// X=0, Non-cacheable, Non-bufferable
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.rept 0xFE9 - 0xFE8
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FL_SECTION_ENTRY __base,0,3,0,0,0,0
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.set __base,__base+1
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.endr
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// Nothing here
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.rept 0xFFF - 0xFE9
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FL_SECTION_ENTRY __base,0,0,0,0,0,0
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.set __base,__base+1
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.endr
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// Verde PMMR
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// X=0, Non-cacheable, Non-bufferable
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.rept 0x1000 - 0xFFF
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FL_SECTION_ENTRY __base,0,3,0,0,0,0
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.set __base,__base+1
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.endr
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#endif /* CYG_HAL_MEMORY_MAP_NORMAL */
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#endif /* CYG_HAL_STARTUP_ROM */
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/*---------------------------------------------------------------------------*/
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/* end of hal_platform_setup.h */
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#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
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