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skrzyp |
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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#define CYGONCE_HAL_PLATFORM_SETUP_H
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/*=============================================================================
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//
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// hal_platform_setup.h
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//
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// Platform specific support for HAL (assembly code)
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): msalter
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// Contributors: msalter
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// Date: 2002-12-10
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// Purpose: Intel XScale IXPD specific support routines
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// Description:
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// Usage: #include <cyg/hal/hal_platform_setup.h>
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// Only used by "vectors.S"
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/system.h> // System-wide configuration info
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#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
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#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
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#include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions
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#include <cyg/hal/hal_mmu.h> // MMU definitions
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#include <cyg/hal/hal_mm.h> // more MMU definitions
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#include <cyg/hal/ixdp425.h> // Platform specific hardware definitions
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// ------------------------------------------------------------------------
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// Convenience macros for setting up page table
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//
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.macro IXP_MAP_SDRAM va, c, b, x, p
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XSCALE_MMU_SECTION SDRAM_PHYS_BASE>>20, \va>>20, SDRAM_SIZE>>20, \c, \b, 3, \x, \p
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.endm
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.macro IXP_MAP_EXP_V n, va, sz, c, b, x, p
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XSCALE_MMU_SECTION (0x500 + ((IXP425_EXP_CS_SIZE * \n) >> 20)), \va>>20, \sz>>20, \c, \b, 3, \x, \p
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.endm
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.macro IXP_MAP_EXP n, sz, c, b, x, p
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IXP_MAP_EXP_V \n, (0x50000000 + (IXP425_EXP_CS_SIZE * \n)), \sz, \c, \b, \x, \p
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.endm
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.macro IXP_MAP_IO addr, sz
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XSCALE_MMU_SECTION \addr>>20, \addr>>20, \sz>>20, 0, 0, 3, 0, 0
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.endm
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#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
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#define PLATFORM_SETUP1 _platform_setup1
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#define CYGHWR_HAL_ARM_HAS_MMU
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// ------------------------------------------------------------------------
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// Define macro used to diddle the LEDs during early initialization.
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// Can use r0+r1. Argument in \x.
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#define CYGHWR_LED_MACRO DISPLAY \x, r0, r1
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// Delay a bit
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.macro DELAY cycles, reg0
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ldr \reg0, =\cycles
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subs \reg0, \reg0, #1
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subne pc, pc, #0xc
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.endm
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// ------------------------------------------------------------------------
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// This macro represents the initial startup code for the platform
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.macro _platform_setup1
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#ifdef CYGHWR_HAL_ARM_BIGENDIAN
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// set big-endian
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x80
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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#endif
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ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
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msr cpsr, r0
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// invalidate I & D caches & BTB
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mcr p15, 0, r0, c7, c7, 0
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CPWAIT r0
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// invalidate I & Data TLB
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mcr p15, 0, r0, c8, c7, 0
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CPWAIT r0
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// drain write and fill buffers
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mcr p15, 0, r0, c7, c10, 4
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CPWAIT r0
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// disable write buffer coalescing
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #1
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mcr p15, 0, r0, c1, c0, 1
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CPWAIT r0
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// Setup chip selects
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ldr r1, =IXP425_EXP_CFG_BASE
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#ifdef IXP425_EXP_CS0_INIT
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ldr r0, =IXP425_EXP_CS0_INIT
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str r0, [r1, #IXP425_EXP_CS0]
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#endif
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#ifdef IXP425_EXP_CS1_INIT
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ldr r0, =IXP425_EXP_CS1_INIT
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str r0, [r1, #IXP425_EXP_CS1]
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#endif
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#ifdef IXP425_EXP_CS2_INIT
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ldr r0, =IXP425_EXP_CS2_INIT
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str r0, [r1, #IXP425_EXP_CS2]
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#endif
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#ifdef IXP425_EXP_CS3_INIT
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ldr r0, =IXP425_EXP_CS3_INIT
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str r0, [r1, #IXP425_EXP_CS3]
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#endif
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#ifdef IXP425_EXP_CS4_INIT
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ldr r0, =IXP425_EXP_CS4_INIT
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str r0, [r1, #IXP425_EXP_CS4]
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#endif
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#ifdef IXP425_EXP_CS5_INIT
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ldr r0, =IXP425_EXP_CS5_INIT
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str r0, [r1, #IXP425_EXP_CS5]
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#endif
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#ifdef IXP425_EXP_CS6_INIT
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ldr r0, =IXP425_EXP_CS6_INIT
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str r0, [r1, #IXP425_EXP_CS6]
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#endif
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#ifdef IXP425_EXP_CS7_INIT
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ldr r0, =IXP425_EXP_CS7_INIT
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str r0, [r1, #IXP425_EXP_CS7]
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#endif
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DISPLAY 0x1001, r7, r8
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// Enable the Icache
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #MMU_Control_I
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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DISPLAY 0x1002, r7, r8
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// Setup SDRAM controller
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ldr r0, =IXP425_SDRAM_CFG_BASE
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ldr r1, =IXP425_SDRAM_CONFIG_INIT
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str r1, [r0, #IXP425_SDRAM_CONFIG]
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// disable refresh cycles
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mov r1, #0
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str r1, [r0, #IXP425_SDRAM_REFRESH]
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// send nop command
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mov r1, #SDRAM_IR_NOP
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str r1, [r0, #IXP425_SDRAM_IR]
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DELAY 0x10000, r1
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// set SDRAM internal refresh val
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ldr r1, =IXP425_SDRAM_REFRESH_CNT
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str r1, [r0, #IXP425_SDRAM_REFRESH]
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DELAY 0x10000, r1
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// send precharge-all command to close all open banks
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mov r1, #SDRAM_IR_PRECHARGE
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str r1, [r0, #IXP425_SDRAM_IR]
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DELAY 0x10000, r1
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// provide 8 auto-refresh cycles
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mov r1, #SDRAM_IR_AUTO_REFRESH
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mov r2, #8
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1:
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str r1, [r0, #IXP425_SDRAM_IR]
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DELAY 0x800, r3
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subs r2, r2, #1
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bne 1b
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// set mode register in sdram
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mov r1, #IXP425_SDRAM_SET_MODE_CMD
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str r1, [r0, #IXP425_SDRAM_IR]
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DELAY 0x10000, r1
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// start normal operation
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mov r1, #SDRAM_IR_NORMAL
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str r1, [r0, #IXP425_SDRAM_IR]
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DELAY 0x10000, r1
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DISPLAY 0x1003, r7, r8
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// Enable byte swapping control via page table P bit.
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ldr r2, =IXP425_EXP_CFG_BASE
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ldr r1, [r2, #IXP425_EXP_CNFG1]
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orr r1, r1, #EXP_CNFG1_BYTE_SWAP_EN
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str r1, [r2, #IXP425_EXP_CNFG1]
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// value to load into pc to jump to real runtime address
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ldr r0, =1f
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#if defined(CYG_HAL_STARTUP_ROMRAM)
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// R0 holds a RAM address for ROMRAM startup,
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// so convert to a flash address.
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orr r0, r0, #IXDP_FLASH_BASE
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#endif
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// Setup EXP_CNFG0 value to switch EXP bus out of low memory
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ldr r2, =IXP425_EXP_CFG_BASE
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ldr r1, [r2, #IXP425_EXP_CNFG0]
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bic r1, r1, #EXP_CNFG0_MEM_MAP
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ldr r3, =0xFFFF
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ldr r4, =IXDP425_LED_DATA
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b icache_boundary
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.p2align 5
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icache_boundary:
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// Here is where we switch from boot address (0x000000000) to the
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// actual flash runtime address. We align to cache boundary so we
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// execute from cache during the switchover. Cachelines are 8 words.
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str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch
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nop
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nop
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nop
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nop
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mov pc, r0
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strh r3, [r4] // We should never reach this point. If we do,
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// display FFFF and loop forever.
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0: b 0b
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1:
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DISPLAY 0x1004, r7, r8
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#if defined(CYG_HAL_STARTUP_ROMRAM)
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mov r0, #IXDP_FLASH_BASE
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mov r1, #SDRAM_PHYS_BASE
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ldr r2, =__ram_data_end
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20: ldr r3, [r0],#4
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str r3, [r1],#4
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cmp r1, r2
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bne 20b
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// start executing from RAM
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ldr r0, =30f
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mov pc, r0
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30:
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#endif
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// Build mmu tables into RAM so page table walks by the cpu
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// don't interfere with FLASH programming.
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mov r1, #SDRAM_PHYS_BASE
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orr r1, r1, #0x4000 // RAM tables
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add r2, r1, #0x4000 // End of tables
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| 288 |
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// First clear table
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mov r0, #0
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1:
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str r0, [r1], #4
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cmp r1, r2
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bne 1b
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// Build section mappings
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IXP_MAP_SDRAM SDRAM_BASE, 1, 0, 0, 0 // Cached SDRAM
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IXP_MAP_SDRAM SDRAM_ALIAS_BASE, 1, 0, 0, 0 // Cached SDRAM alias
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IXP_MAP_SDRAM SDRAM_UNCACHED_BASE, 0, 0, 0, 0 // Uncached SDRAM
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IXP_MAP_SDRAM SDRAM_DC_BASE, 1, 0, 0, 1 // Cached data coherent SDRAM
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IXP_MAP_EXP 0, IXDP_FLASH_SIZE, 1, 0, 0, 0 // Flash
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IXP_MAP_EXP 2, IXDP425_LED_SIZE, 0, 0, 0, 0 // LED
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IXP_MAP_EXP 4, (1 << 20), 0, 0, 0, 0 // NPE use
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IXP_MAP_EXP 5, (1 << 20), 0, 0, 0, 0 // NPE use
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IXP_MAP_EXP_V 0, IXDP_FLASH_DC_BASE, IXDP_FLASH_SIZE, 1, 0, 0, 1 // data coherent flash
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IXP_MAP_EXP_V 0, IXDP_FLASH_UNCACHED_BASE, IXDP_FLASH_SIZE, 0, 0, 0, 0 // uncached flash
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IXP_MAP_IO IXP425_PCI_WINDOW_BASE, IXP425_PCI_WINDOW_SIZE
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IXP_MAP_IO IXP425_QMGR_BASE, IXP425_QMGR_SIZE
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IXP_MAP_IO IXP425_PCI_CFG_BASE, IXP425_PCI_CFG_SIZE
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IXP_MAP_IO IXP425_EXP_CFG_BASE, IXP425_EXP_CFG_SIZE
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IXP_MAP_IO IXP425_MISC_CFG_BASE, IXP425_MISC_CFG_SIZE
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IXP_MAP_IO IXP425_SDRAM_CFG_BASE, IXP425_SDRAM_CFG_SIZE
|
| 315 |
|
|
|
| 316 |
|
|
DISPLAY 0x1005, r7, r8
|
| 317 |
|
|
|
| 318 |
|
|
mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
|
| 319 |
|
|
CPWAIT r0
|
| 320 |
|
|
|
| 321 |
|
|
// Set the TTB register to DRAM mmu_table
|
| 322 |
|
|
ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables
|
| 323 |
|
|
mcr p15, 0, r0, c2, c0, 0 // load page table pointer
|
| 324 |
|
|
CPWAIT r0
|
| 325 |
|
|
|
| 326 |
|
|
// enable permission checks in all domains
|
| 327 |
|
|
ldr r0, =0x55555555
|
| 328 |
|
|
mcr p15, 0, r0, c3, c0, 0
|
| 329 |
|
|
CPWAIT r0
|
| 330 |
|
|
|
| 331 |
|
|
DISPLAY 0x1006, r7, r8
|
| 332 |
|
|
|
| 333 |
|
|
// enable mmu
|
| 334 |
|
|
mrc p15, 0, r0, c1, c0, 0
|
| 335 |
|
|
orr r0, r0, #MMU_Control_M
|
| 336 |
|
|
orr r0, r0, #MMU_Control_R
|
| 337 |
|
|
mcr p15, 0, r0, c1, c0, 0
|
| 338 |
|
|
CPWAIT r0
|
| 339 |
|
|
|
| 340 |
|
|
DISPLAY 0x1007, r7, r8
|
| 341 |
|
|
|
| 342 |
|
|
// enable D cache
|
| 343 |
|
|
mrc p15, 0, r0, c1, c0, 0
|
| 344 |
|
|
orr r0, r0, #MMU_Control_C
|
| 345 |
|
|
mcr p15, 0, r0, c1, c0, 0
|
| 346 |
|
|
CPWAIT r0
|
| 347 |
|
|
|
| 348 |
|
|
DISPLAY 0x1008, r7, r8
|
| 349 |
|
|
|
| 350 |
|
|
// Enable branch target buffer
|
| 351 |
|
|
mrc p15, 0, r0, c1, c0, 0
|
| 352 |
|
|
orr r0, r0, #MMU_Control_BTB
|
| 353 |
|
|
mcr p15, 0, r0, c1, c0, 0
|
| 354 |
|
|
CPWAIT r0
|
| 355 |
|
|
|
| 356 |
|
|
DISPLAY 0x1009, r7, r8
|
| 357 |
|
|
|
| 358 |
|
|
mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
|
| 359 |
|
|
CPWAIT r0
|
| 360 |
|
|
|
| 361 |
|
|
mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
|
| 362 |
|
|
CPWAIT r0
|
| 363 |
|
|
|
| 364 |
|
|
mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
|
| 365 |
|
|
CPWAIT r0
|
| 366 |
|
|
|
| 367 |
|
|
mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
|
| 368 |
|
|
CPWAIT r0
|
| 369 |
|
|
|
| 370 |
|
|
DISPLAY 0x100A, r7, r8
|
| 371 |
|
|
|
| 372 |
|
|
// save SDRAM size
|
| 373 |
|
|
ldr r1, =hal_dram_size /* [see hal_intr.h] */
|
| 374 |
|
|
mov r8, #SDRAM_SIZE
|
| 375 |
|
|
str r8, [r1]
|
| 376 |
|
|
|
| 377 |
|
|
DISPLAY 0x100B, r7, r8
|
| 378 |
|
|
|
| 379 |
|
|
.endm // _platform_setup1
|
| 380 |
|
|
|
| 381 |
|
|
#else // defined(CYG_HAL_STARTUP_ROM)
|
| 382 |
|
|
#define PLATFORM_SETUP1
|
| 383 |
|
|
#endif
|
| 384 |
|
|
|
| 385 |
|
|
#define PLATFORM_VECTORS _platform_vectors
|
| 386 |
|
|
.macro _platform_vectors
|
| 387 |
|
|
.endm
|
| 388 |
|
|
|
| 389 |
|
|
/*---------------------------------------------------------------------------*/
|
| 390 |
|
|
/* end of hal_platform_setup.h */
|
| 391 |
|
|
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
|
