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skrzyp |
/*=============================================================================
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//
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// hal_platform_setup.h
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//
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// Platform specific support for HAL (assembly code)
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): <knud.woehler@microplex.de>
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// Date: 2003-01-09
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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#define CYGONCE_HAL_PLATFORM_SETUP_H
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#include <pkgconf/system.h> // System-wide configuration info
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#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
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#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
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#include <cyg/hal/hal_pxa2x0.h> // Platform specific hardware definitions
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#include <cyg/hal/hal_mmu.h> // MMU definitions
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#include <cyg/hal/hal_mm.h> // more MMU definitions
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#include <cyg/hal/mpc50.h>
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/**********************************************************************************************************************
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* MMU/Cache
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**********************************************************************************************************************/
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.macro init_mmu_cache_on
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ldr r0, =0x2001
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mcr p15, 0, r0, c15, c1, 0
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mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
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CPWAIT r0
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mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
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CPWAIT r0
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mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
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CPWAIT r0
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// Icache on
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #MMU_Control_I
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orr r0, r0, #MMU_Control_BTB // Enable the BTB
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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// create stack for "C"
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ldr r1,=__startup_stack
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ldr r2,=PXA2X0_RAM_BANK0_BASE
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orr sp,r1,r2
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bl hal_mmu_init // create MMU Tables
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// Enable permission checks in all domains
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ldr r0, =0x55555555
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mcr p15, 0, r0, c3, c0, 0
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// MMU on
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ldr r2,=1f
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #MMU_Control_M
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orr r0, r0, #MMU_Control_R
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mcr p15, 0, r0, c1, c0, 0
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mov pc,r2
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nop
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nop
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nop
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1:
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mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
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CPWAIT r0
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// Dcache on
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #MMU_Control_C
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mcr p15, 0, r0, c1, c0, 0
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CPWAIT r0
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// clean/drain/flush the main Dcache
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mov r1, #0xc0000000
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mov r0, #1024
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2:
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mcr p15, 0, r1, c7, c2, 5
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add r1, r1, #32
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subs r0, r0, #1
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bne 2b
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// clean/drain/flush the mini Dcache
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//ldr r1, =(DCACHE_FLUSH_AREA+DCACHE_SIZE) // use a CACHEABLE area of
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mov r0, #64 // number of lines in the mini Dcache
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3:
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mcr p15, 0, r1, c7, c2, 5 // allocate a Dcache line
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add r1, r1, #32 // increment the address to
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subs r0, r0, #1 // decrement the loop count
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bne 3b
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// flush Dcache
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mcr p15, 0, r0, c7, c6, 0
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CPWAIT r0
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// drain the write & fill buffers
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mcr p15, 0, r0, c7, c10, 4
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CPWAIT r0
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.endm
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.macro init_mmu_off
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mov r0, #0x78
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mcr p15, 0, r0, c1, c0, 0 // caches off -- MMU off or ID map
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mcr p15, 0, r0, c7, c7, 0 // Invalidate the I & D cache, mini- d cache, and BTB
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mcr p15, 0, r0, c7, c10, 4 // Drain write buffer -- r0 ignored
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CPWAIT r0
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nop
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nop
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nop
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nop
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mvn r0, #0
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mcr p15, 0, r0, c3, c0, 0
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.endm
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/**********************************************************************************************************************
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* Clock
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**********************************************************************************************************************/
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#define CCCR_OFFS (PXA2X0_CCCR-PXA2X0_CLK_BASE)
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.macro init_clks
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ldr r1, =PXA2X0_CLK_BASE
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// TurboMode=400MHz/RunMode=200MHz/Memory=100MHz/SDRam=100MHz
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// ldr r0, =(PXA2X0_CCCR_L27 | PXA2X0_CCCR_M2 | PXA2X0_CCCR_N20)
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// TurboMode=300MHz/RunMode=200MHz/Memory=100MHz/SDRam=100MHz
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// ldr r0, =(PXA2X0_CCCR_L27 | PXA2X0_CCCR_M2 | PXA2X0_CCCR_N15)
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adr r0, mpc50_static_info
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ldr r0, [r0, #MPC50_VAL_OFFS_CCCR]
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str r0, [r1, #CCCR_OFFS] // set Core Clock
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mov r0, #3
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mcr p14, 0, r0, c6, c0, 0 // Turbo Mode on
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.endm
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/**********************************************************************************************************************
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* Interrupt controller
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**********************************************************************************************************************/
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#define ICLR_OFFS (PXA2X0_ICLR-PXA2X0_IC_BASE)
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#define ICMR_OFFS (PXA2X0_ICMR-PXA2X0_IC_BASE)
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.macro init_intc_cnt
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ldr r1, =PXA2X0_IC_BASE
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mov r0, #0
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str r0, [r1, #ICLR_OFFS] // clear Interrupt level Register
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str r0, [r1, #ICMR_OFFS] // clear Interrupt mask Register
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.endm
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/**********************************************************************************************************************
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* SDRAM
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**********************************************************************************************************************/
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//#define MDCNFG_VAL 0x094B094B // SDRAM Config Reg (32Bit, 9 Col, 13 Row, 2 Bank, CL2)
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//#define MDREFR_VAL 0x0005b018 // SDRAM Refresh Reg SDCLK=memory clock
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//#define MDREFR_VAL 0x000ff018 // SDRAM Refresh Reg SDCLK=1/2 memory clock
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#define MDMRS_VAL 0x00000000 // SDRAM Mode Reg Set Config Reg
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#define MSC0_VAL 0x199123da // CS1(FPGA)/CS0(Flash)
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#define MSC1_VAL 0x7ff07ff1 // CS3(not used)/CS2(ETH)
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#define OSCR_OFFS (PXA2X0_OSCR-PXA2X0_OSTIMER_BASE)
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#define MDREFR_OFFS (PXA2X0_MDREFR-PXA2X0_MEMORY_CTL_BASE)
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#define MDCNFG_OFFS (PXA2X0_MDCNFG-PXA2X0_MEMORY_CTL_BASE)
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#define MDMRS_OFFS (PXA2X0_MDMRS-PXA2X0_MEMORY_CTL_BASE)
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#define MSC0_OFFS (PXA2X0_MSC0-PXA2X0_MEMORY_CTL_BASE)
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#define MSC1_OFFS (PXA2X0_MSC1-PXA2X0_MEMORY_CTL_BASE)
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#define MSC2_OFFS (PXA2X0_MSC2-PXA2X0_MEMORY_CTL_BASE)
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.macro init_sdram_cnt
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// Hardware Reset Operation (S. 5-83)
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// Step 1
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// wait 200 usec
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ldr r1, =PXA2X0_OSTIMER_BASE // set OS Timer Count
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mov r0, #0
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str r0, [r1, #OSCR_OFFS]
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ldr r2, =0x300 // wait 200 usec
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61:
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ldr r0, [r1, #OSCR_OFFS]
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cmp r2, r0
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bgt 61b
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ldr r1, =PXA2X0_MEMORY_CTL_BASE
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ldr r0, =MSC0_VAL
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str r0, [r1, #MSC0_OFFS] // FPGA/Flash
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ldr r0, =MSC1_VAL
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str r0, [r1, #MSC1_OFFS] // ETH
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// Refresh Register
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//ldr r3, =MDREFR_VAL // load SDRAM refresh info
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adr r3, mpc50_static_info
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ldr r3, [r3, #MPC50_VAL_OFFS_MDREFR]
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| 228 |
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| 230 |
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ldr r2, =0xFFF // DRI field
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and r3, r3, r2
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ldr r4, [r1, #MDREFR_OFFS] // read Reset Status
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| 233 |
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bic r4, r4, r2
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bic r4, r4, #(0x01000000 | 0x02000000) // clear K1Free, K2Free,
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| 235 |
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bic r4, r4, #0x00004000 // K0DB2
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| 236 |
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orr r4, r4, r3 // add DRI field
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| 237 |
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str r4, [r1, #MDREFR_OFFS] //
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| 238 |
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ldr r4, [r1, #MDREFR_OFFS]
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| 240 |
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// Step 2
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| 241 |
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//
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| 242 |
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| 243 |
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// Step 3
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| 244 |
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//ldr r3, =MDREFR_VAL // load SDRAM Refresh Info
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| 245 |
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adr r3, mpc50_static_info
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| 246 |
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ldr r3, [r3, #MPC50_VAL_OFFS_MDREFR]
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| 247 |
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| 248 |
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| 249 |
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ldr r2, =0x000f0000
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| 250 |
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and r3, r3, r2
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| 251 |
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orr r4, r4, r3
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| 252 |
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str r4, [r1, #MDREFR_OFFS]
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| 253 |
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ldr r4, [r1, #MDREFR_OFFS]
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| 254 |
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| 255 |
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bic r4, r4, #0x00400000 // Self Refresh off
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| 256 |
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str r4, [r1, #MDREFR_OFFS]
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| 257 |
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ldr r4, [r1, #MDREFR_OFFS]
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| 258 |
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| 259 |
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orr r4, r4, #0x00008000 // SDCKE1 on
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| 260 |
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str r4, [r1, #MDREFR_OFFS]
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| 261 |
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ldr r4, [r1, #MDREFR_OFFS]
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| 262 |
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| 263 |
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orr r4, r4, #0x00800000 // K0Free on
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| 264 |
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str r4, [r1, #MDREFR_OFFS]
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| 265 |
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ldr r4, [r1, #MDREFR_OFFS]
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| 266 |
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nop
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| 267 |
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nop
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| 268 |
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| 269 |
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// Step 4
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| 270 |
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//ldr r2, =MDCNFG_VAL
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| 271 |
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adr r2, mpc50_static_info
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| 272 |
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ldr r2, [r2, #MPC50_VAL_OFFS_MDCNFG]
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| 273 |
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| 274 |
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| 275 |
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bic r2, r2, #0x0003 // DE1-0
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| 276 |
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bic r2, r2, #0x00030000 // DE3-2
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| 277 |
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str r2, [r1, #MDCNFG_OFFS]
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| 278 |
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| 279 |
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// Step 5
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| 280 |
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// wait 200 usec
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| 281 |
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ldr r1, =PXA2X0_OSTIMER_BASE
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| 282 |
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mov r0, #0
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| 283 |
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str r0, [r1, #OSCR_OFFS]
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| 284 |
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ldr r2, =0x300
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| 285 |
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71:
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| 286 |
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ldr r0, [r1, #OSCR_OFFS]
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| 287 |
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cmp r2, r0
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| 288 |
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bgt 71b
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| 289 |
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| 290 |
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// Step 6
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| 291 |
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mov r0, #0x78
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| 292 |
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mcr p15, 0, r0, c1, c0, 0 // (caches off, MMU off, etc.)
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| 293 |
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| 294 |
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// Step 7
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| 295 |
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ldr r2, =PXA2X0_RAM_BANK0_BASE
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| 296 |
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str r2, [r2]
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| 297 |
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str r2, [r2]
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| 298 |
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str r2, [r2]
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| 299 |
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str r2, [r2]
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| 300 |
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str r2, [r2]
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| 301 |
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str r2, [r2]
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| 302 |
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str r2, [r2]
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| 303 |
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str r2, [r2]
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| 304 |
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| 305 |
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// Step 8
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| 306 |
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//
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| 307 |
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// Step 9
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| 308 |
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// SDRAM enable
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| 309 |
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//ldr r3, =MDCNFG_VAL
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| 310 |
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adr r3, mpc50_static_info
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| 311 |
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ldr r3, [r3, #MPC50_VAL_OFFS_MDCNFG]
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| 312 |
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| 313 |
|
|
|
| 314 |
|
|
ldr r2, =0x00030003
|
| 315 |
|
|
and r2, r3, r2
|
| 316 |
|
|
ldr r1, =PXA2X0_MEMORY_CTL_BASE
|
| 317 |
|
|
ldr r3, [r1, #MDCNFG_OFFS]
|
| 318 |
|
|
orr r3, r3, r2
|
| 319 |
|
|
str r3, [r1, #MDCNFG_OFFS]
|
| 320 |
|
|
|
| 321 |
|
|
// Step 10
|
| 322 |
|
|
ldr r2, =MDMRS_VAL
|
| 323 |
|
|
str r2, [r1, #MDMRS_OFFS]
|
| 324 |
|
|
.endm
|
| 325 |
|
|
|
| 326 |
|
|
|
| 327 |
|
|
/**********************************************************************************************************************
|
| 328 |
|
|
* GPIOs
|
| 329 |
|
|
**********************************************************************************************************************/
|
| 330 |
|
|
|
| 331 |
|
|
// GPIO Name Pin GPDR GAFR GPSR
|
| 332 |
|
|
|
| 333 |
|
|
// 0 INT0 L10 0 00 0
|
| 334 |
|
|
// 1 INT1 L12 0 00 0
|
| 335 |
|
|
// 2 FLX-CLK L13 1 00 0
|
| 336 |
|
|
// 3 FLX-DAT K14 1 00 0
|
| 337 |
|
|
|
| 338 |
|
|
// 4 FLX-CONFIG J12 1 00 1
|
| 339 |
|
|
// 5 FLX-STATUS J11 0 00 0
|
| 340 |
|
|
// 6 FLX-CONFDONE H14 0 00 0
|
| 341 |
|
|
// 7 LAN_INT G15 0 00 0
|
| 342 |
|
|
|
| 343 |
|
|
// 8 USB-H-ON F14 1 00 1
|
| 344 |
|
|
// 9 USB-CL-ON F12 0 00 0
|
| 345 |
|
|
// 10 MPSB-INT0 F7 0 00 0
|
| 346 |
|
|
// 11 - A7 0 00 0
|
| 347 |
|
|
|
| 348 |
|
|
// 12 MPSB-INT1 B6 0 00 0
|
| 349 |
|
|
// 13 MBGNT B5 1 10 0
|
| 350 |
|
|
// 14 MBREQ B4 0 01 0
|
| 351 |
|
|
// 15 nCS_1 T8 1 10 1
|
| 352 |
|
|
|
| 353 |
|
|
#define GAFR0_L_VAL 0x80000000 //0x98000000
|
| 354 |
|
|
|
| 355 |
|
|
// 16 PWM0 E12 0 00 0
|
| 356 |
|
|
// 17 PWM1 D12 0 00 0
|
| 357 |
|
|
// 18 RDY C1 0 01 0
|
| 358 |
|
|
// 19 DREQ[1] N14 0 00 0
|
| 359 |
|
|
|
| 360 |
|
|
// 20 DREQ[0] N12 0 00 0
|
| 361 |
|
|
// 21 DVAL0 N15 0 00 0
|
| 362 |
|
|
// 22 DVAL1 M12 0 00 0
|
| 363 |
|
|
// 23 SSPSCLK F9 0 00 0
|
| 364 |
|
|
|
| 365 |
|
|
// 24 SSPSFRM E9 0 00 0
|
| 366 |
|
|
// 25 SSPTXD D9 0 00 0
|
| 367 |
|
|
// 26 SSPRXD A9 0 00 0
|
| 368 |
|
|
// 27 SSPEXTCLK B9 0 00 0
|
| 369 |
|
|
|
| 370 |
|
|
// 28 BITCLK C9 0 00 0
|
| 371 |
|
|
// 29 SDATIN0 E10 0 00 0
|
| 372 |
|
|
// 30 SDATOUT A10 0 00 0
|
| 373 |
|
|
// 31 SYNC E11 0 00 0
|
| 374 |
|
|
|
| 375 |
|
|
#define GPDR0_VAL 0x0000811c //0x0000a11c
|
| 376 |
|
|
#define GAFR0_U_VAL 0x00000010
|
| 377 |
|
|
#define GPSR0_VAL 0x00008110
|
| 378 |
|
|
|
| 379 |
|
|
// 32 SDATIN1 A16 0 00 0
|
| 380 |
|
|
// 33 Reset-Button T13 0 00 0
|
| 381 |
|
|
// 34 FFRXD A13 0 01 0
|
| 382 |
|
|
// 35 FFCTS A14 0 01 0
|
| 383 |
|
|
|
| 384 |
|
|
// 36 FFDCD A12 0 01 0
|
| 385 |
|
|
// 37 FFDSR B11 0 01 0
|
| 386 |
|
|
// 38 FFRI B10 0 01 0
|
| 387 |
|
|
// 39 FFTXD E13 1 10 1
|
| 388 |
|
|
|
| 389 |
|
|
// 40 FFDTR F10 1 10 1
|
| 390 |
|
|
// 41 FFRTS F8 1 10 1
|
| 391 |
|
|
// 42 BTRXD B13 0 00 0
|
| 392 |
|
|
// 43 BTTXD D13 0 00 0
|
| 393 |
|
|
|
| 394 |
|
|
// 44 BTCTS A15 0 00 0
|
| 395 |
|
|
// 45 BTRTS B14 0 00 0
|
| 396 |
|
|
// 46 IRRXD B15 0 00 0
|
| 397 |
|
|
// 47 IRTXD C15 0 00 0
|
| 398 |
|
|
|
| 399 |
|
|
#define GAFR1_L_VAL 0x000a9550
|
| 400 |
|
|
|
| 401 |
|
|
|
| 402 |
|
|
// 48 LED_DP P13 1 00 0
|
| 403 |
|
|
// 49 LED_G T14 1 00 0
|
| 404 |
|
|
// 50 LED_F T15 1 00 0
|
| 405 |
|
|
// 51 LED_E R15 1 00 0
|
| 406 |
|
|
|
| 407 |
|
|
// 52 LED_D P14 1 00 0
|
| 408 |
|
|
// 53 LED_C R16 1 00 0
|
| 409 |
|
|
// 54 LED_B P16 1 00 0
|
| 410 |
|
|
// 55 LED_A M13 1 00 0
|
| 411 |
|
|
|
| 412 |
|
|
// 56 GPIO56 N16 0 00 0
|
| 413 |
|
|
// 57 GPIO57 M16 0 00 0
|
| 414 |
|
|
// 58 LCDD0 E7 0 00 0
|
| 415 |
|
|
// 59 LCDD1 D7 0 00 0
|
| 416 |
|
|
|
| 417 |
|
|
// 60 LCDD2 C7 0 00 0
|
| 418 |
|
|
// 61 LCDD3 B7 0 00 0
|
| 419 |
|
|
// 62 LCDD4 E6 0 00 0
|
| 420 |
|
|
// 63 LCDD5 D6 0 00 0
|
| 421 |
|
|
|
| 422 |
|
|
#define GPDR1_VAL 0x00ff0380
|
| 423 |
|
|
#define GAFR1_U_VAL 0x00000000
|
| 424 |
|
|
#define GPSR1_VAL 0x00000380
|
| 425 |
|
|
#define GPSR_LED_VAL 0x00ff0000
|
| 426 |
|
|
|
| 427 |
|
|
// 64 LCDD6 E5 0 00 0
|
| 428 |
|
|
// 65 LCDD7 A6 0 00 0
|
| 429 |
|
|
// 66 LCDD8 C5 0 00 0
|
| 430 |
|
|
// 67 LCDD9 A5 0 00 0
|
| 431 |
|
|
|
| 432 |
|
|
// 68 LCDD10 D5 0 00 0
|
| 433 |
|
|
// 69 LCDD11 A4 0 00 0
|
| 434 |
|
|
// 70 LCDD12 A3 0 00 0
|
| 435 |
|
|
// 71 LCDD13 A2 0 00 0
|
| 436 |
|
|
|
| 437 |
|
|
// 72 LCDD14 C3 0 00 0
|
| 438 |
|
|
// 73 LCDD15 B3 0 00 0
|
| 439 |
|
|
// 74 LCDFCLK E8 0 00 0
|
| 440 |
|
|
// 75 LCDLCLK D8 0 00 0
|
| 441 |
|
|
|
| 442 |
|
|
// 76 LCDPCLK B8 0 00 0
|
| 443 |
|
|
// 77 LCDBIAS A8 0 00 0
|
| 444 |
|
|
// 78 n_CS2 P9 1 10 1
|
| 445 |
|
|
// 79 LAN_RES T9 1 00 1
|
| 446 |
|
|
|
| 447 |
|
|
#define GAFR2_L_VAL 0x20000000
|
| 448 |
|
|
|
| 449 |
|
|
// 80 n_CS4 R13 0 00 0
|
| 450 |
|
|
|
| 451 |
|
|
#define GPDR2_VAL 0x0000c000
|
| 452 |
|
|
#define GAFR2_U_VAL 0x00000000
|
| 453 |
|
|
#define GPSR2_VAL 0x0000c000
|
| 454 |
|
|
|
| 455 |
|
|
|
| 456 |
|
|
#define GPSR0_OFFS (PXA2X0_GPSR0-PXA2X0_GPIO_BASE)
|
| 457 |
|
|
#define GPCR0_OFFS (PXA2X0_GPCR0-PXA2X0_GPIO_BASE)
|
| 458 |
|
|
#define GPSR1_OFFS (PXA2X0_GPSR1-PXA2X0_GPIO_BASE)
|
| 459 |
|
|
#define GPCR1_OFFS (PXA2X0_GPCR1-PXA2X0_GPIO_BASE)
|
| 460 |
|
|
#define GPSR2_OFFS (PXA2X0_GPSR2-PXA2X0_GPIO_BASE)
|
| 461 |
|
|
#define GPCR2_OFFS (PXA2X0_GPCR2-PXA2X0_GPIO_BASE)
|
| 462 |
|
|
#define GPDR0_OFFS (PXA2X0_GPDR0-PXA2X0_GPIO_BASE)
|
| 463 |
|
|
#define GPDR1_OFFS (PXA2X0_GPDR1-PXA2X0_GPIO_BASE)
|
| 464 |
|
|
#define GPDR2_OFFS (PXA2X0_GPDR2-PXA2X0_GPIO_BASE)
|
| 465 |
|
|
#define GAFR0_L_OFFS (PXA2X0_GAFR0_L-PXA2X0_GPIO_BASE)
|
| 466 |
|
|
#define GAFR0_U_OFFS (PXA2X0_GAFR0_U-PXA2X0_GPIO_BASE)
|
| 467 |
|
|
#define GAFR1_L_OFFS (PXA2X0_GAFR1_L-PXA2X0_GPIO_BASE)
|
| 468 |
|
|
#define GAFR1_U_OFFS (PXA2X0_GAFR1_U-PXA2X0_GPIO_BASE)
|
| 469 |
|
|
#define GAFR2_L_OFFS (PXA2X0_GAFR2_L-PXA2X0_GPIO_BASE)
|
| 470 |
|
|
#define GAFR2_U_OFFS (PXA2X0_GAFR2_U-PXA2X0_GPIO_BASE)
|
| 471 |
|
|
#define PSSR_OFFS (PXA2X0_PSSR-PXA2X0_PM_BASE)
|
| 472 |
|
|
|
| 473 |
|
|
.macro init_mpc_gpio
|
| 474 |
|
|
ldr r1, =PXA2X0_GPIO_BASE
|
| 475 |
|
|
|
| 476 |
|
|
ldr r0, =GPSR0_VAL // set GPIO outputs to default
|
| 477 |
|
|
str r0, [r1, #GPSR0_OFFS]
|
| 478 |
|
|
mvn r0, r0
|
| 479 |
|
|
str r0, [r1, #GPCR0_OFFS]
|
| 480 |
|
|
ldr r0, =GPSR1_VAL // set GPIO outputs to default
|
| 481 |
|
|
str r0, [r1, #GPSR1_OFFS]
|
| 482 |
|
|
mvn r0, r0
|
| 483 |
|
|
str r0, [r1, #GPCR1_OFFS]
|
| 484 |
|
|
ldr r0, =GPSR2_VAL // set GPIO outputs to default
|
| 485 |
|
|
str r0, [r1, #GPSR2_OFFS]
|
| 486 |
|
|
mvn r0, r0
|
| 487 |
|
|
str r0, [r1, #GPCR2_OFFS]
|
| 488 |
|
|
|
| 489 |
|
|
ldr r0, =GPDR0_VAL // GPIO direction
|
| 490 |
|
|
str r0, [r1, #GPDR0_OFFS]
|
| 491 |
|
|
ldr r0, =GPDR1_VAL // GPIO direction
|
| 492 |
|
|
str r0, [r1, #GPDR1_OFFS]
|
| 493 |
|
|
ldr r0, =GPDR2_VAL // GPIO direction
|
| 494 |
|
|
str r0, [r1, #GPDR2_OFFS]
|
| 495 |
|
|
|
| 496 |
|
|
ldr r0, =GAFR0_L_VAL // GPIO alternate function
|
| 497 |
|
|
str r0, [r1, #GAFR0_L_OFFS]
|
| 498 |
|
|
ldr r0, =GAFR0_U_VAL // GPIO alternate function
|
| 499 |
|
|
str r0, [r1, #GAFR0_U_OFFS]
|
| 500 |
|
|
ldr r0, =GAFR1_L_VAL // GPIO alternate function
|
| 501 |
|
|
str r0, [r1, #GAFR1_L_OFFS]
|
| 502 |
|
|
ldr r0, =GAFR1_U_VAL // GPIO alternate function
|
| 503 |
|
|
str r0, [r1, #GAFR1_U_OFFS]
|
| 504 |
|
|
ldr r0, =GAFR2_L_VAL // GPIO alternate function
|
| 505 |
|
|
str r0, [r1, #GAFR2_L_OFFS]
|
| 506 |
|
|
ldr r0, =GAFR2_U_VAL // GPIO alternate function
|
| 507 |
|
|
str r0, [r1, #GAFR2_U_OFFS]
|
| 508 |
|
|
|
| 509 |
|
|
ldr r1, =PXA2X0_PM_BASE
|
| 510 |
|
|
ldr r0, =0x20
|
| 511 |
|
|
str r0, [r1, #PSSR_OFFS] // enable GPIO inputs
|
| 512 |
|
|
|
| 513 |
|
|
.endm
|
| 514 |
|
|
|
| 515 |
|
|
/**********************************************************************************************************************
|
| 516 |
|
|
* LED
|
| 517 |
|
|
**********************************************************************************************************************/
|
| 518 |
|
|
// -7-
|
| 519 |
|
|
// | |
|
| 520 |
|
|
// 1 6
|
| 521 |
|
|
// | |
|
| 522 |
|
|
// -2-
|
| 523 |
|
|
// | |
|
| 524 |
|
|
// 3 5
|
| 525 |
|
|
// | |
|
| 526 |
|
|
// -4- 0
|
| 527 |
|
|
|
| 528 |
|
|
#define CYGHWR_LED_MACRO \
|
| 529 |
|
|
b 2f ;\
|
| 530 |
|
|
1: ;\
|
| 531 |
|
|
.byte 0xfb, 0x61, 0xdd, 0xf5 ;\
|
| 532 |
|
|
.byte 0x67, 0xb7, 0xbf, 0xe1 ;\
|
| 533 |
|
|
.byte 0xff, 0xf7, 0xef, 0x3f ;\
|
| 534 |
|
|
.byte 0x1d, 0x7d, 0x9f, 0x8f ;\
|
| 535 |
|
|
2: ;\
|
| 536 |
|
|
ldr r1, =PXA2X0_GPIO_BASE ;\
|
| 537 |
|
|
mov r0, #0x00ff0000 ;\
|
| 538 |
|
|
str r0, [r1, #GPSR1_OFFS] ;\
|
| 539 |
|
|
sub r0, pc, #((3f+4)-1b) ;\
|
| 540 |
|
|
3: ;\
|
| 541 |
|
|
ldrb r0, [r0, #\x] ;\
|
| 542 |
|
|
mov r0, r0, lsl #16 ;\
|
| 543 |
|
|
str r0, [r1, #GPCR1_OFFS] ;
|
| 544 |
|
|
|
| 545 |
|
|
/**********************************************************************************************************************
|
| 546 |
|
|
* initialize controller
|
| 547 |
|
|
**********************************************************************************************************************/
|
| 548 |
|
|
|
| 549 |
|
|
#if defined(CYG_HAL_STARTUP_ROM)
|
| 550 |
|
|
#define PLATFORM_SETUP1 _platform_setup1
|
| 551 |
|
|
#define CYGHWR_HAL_ARM_HAS_MMU
|
| 552 |
|
|
#else
|
| 553 |
|
|
#define PLATFORM_SETUP1
|
| 554 |
|
|
#endif
|
| 555 |
|
|
|
| 556 |
|
|
.macro _platform_setup1
|
| 557 |
|
|
.rept 0x20/4
|
| 558 |
|
|
nop
|
| 559 |
|
|
.endr
|
| 560 |
|
|
b 1f
|
| 561 |
|
|
|
| 562 |
|
|
.globl mpc50_static_info // Space for some static information
|
| 563 |
|
|
mpc50_static_info:
|
| 564 |
|
|
.byte 'M','P','C','5' // Magic
|
| 565 |
|
|
.rept 16
|
| 566 |
|
|
.long 0
|
| 567 |
|
|
.endr
|
| 568 |
|
|
1:
|
| 569 |
|
|
init_mmu_off // MMU on (and Cache)
|
| 570 |
|
|
init_mpc_gpio // GPIOs
|
| 571 |
|
|
LED(12)
|
| 572 |
|
|
init_sdram_cnt // SDRAM
|
| 573 |
|
|
LED(11)
|
| 574 |
|
|
init_intc_cnt // Interrupt Controller
|
| 575 |
|
|
LED(10)
|
| 576 |
|
|
init_clks // Clocks
|
| 577 |
|
|
LED(9)
|
| 578 |
|
|
init_mmu_cache_on // MMU and Cache
|
| 579 |
|
|
LED(8)
|
| 580 |
|
|
.endm
|
| 581 |
|
|
|
| 582 |
|
|
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
|
| 583 |
|
|
|
