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##=============================================================================
##
##      vectors.S
##
##      CalmRISC16 exception vectors
##
##=============================================================================
## ####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later
## version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License
## along with eCos; if not, write to the Free Software Foundation, Inc.,
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
##
## As a special exception, if other files instantiate templates or use
## macros or inline functions from this file, or you compile this file
## and link it with other works to produce a work based on this file,
## this file does not by itself cause the resulting work to be covered by
## the GNU General Public License. However the source code for this file
## must still be made available in accordance with section (3) of the GNU
## General Public License v2.
##
## This exception does not invalidate any other reasons why a work based
## on this file might be covered by the GNU General Public License.
## -------------------------------------------
## ####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):   msalter
## Contributors: msalter
## Date:        2001-02-12
## Purpose:     CalmRISC16 exception vectors
## Description: This file defines the code placed into the exception
##              vectors. It also contains the first level default VSRs
##              that save and restore state for both exceptions and
##              interrupts.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
#include 
 
#ifdef CYGPKG_KERNEL
# include 
#endif
 
#include 
#include 
 
##-----------------------------------------------------------------------------
## Hardware supplied vectors
 
//==========================================================================
// Hardware exception vectors.
//   This entire section will be copied to location 0x0000 at startup time.
//
        .section ".vectors","ax"
        .global SYM_NAME(reset_vector)
SYM_NAME(reset_vector):
        .short  0x100   ; reset
        .short  0x110   ; fiq
        .short  0x120   ; irq
        .short  0x130   ; trq
        .rept 62
        brad    0f      ; swi
         nop
        .endr
 
        ;; 0x100 - reset
        ld      a8,SYM_NAME(_start)
        jmp     a8
 
        .p2align 4
        ;; 0x110 - fiq
        push    a8
        ld      a8,0
        ldw     a8,@[a8+0]
        jmp     a8
 
        .p2align 4
        ;; 0x120 - irq
        push    a8
        ld      a8,0
        ldw     a8,@[a8+4]
        jmp     a8
 
        .p2align 4
        ;; 0x130 - trq
        push    a8
        ld      a8,0
        ldw     a8,@[a8+8]
        jmp     a8
 
        .p2align 4
        ;; 0x140 - swi
  0:
        push    a8
        ld      a8,0
        ldw     a8,@[a8+12]
        jmp     a8
 
##-----------------------------------------------------------------------------
## Startup code
 
        .text
 
FUNC_START _start
        ld      r0,0
        cld     #28,r0
        cld     #29,r0
        cld     #30,r0
        cld     #31,r0
  2:
        # Initialize hardware
        hal_cpu_init
        hal_diag_init
        hal_memc_init
        hal_cache_init
        hal_timer_init
 
        # load initial stack pointer
        ld      sp,__startup_stack
 
        hal_mon_init
 
#ifdef CYG_HAL_STARTUP_ROM
        # Copy data from ROM to RAM
 
        .extern SYM_NAME(hal_copy_data)
        jsr     SYM_NAME(hal_copy_data)
#endif
        # Zero BSS
 
        .extern SYM_NAME(hal_zero_bss)
        jsr     SYM_NAME(hal_zero_bss)
 
        # Call variant and platform HAL
        # initialization routines.
 
        .extern SYM_NAME(hal_variant_init)
        jsr     SYM_NAME(hal_variant_init)
 
        .extern SYM_NAME(hal_platform_init)
        jsr     SYM_NAME(hal_platform_init)
 
        # Call constructors
        .extern SYM_NAME(cyg_hal_invoke_constructors)
        jsr     SYM_NAME(cyg_hal_invoke_constructors)
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
        .extern SYM_NAME(initialize_stub)
        jsr     SYM_NAME(initialize_stub)
#endif
#if defined(CYGDBG_HAL_CALM16_DEBUG_GDB_CTRLC_SUPPORT)
        .extern SYM_NAME(hal_ctrlc_isr_init)
        jsr     SYM_NAME(hal_ctrlc_isr_init)
#endif
 
        # Call cyg_start
        setsr   fe
        setsr   ie
 
        .extern SYM_NAME(cyg_start)
        ld      lr,SYM_NAME(_start)
        jmp     SYM_NAME(cyg_start)
 
FUNC_END _start
 
#if 0
FUNC_START __txchar
        ldw     r0,@[sp+2]
    99:
        cld     r6,#29
        cmp     eq,r6,#0
        brfd    99b
         nop
        cld     #30,r0
        ld      r6,1
        cld     #29,r6
        jmp     lr
FUNC_END __txchar
#endif
 
        .macro switch_stack_and_save_regs
        // a8 already pushed on the current stack
        push    r0
 
        ld      r0,e15
        and     r0,#0x3f
        cmp     ugt,r0,#%hi(__GDB_stack)
        brt     80f
        // sp <= __GDB_stack
        cmp     eq,r0,#%hi(__GDB_stack)
        brf     80f
        // %hi(sp) == %hi(__GDB_stack)
        ld      a8,#__GDB_stack
        cmp     ugt,r15,r8
        brt     80f
        // don't need switch
        pop     r0
        pop     a8
        sub     sp,#4
        push    a14
        ld      a14,sp
        add     a14,#8
        ldw     @[sp+6],a14
        bra     85f
   80:
        // switch to GDB stack
        pop     r0
        ld      a8,sp
        ld      sp,#__GDB_stack
        add     a8,#4
        push    a8
        push    a14
        sub     a8,#2
        ldw     a8,@[a8+0]
   85:
        // at this point, we're using the correct stack
        // and a15/a14 have been pushed
        push    a13,a12
        push    a11,a10
        push    a9,a8
        push    r7,r6
        push    r5,r4
        push    r3,r2
        push    r1,r0
 
        ld      r0,ssr_swi
        push    r0
        ld      r0,ssr_irq
        push    r0
        ld      r0,ssr_fiq
        push    r0
        ld      r0,spcl_irq
        push    r0
        ld      r0,spch_irq
        push    r0
        ld      r0,spcl_fiq
        push    r0
        ld      r0,spch_fiq
        push    r0
        .endm //  switch_stack_and_save_regs
 
 
        .macro restore_regs
        pop     r0
        ld      spch_fiq,r0
        pop     r0
        ld      spcl_fiq,r0
        pop     r0
        ld      spch_irq,r0
        pop     r0
        ld      spcl_irq,r0
        pop     r0
        ld      ssr_fiq,r0
        pop     r0
        ld      ssr_irq,r0
        pop     r0
        ld      ssr_swi,r0
 
        pop     r0,r1
        pop     r2,r3
        pop     r4,r5
        pop     r6,r7
        pop     a8,a9
        pop     a10,a11
        pop     a12,a13
        pop     a14
        ldw     sp,@[sp+2]
        .endm
 
##------------------------------------------------------------------------------
## Default interrupt VSR.
## Saves machine state and calls appropriate ISR.
 
FUNC_START __default_irq_vsr
 
        // IRQ is overloaded for use by the break insn.
        // For RedBoot (or any stub) on the core eval boards, we treat
        // IRQ as an exception.
 
        switch_stack_and_save_regs
        ld      r0,2
        push    r0
 
#if 0
        // push interrupt_data arg
 
        ld      a8,#SYM_NAME(hal_interrupt_data)
        ldw     a8,@[a8 + 4]
        push    a8
 
        // push vector arg
        push    r0
        ld      r0,0
        push    r0
 
        // call handler
        ld      a8,#SYM_NAME(hal_interrupt_handlers)
        ldw     a8,@[a8 + 4]
        jsr     a8
        add     sp,#10
#else
        // call exception handler
        ld      a8,sp
        add     a8,#2
        push    a8
        jsr     SYM_NAME(cyg_hal_exception_handler)
        add     sp,#6
#endif
 
        restore_regs
        ret_irq
FUNC_END   __default_irq_vsr
 
##------------------------------------------------------------------------------
## Default fast interrupt VSR.
## Saves machine state and calls appropriate ISR.
 
FUNC_START __default_fiq_vsr
 
        switch_stack_and_save_regs
        ld      r0,1
        push    r0
 
        // push interrupt_data arg
        ld      a8,#SYM_NAME(hal_interrupt_data)
        ldw     a8,@[a8 + 0]
        push    a8
 
        // push vector arg
        push    r0
        ld      r0,0
        push    r0
 
        // call handler
        ld      a8,#SYM_NAME(hal_interrupt_handlers)
        ldw     a8,@[a8 + 0]
        jsr     a8
        add     sp,#10
 
        restore_regs
        ret_fiq
FUNC_END   __default_fiq_vsr
 
##------------------------------------------------------------------------------
## Default trace VSR.
## Saves machine state and calls appropriate handler.
 
FUNC_START __default_trq_vsr
        switch_stack_and_save_regs
        ld      r0,3
        push    r0
 
        // call exception handler
        ld      a8,sp
        add     a8,#2
        push    a8
        jsr     SYM_NAME(cyg_hal_exception_handler)
        add     sp,#6
 
        restore_regs
        ret_irq
FUNC_END   __default_trq_vsr
 
##------------------------------------------------------------------------------
## Default swi VSR.
## Saves machine state and calls appropriate handler.
 
FUNC_START __default_swi_vsr
        switch_stack_and_save_regs
        ld      r0,4
        push    r0
 
        // call exception handler
        ld      a8,sp
        add     a8,#2
        push    a8
        jsr     SYM_NAME(cyg_hal_exception_handler)
        add     sp,#6
 
        restore_regs
        ret_swi
FUNC_END   __default_swi_vsr
 
##-----------------------------------------------------------------------------
## Short circuit in case any code tries to use "__gccmain()"
 
FUNC_START __gccmain
        jmp     lr
FUNC_END __gccmain
 
##-----------------------------------------------------------------------------
## Stacks.
## Used during intialization and for executing ISRs.
 
        .section ".bss"
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        .p2align 2
__GDB_stack_base:
        .rept 0x1000
        .byte 0
        .endr
__GDB_stack:
        .long   0
#endif
        .p2align 2
__startup_stack_base:
        .rept 0x1000
        .byte 0
        .endr
        .p2align 2
__startup_stack:
        .long   0
 
##-----------------------------------------------------------------------------
## VSR table.
## The main interrupt code indirects through here to find the VSR
## to execute for each architecture defined interrupt.
## This is only used for simulated targets, on real targets a fixed location VSR
## table is now allocated at 0x000000.
 
#ifndef CYG_HAL_CALM16_VSR_TABLE_DEFINED
 
##      .section ".vsr_table","a"
 
        .data
 
        .globl  SYM_NAME(hal_vsr_table)
 
SYM_NAME(hal_vsr_table):
        .long   SYM_NAME(__default_fiq_vsr)     // FIQ
        .long   SYM_NAME(__default_irq_vsr)     // IRQ
        .long   SYM_NAME(__default_trq_vsr)     // TRQ
        .long   SYM_NAME(__default_swi_vsr)     // SWI
#endif
 
        .data
        .balign 16
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
        // Vectors used to communicate between eCos and ROM environments
        .globl  SYM_NAME(hal_virtual_vector_table)
SYM_NAME(hal_virtual_vector_table):
        .rept   64
        .long   0
        .endr
#endif
 
#------------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
# hal_interrupt_level contains the interrupt level set by
# HAL_INTERRUPT_CONFIGURE().
# This is a default set that provide support only for the single external
# interrupt. Platforms or boards are expected to define their own versions
# of these if they have their own interrupt mappings.
 
#ifndef CYG_HAL_CALM16_ISR_TABLES_DEFINED
 
        .extern SYM_NAME(hal_default_isr)
 
        .data
 
        .globl  SYM_NAME(hal_interrupt_handlers)
SYM_NAME(hal_interrupt_handlers):
        .long   SYM_NAME(hal_default_isr)
        .long   SYM_NAME(hal_default_isr)
 
 
        .globl  SYM_NAME(hal_interrupt_data)
SYM_NAME(hal_interrupt_data):
        .long   0
        .long   0
 
        .globl  SYM_NAME(hal_interrupt_objects)
SYM_NAME(hal_interrupt_objects):
        .long   0
        .long   0
 
#endif
 
##-----------------------------------------------------------------------------
## end of vectors.S
 
 

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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [calmrisc16/] [arch/] [current/] [src/] [vectors.S] - Blame information for rev 868

Line No.	Rev	Author	Line
1	786	skrzyp	`##=============================================================================`
2			`##`
3			`## vectors.S`
4			`##`
5			`## CalmRISC16 exception vectors`
6			`##`
7			`##=============================================================================`
8			`## ####ECOSGPLCOPYRIGHTBEGIN####`
9			`## -------------------------------------------`
10			`## This file is part of eCos, the Embedded Configurable Operating System.`
11			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.`
12			`##`
13			`## eCos is free software; you can redistribute it and/or modify it under`
14			`## the terms of the GNU General Public License as published by the Free`
15			`## Software Foundation; either version 2 or (at your option) any later`
16			`## version.`
17			`##`
18			`## eCos is distributed in the hope that it will be useful, but WITHOUT`
19			`## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
20			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
21			`## for more details.`
22			`##`
23			`## You should have received a copy of the GNU General Public License`
24			`## along with eCos; if not, write to the Free Software Foundation, Inc.,`
25			`## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
26			`##`
27			`## As a special exception, if other files instantiate templates or use`
28			`## macros or inline functions from this file, or you compile this file`
29			`## and link it with other works to produce a work based on this file,`
30			`## this file does not by itself cause the resulting work to be covered by`
31			`## the GNU General Public License. However the source code for this file`
32			`## must still be made available in accordance with section (3) of the GNU`
33			`## General Public License v2.`
34			`##`
35			`## This exception does not invalidate any other reasons why a work based`
36			`## on this file might be covered by the GNU General Public License.`
37			`## -------------------------------------------`
38			`## ####ECOSGPLCOPYRIGHTEND####`
39			`##=============================================================================`
40			`#######DESCRIPTIONBEGIN####`
41			`##`
42			`## Author(s): msalter`
43			`## Contributors: msalter`
44			`## Date: 2001-02-12`
45			`## Purpose: CalmRISC16 exception vectors`
46			`## Description: This file defines the code placed into the exception`
47			`## vectors. It also contains the first level default VSRs`
48			`## that save and restore state for both exceptions and`
49			`## interrupts.`
50			`##`
51			`######DESCRIPTIONEND####`
52			`##`
53			`##=============================================================================`
54
55			`#include`
56			`#include`
57
58			`#ifdef CYGPKG_KERNEL`
59			`# include`
60			`#endif`
61
62			`#include`
63			`#include`
64
65			`##-----------------------------------------------------------------------------`
66			`## Hardware supplied vectors`
67
68			`//==========================================================================`
69			`// Hardware exception vectors.`
70			`// This entire section will be copied to location 0x0000 at startup time.`
71			`//`
72			`.section ".vectors","ax"`
73			`.global SYM_NAME(reset_vector)`
74			`SYM_NAME(reset_vector):`
75			`.short 0x100 ; reset`
76			`.short 0x110 ; fiq`
77			`.short 0x120 ; irq`
78			`.short 0x130 ; trq`
79			`.rept 62`
80			`brad 0f ; swi`
81			`nop`
82			`.endr`
83
84			`;; 0x100 - reset`
85			`ld a8,SYM_NAME(_start)`
86			`jmp a8`
87
88			`.p2align 4`
89			`;; 0x110 - fiq`
90			`push a8`
91			`ld a8,0`
92			`ldw a8,@[a8+0]`
93			`jmp a8`
94
95			`.p2align 4`
96			`;; 0x120 - irq`
97			`push a8`
98			`ld a8,0`
99			`ldw a8,@[a8+4]`
100			`jmp a8`
101
102			`.p2align 4`
103			`;; 0x130 - trq`
104			`push a8`
105			`ld a8,0`
106			`ldw a8,@[a8+8]`
107			`jmp a8`
108
109			`.p2align 4`
110			`;; 0x140 - swi`
111			`0:`
112			`push a8`
113			`ld a8,0`
114			`ldw a8,@[a8+12]`
115			`jmp a8`
116
117			`##-----------------------------------------------------------------------------`
118			`## Startup code`
119
120			`.text`
121
122			`FUNC_START _start`
123			`ld r0,0`
124			`cld #28,r0`
125			`cld #29,r0`
126			`cld #30,r0`
127			`cld #31,r0`
128			`2:`
129			`# Initialize hardware`
130			`hal_cpu_init`
131			`hal_diag_init`
132			`hal_memc_init`
133			`hal_cache_init`
134			`hal_timer_init`
135
136			`# load initial stack pointer`
137			`ld sp,__startup_stack`
138
139			`hal_mon_init`
140
141			`#ifdef CYG_HAL_STARTUP_ROM`
142			`# Copy data from ROM to RAM`
143
144			`.extern SYM_NAME(hal_copy_data)`
145			`jsr SYM_NAME(hal_copy_data)`
146			`#endif`
147			`# Zero BSS`
148
149			`.extern SYM_NAME(hal_zero_bss)`
150			`jsr SYM_NAME(hal_zero_bss)`
151
152			`# Call variant and platform HAL`
153			`# initialization routines.`
154
155			`.extern SYM_NAME(hal_variant_init)`
156			`jsr SYM_NAME(hal_variant_init)`
157
158			`.extern SYM_NAME(hal_platform_init)`
159			`jsr SYM_NAME(hal_platform_init)`
160
161			`# Call constructors`
162			`.extern SYM_NAME(cyg_hal_invoke_constructors)`
163			`jsr SYM_NAME(cyg_hal_invoke_constructors)`
164
165			`#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)`
166			`.extern SYM_NAME(initialize_stub)`
167			`jsr SYM_NAME(initialize_stub)`
168			`#endif`
169			`#if defined(CYGDBG_HAL_CALM16_DEBUG_GDB_CTRLC_SUPPORT)`
170			`.extern SYM_NAME(hal_ctrlc_isr_init)`
171			`jsr SYM_NAME(hal_ctrlc_isr_init)`
172			`#endif`
173
174			`# Call cyg_start`
175			`setsr fe`
176			`setsr ie`
177
178			`.extern SYM_NAME(cyg_start)`
179			`ld lr,SYM_NAME(_start)`
180			`jmp SYM_NAME(cyg_start)`
181
182			`FUNC_END _start`
183
184			`#if 0`
185			`FUNC_START __txchar`
186			`ldw r0,@[sp+2]`
187			`99:`
188			`cld r6,#29`
189			`cmp eq,r6,#0`
190			`brfd 99b`
191			`nop`
192			`cld #30,r0`
193			`ld r6,1`
194			`cld #29,r6`
195			`jmp lr`
196			`FUNC_END __txchar`
197			`#endif`
198
199			`.macro switch_stack_and_save_regs`
200			`// a8 already pushed on the current stack`
201			`push r0`
202
203			`ld r0,e15`
204			`and r0,#0x3f`
205			`cmp ugt,r0,#%hi(__GDB_stack)`
206			`brt 80f`
207			`// sp <= __GDB_stack`
208			`cmp eq,r0,#%hi(__GDB_stack)`
209			`brf 80f`
210			`// %hi(sp) == %hi(__GDB_stack)`
211			`ld a8,#__GDB_stack`
212			`cmp ugt,r15,r8`
213			`brt 80f`
214			`// don't need switch`
215			`pop r0`
216			`pop a8`
217			`sub sp,#4`
218			`push a14`
219			`ld a14,sp`
220			`add a14,#8`
221			`ldw @[sp+6],a14`
222			`bra 85f`
223			`80:`
224			`// switch to GDB stack`
225			`pop r0`
226			`ld a8,sp`
227			`ld sp,#__GDB_stack`
228			`add a8,#4`
229			`push a8`
230			`push a14`
231			`sub a8,#2`
232			`ldw a8,@[a8+0]`
233			`85:`
234			`// at this point, we're using the correct stack`
235			`// and a15/a14 have been pushed`
236			`push a13,a12`
237			`push a11,a10`
238			`push a9,a8`
239			`push r7,r6`
240			`push r5,r4`
241			`push r3,r2`
242			`push r1,r0`
243
244			`ld r0,ssr_swi`
245			`push r0`
246			`ld r0,ssr_irq`
247			`push r0`
248			`ld r0,ssr_fiq`
249			`push r0`
250			`ld r0,spcl_irq`
251			`push r0`
252			`ld r0,spch_irq`
253			`push r0`
254			`ld r0,spcl_fiq`
255			`push r0`
256			`ld r0,spch_fiq`
257			`push r0`
258			`.endm // switch_stack_and_save_regs`
259
260
261			`.macro restore_regs`
262			`pop r0`
263			`ld spch_fiq,r0`
264			`pop r0`
265			`ld spcl_fiq,r0`
266			`pop r0`
267			`ld spch_irq,r0`
268			`pop r0`
269			`ld spcl_irq,r0`
270			`pop r0`
271			`ld ssr_fiq,r0`
272			`pop r0`
273			`ld ssr_irq,r0`
274			`pop r0`
275			`ld ssr_swi,r0`
276
277			`pop r0,r1`
278			`pop r2,r3`
279			`pop r4,r5`
280			`pop r6,r7`
281			`pop a8,a9`
282			`pop a10,a11`
283			`pop a12,a13`
284			`pop a14`
285			`ldw sp,@[sp+2]`
286			`.endm`
287
288			`##------------------------------------------------------------------------------`
289			`## Default interrupt VSR.`
290			`## Saves machine state and calls appropriate ISR.`
291
292			`FUNC_START __default_irq_vsr`
293
294			`// IRQ is overloaded for use by the break insn.`
295			`// For RedBoot (or any stub) on the core eval boards, we treat`
296			`// IRQ as an exception.`
297
298			`switch_stack_and_save_regs`
299			`ld r0,2`
300			`push r0`
301
302			`#if 0`
303			`// push interrupt_data arg`
304
305			`ld a8,#SYM_NAME(hal_interrupt_data)`
306			`ldw a8,@[a8 + 4]`
307			`push a8`
308
309			`// push vector arg`
310			`push r0`
311			`ld r0,0`
312			`push r0`
313
314			`// call handler`
315			`ld a8,#SYM_NAME(hal_interrupt_handlers)`
316			`ldw a8,@[a8 + 4]`
317			`jsr a8`
318			`add sp,#10`
319			`#else`
320			`// call exception handler`
321			`ld a8,sp`
322			`add a8,#2`
323			`push a8`
324			`jsr SYM_NAME(cyg_hal_exception_handler)`
325			`add sp,#6`
326			`#endif`
327
328			`restore_regs`
329			`ret_irq`
330			`FUNC_END __default_irq_vsr`
331
332			`##------------------------------------------------------------------------------`
333			`## Default fast interrupt VSR.`
334			`## Saves machine state and calls appropriate ISR.`
335
336			`FUNC_START __default_fiq_vsr`
337
338			`switch_stack_and_save_regs`
339			`ld r0,1`
340			`push r0`
341
342			`// push interrupt_data arg`
343			`ld a8,#SYM_NAME(hal_interrupt_data)`
344			`ldw a8,@[a8 + 0]`
345			`push a8`
346
347			`// push vector arg`
348			`push r0`
349			`ld r0,0`
350			`push r0`
351
352			`// call handler`
353			`ld a8,#SYM_NAME(hal_interrupt_handlers)`
354			`ldw a8,@[a8 + 0]`
355			`jsr a8`
356			`add sp,#10`
357
358			`restore_regs`
359			`ret_fiq`
360			`FUNC_END __default_fiq_vsr`
361
362			`##------------------------------------------------------------------------------`
363			`## Default trace VSR.`
364			`## Saves machine state and calls appropriate handler.`
365
366			`FUNC_START __default_trq_vsr`
367			`switch_stack_and_save_regs`
368			`ld r0,3`
369			`push r0`
370
371			`// call exception handler`
372			`ld a8,sp`
373			`add a8,#2`
374			`push a8`
375			`jsr SYM_NAME(cyg_hal_exception_handler)`
376			`add sp,#6`
377
378			`restore_regs`
379			`ret_irq`
380			`FUNC_END __default_trq_vsr`
381
382			`##------------------------------------------------------------------------------`
383			`## Default swi VSR.`
384			`## Saves machine state and calls appropriate handler.`
385
386			`FUNC_START __default_swi_vsr`
387			`switch_stack_and_save_regs`
388			`ld r0,4`
389			`push r0`
390
391			`// call exception handler`
392			`ld a8,sp`
393			`add a8,#2`
394			`push a8`
395			`jsr SYM_NAME(cyg_hal_exception_handler)`
396			`add sp,#6`
397
398			`restore_regs`
399			`ret_swi`
400			`FUNC_END __default_swi_vsr`
401
402			`##-----------------------------------------------------------------------------`
403			`## Short circuit in case any code tries to use "__gccmain()"`
404
405			`FUNC_START __gccmain`
406			`jmp lr`
407			`FUNC_END __gccmain`
408
409			`##-----------------------------------------------------------------------------`
410			`## Stacks.`
411			`## Used during intialization and for executing ISRs.`
412
413			`.section ".bss"`
414
415			`#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS`
416			`.p2align 2`
417			`__GDB_stack_base:`
418			`.rept 0x1000`
419			`.byte 0`
420			`.endr`
421			`__GDB_stack:`
422			`.long 0`
423			`#endif`
424			`.p2align 2`
425			`__startup_stack_base:`
426			`.rept 0x1000`
427			`.byte 0`
428			`.endr`
429			`.p2align 2`
430			`__startup_stack:`
431			`.long 0`
432
433			`##-----------------------------------------------------------------------------`
434			`## VSR table.`
435			`## The main interrupt code indirects through here to find the VSR`
436			`## to execute for each architecture defined interrupt.`
437			`## This is only used for simulated targets, on real targets a fixed location VSR`
438			`## table is now allocated at 0x000000.`
439
440			`#ifndef CYG_HAL_CALM16_VSR_TABLE_DEFINED`
441
442			`## .section ".vsr_table","a"`
443
444			`.data`
445
446			`.globl SYM_NAME(hal_vsr_table)`
447
448			`SYM_NAME(hal_vsr_table):`
449			`.long SYM_NAME(__default_fiq_vsr) // FIQ`
450			`.long SYM_NAME(__default_irq_vsr) // IRQ`
451			`.long SYM_NAME(__default_trq_vsr) // TRQ`
452			`.long SYM_NAME(__default_swi_vsr) // SWI`
453			`#endif`
454
455			`.data`
456			`.balign 16`
457			`#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT`
458			`// Vectors used to communicate between eCos and ROM environments`
459			`.globl SYM_NAME(hal_virtual_vector_table)`
460			`SYM_NAME(hal_virtual_vector_table):`
461			`.rept 64`
462			`.long 0`
463			`.endr`
464			`#endif`
465
466			`#------------------------------------------------------------------------------`
467			`# Interrupt vector tables.`
468			`# These tables contain the isr, data and object pointers used to deliver`
469			`# interrupts to user code.`
470			`# hal_interrupt_level contains the interrupt level set by`
471			`# HAL_INTERRUPT_CONFIGURE().`
472			`# This is a default set that provide support only for the single external`
473			`# interrupt. Platforms or boards are expected to define their own versions`
474			`# of these if they have their own interrupt mappings.`
475
476			`#ifndef CYG_HAL_CALM16_ISR_TABLES_DEFINED`
477
478			`.extern SYM_NAME(hal_default_isr)`
479
480			`.data`
481
482			`.globl SYM_NAME(hal_interrupt_handlers)`
483			`SYM_NAME(hal_interrupt_handlers):`
484			`.long SYM_NAME(hal_default_isr)`
485			`.long SYM_NAME(hal_default_isr)`
486
487
488			`.globl SYM_NAME(hal_interrupt_data)`
489			`SYM_NAME(hal_interrupt_data):`
490			`.long 0`
491			`.long 0`
492
493			`.globl SYM_NAME(hal_interrupt_objects)`
494			`SYM_NAME(hal_interrupt_objects):`
495			`.long 0`
496			`.long 0`
497
498			`#endif`
499
500			`##-----------------------------------------------------------------------------`
501			`## end of vectors.S`
502
503