OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [calmrisc32/] [arch/] [current/] [src/] [context.S] - Blame information for rev 791

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
##=============================================================================##
2
##      context.S
3
##
4
##      CalmRISC32 context switch code
5
##
6
##=============================================================================
7
## ####ECOSGPLCOPYRIGHTBEGIN####
8
## -------------------------------------------
9
## This file is part of eCos, the Embedded Configurable Operating System.
10
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
11
##
12
## eCos is free software; you can redistribute it and/or modify it under
13
## the terms of the GNU General Public License as published by the Free
14
## Software Foundation; either version 2 or (at your option) any later
15
## version.
16
##
17
## eCos is distributed in the hope that it will be useful, but WITHOUT
18
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
## for more details.
21
##
22
## You should have received a copy of the GNU General Public License
23
## along with eCos; if not, write to the Free Software Foundation, Inc.,
24
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
25
##
26
## As a special exception, if other files instantiate templates or use
27
## macros or inline functions from this file, or you compile this file
28
## and link it with other works to produce a work based on this file,
29
## this file does not by itself cause the resulting work to be covered by
30
## the GNU General Public License. However the source code for this file
31
## must still be made available in accordance with section (3) of the GNU
32
## General Public License v2.
33
##
34
## This exception does not invalidate any other reasons why a work based
35
## on this file might be covered by the GNU General Public License.
36
## -------------------------------------------
37
## ####ECOSGPLCOPYRIGHTEND####
38
##=============================================================================
39
#######DESCRIPTIONBEGIN####
40
##
41
## Author(s):   msalter
42
## Contributors: msalter
43
## Date:        2001-02-12
44
## Purpose:     CalmRISC32 context switch code
45
## Description: This file contains implementations of the thread context
46
##              switch routines. It also contains the longjmp() and setjmp()
47
##              routines.
48
##
49
######DESCRIPTIONEND####
50
##
51
##=============================================================================
52
 
53
#include 
54
#include 
55
 
56
#------------------------------------------------------------------------------
57
# hal_thread_switch_context
58
# Switch thread contexts
59
# A0 = address of sp of next thread to execute
60
# A1 = address of sp save location of current thread
61
 
62
        .global hal_thread_switch_context
63
hal_thread_switch_context:
64
        // FIXME
65
        # Now load the destination thread by dropping through
66
        # to hal_thread_load_context
67
 
68
#------------------------------------------------------------------------------
69
# hal_thread_load_context
70
# Load thread context
71
# A0 = address of sp of next thread to execute
72
# Note that this function is also the second half of hal_thread_switch_context
73
# and is simply dropped into from it.
74
 
75
        .global hal_thread_load_context
76
hal_thread_load_context:
77
        // FIXME
78
 
79
#------------------------------------------------------------------------------
80
# HAL longjmp, setjmp implementations
81
# hal_setjmp saves only callee save registers into given buffer
82
# Note: These definitions are repeated in hal_arch.h. If changes are required
83
# remember to update both sets.
84
 
85
#define CYGARC_JMP_BUF_R0        0
86
#define CYGARC_JMP_BUF_R1        1
87
#define CYGARC_JMP_BUF_R2        2
88
#define CYGARC_JMP_BUF_R3        3
89
#define CYGARC_JMP_BUF_R4        4
90
#define CYGARC_JMP_BUF_R5        5
91
#define CYGARC_JMP_BUF_R6        6
92
#define CYGARC_JMP_BUF_R7        7
93
#define CYGARC_JMP_BUF_R12       8
94
#define CYGARC_JMP_BUF_R13       9
95
#define CYGARC_JMP_BUF_R14      10
96
#define CYGARC_JMP_BUF_R15      11
97
 
98
#define CYGARC_JMP_BUF_SIZE     48
99
 
100
// FIXME: The follwing restricts us to using only 32 bit registers
101
// in jump buffers. If/when we move to a full 64 bit architecture,
102
// this will need to change, as will the instructions that we use to
103
// save and restore them.
104
 
105
#define jmpbuf_regsize 4
106
 
107
        .globl  hal_setjmp
108
hal_setjmp:
109
        ld      r8, r0
110
        ldw     @[r8+0], r0
111
        ldw     @[r8+4], r1
112
        ldw     @[r8+8], r2
113
        ldw     @[r8+12], r3
114
        ldw     @[r8+16], r4
115
        ldw     @[r8+20], r5
116
        ldw     @[r8+24], r6
117
        ldw     @[r8+28], r7
118
        ldw     @[r8+32], r12
119
        ldw     @[r8+36], r13
120
        ldw     @[r8+40], r14
121
        ldw     @[r8+44], sp
122
 
123
        jmpd    r14
124
         ldw    r0, #0
125
 
126
        .globl  hal_longjmp
127
hal_longjmp:
128
        ld      r9, r0
129
        ld      r8, r1
130
        ldw     sp, @[r9+44]
131
        ldw     r14, @[r9+40]
132
        ldw     r13, @[r9+36]
133
        ldw     r12, @[r9+32]
134
        ldw     r7, @[r9+28]
135
        ldw     r6, @[r9+24]
136
        ldw     r5, @[r9+20]
137
        ldw     r4, @[r9+16]
138
        ldw     r3, @[r9+12]
139
        ldw     r2, @[r9+8]
140
        ldw     r1, @[r9+4]
141
        # Value to return is in r8.  If zero, return 1
142
        ld      r0, r8
143
        cmp eq  r0, #0
144
        brf     0f
145
        ldw     r0, #1
146
    0:
147
        jmpd    r14
148
         nop
149
 
150
 
151
#------------------------------------------------------------------------------
152
# end of context.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.