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##=============================================================================
##
##      vectors.S
##
##      CalmRISC32 exception vectors
##
##=============================================================================
## ####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later
## version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License
## along with eCos; if not, write to the Free Software Foundation, Inc.,
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
##
## As a special exception, if other files instantiate templates or use
## macros or inline functions from this file, or you compile this file
## and link it with other works to produce a work based on this file,
## this file does not by itself cause the resulting work to be covered by
## the GNU General Public License. However the source code for this file
## must still be made available in accordance with section (3) of the GNU
## General Public License v2.
##
## This exception does not invalidate any other reasons why a work based
## on this file might be covered by the GNU General Public License.
## -------------------------------------------
## ####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):   msalter
## Contributors: msalter
## Date:        2001-02-12
## Purpose:     CalmRISC32 exception vectors
## Description: This file defines the code placed into the exception
##              vectors. It also contains the first level default VSRs
##              that save and restore state for both exceptions and
##              interrupts.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
#include 
#include 
 
#ifdef CYGPKG_KERNEL
# include 
#else
# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
#endif
 
#include 
#include 
 
        .macro  txreg reg
    99:
        cld     r0,fr29
        cmp     eq r0,#0
        brfd    99b
         nop
        cld     fr30,\reg
        ld      r0,#1
        cld     fr29,r0
        .endm
 
        .extern cyg_instrument
 
##-----------------------------------------------------------------------------
## Hardware supplied vectors
 
        .macro  cpu_vector  vsr_nr
        setsr   bs
        clrsr   rs0
        clrsr   rs1
        nop
        push    r8
        brad    __exc_trampoline
         ld     r8,#\vsr_nr
        .endm
 
##==========================================================================
## Hardware exception vectors.
##
        .section ".vectors","ax"
        .global reset_vector
reset_vector:
        ldw     r0,#_start
        jmpd    r0
         nop
 
        # 0x20 - FIQ
        .p2align 5
        cpu_vector 0
 
        # 0x40 - IRQ
        .p2align 5
        cpu_vector 1
 
        # 0x50 - COP
        .p2align 4
        cpu_vector 2
 
        # 0x60 - DABRT
        .p2align 4
        cpu_vector 3
 
        # 0x70 - IABRT
        .p2align 4
        cpu_vector 4
 
        # 0x80 - PRIV
        .p2align 4
        cpu_vector 5
 
        # 0xA0 - UNIMPL
        .p2align 5
        cpu_vector 6
 
        # 0xC0 - TRACE
        .p2align 5
        cpu_vector 7
 
        # 0x100 - SWI 0
        .p2align 6
        cpu_vector 8
 
        # SWI 1
        .p2align 4
        cpu_vector 8
 
        # SWI 2
        .p2align 4
        cpu_vector 8
 
        # SWI 3
        .p2align 4
        cpu_vector 8
 
        # SWI 4
        .p2align 4
        cpu_vector 8
 
        # SWI 5
        .p2align 4
        cpu_vector 8
 
        # SWI 6
        .p2align 4
        cpu_vector 8
 
        # SWI 7
        .p2align 4
        cpu_vector 8
 
        # SWI 8
        .p2align 4
        cpu_vector 8
 
        # SWI 9
        .p2align 4
        cpu_vector 8
 
        # SWI 10
        .p2align 4
        cpu_vector 8
 
        # SWI 11
        .p2align 4
        cpu_vector 8
 
        # SWI 12
        .p2align 4
        cpu_vector 8
 
        # SWI 13
        .p2align 4
        cpu_vector 8
 
        # SWI 14
        .p2align 4
        cpu_vector 8
 
        # SWI 15
        .p2align 4
        cpu_vector 8
 
__exc_trampoline:
        push    r8      // vsr number
        sl2     r8      // offset into vsr table
        ldw     r8,@[r8 + 0]
        jmpd    r8
         pop    r8
 
##-----------------------------------------------------------------------------
## Startup code
 
        .text
 
FUNC_START _start
        # default vector table
        ld      r0,#0
        ld      vbr,r0
 
        # ensure privileged mode with all bank1 register view
        setsr   pm
        setsr   bs
        clrsr   rs0
        clrsr   rs1
 
        # Initialize hardware
        hal_cpu_init
        hal_diag_init
        hal_memc_init
        hal_cache_init
        hal_timer_init
 
        # load initial stack pointer
        ldw     sp,#__startup_stack
 
        clrsr   bs
        nop
        ldw     sp,#__user_stack
        setsr   bs
        nop
 
        hal_mon_init
 
#ifdef CYG_HAL_STARTUP_ROM
        # Copy data from ROM to RAM
 
        .extern hal_copy_data
        ldw     r0,#hal_copy_data
        jsrd    r0
         nop
#endif
 
        # Zero BSS
 
        .extern hal_zero_bss
        ldw     r0,#hal_zero_bss
        jsrd    r0
         nop
 
        # Call variant and platform HAL
        # initialization routines.
 
        .extern hal_variant_init
        ldw     r0,#hal_variant_init
        jsrd    r0
         nop
 
        .extern hal_platform_init
        ldw     r0,#hal_platform_init
        jsrd    r0
         nop
 
        # Call constructors
        .extern cyg_hal_invoke_constructors
        ldw     r0,#cyg_hal_invoke_constructors
        jsrd     r0
         nop
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
        .extern initialize_stub
        ldw     r0,#initialize_stub
        jsrd     r0
         nop
#endif
 
#if defined(CYGDBG_HAL_CALM32_DEBUG_GDB_CTRLC_SUPPORT)
        .extern hal_ctrlc_isr_init
        ldw     r0,#hal_ctrlc_isr_init
        jsrd     r0
         nop
#endif
 
        # Call cyg_start
 
        .extern cyg_start
#if 0
        clrsr   pm
        nop
        clrsr   bs
        nop
#endif
        ld      fp,sp
 
        ldw     lr,#_start
        ldw     r0,#cyg_start
        jmpd    r0
         nop
FUNC_END _start
 
 
        .macro switch_stack_and_save_regs tmpvar
        // save vector number temporarily
        push    r9
        ldw     r9,#\tmpvar
        ldw     @[r9 + 0],r8
        pop     r9
 
        // Make sure we use the gdb stack
        ldw     r8,#__GDB_stack
        cmpu    gt sp,r8
        brtd    0f
         nop
        ldw     r8,#__GDB_stack_base
        cmpu    gt sp,r8
        brtd    1f
         nop
    0:
        // need to switch stack
        ld      r8,sp
        add     r8,#4
        ldw     sp,#__GDB_stack
        push    r8
        push    r14
        push    r13
        push    r12
        sub     r8,#4
        brad    2f
         ldw    r8,@[r8+0]
    1:
        // already using gdb stack
        pop     r8
        // save bank 1 regs
        push    q3
    2:
        // save rest of bank1 regs
        push    q2
        push    q1
        push    q0
 
        // save bank 0 regs
        setsr   rs1
        nop
        push    q1
        push    q0
        clrsr   rs1
        setsr   rs0
        nop
        push    q1
        push    q0
        clrsr   rs0
        nop
        // save special regs
        ld      r0,ssr_expt
        push    r0
        ld      r0,ssr_swi
        push    r0
        ld      r0,ssr_fiq
        push    r0
        ld      r0,ssr_irq
        push    r0
        ld      r0,spc_expt
        push    r0
        ld      r0,spc_swi
        push    r0
        ld      r0,spc_fiq
        push    r0
        ld      r0,spc_irq
        push    r0
        ld      r0,vbr
        push    r0
 
        ldw     r8,#\tmpvar
        ldw     r8,@[r8+0]
        push    r8
        .endm
 
        .macro restore_regs
        // discard vector
        pop     r0
        // restore special regs
        pop     r0
        ld      vbr,r0
        pop     r0
        ld      spc_irq,r0
        pop     r0
        ld      spc_fiq,r0
        pop     r0
        ld      spc_swi,r0
        pop     r0
        ld      spc_expt,r0
        pop     r0
        ld      ssr_irq,r0
        pop     r0
        ld      ssr_fiq,r0
        pop     r0
        ld      ssr_swi,r0
        pop     r0
        ld      ssr_expt,r0
        // restore bank 0 regs
        setsr   rs1
        nop
        pop     q0
        pop     q1
        clrsr   rs1
        setsr   rs0
        nop
        pop     q0
        pop     q1
        clrsr   rs0
        nop
        // restore bank 1 regs
        pop     q0
        pop     q1
        pop     q2
        pop     q3
        .endm
 
 
##-----------------------------------------------------------------------------
## Default exception VSR.
## Saves machine state and calls external handling code.
## On entry, the original R8 has been pushed on the stack and R8 now
## contains the vector number.
 
FUNC_START __default_exception_vsr
 
        switch_stack_and_save_regs __expt_temp
 
        // call exception handler
        ldw     r8,#cyg_hal_exception_handler
        jsrd    r8
         ld     r0,sp
 
        restore_regs
 
        ret_expt
         nop
 
FUNC_END   __default_exception_vsr
 
##-----------------------------------------------------------------------------
## Default swi VSR.
## Saves machine state and calls external handling code.
## On entry, the original R8 has been pushed on the stack and R8 now
## contains the vector number.
 
FUNC_START __default_swi_vsr
 
        switch_stack_and_save_regs __swi_temp
 
        // call exception handler
        ldw     r8,#cyg_hal_exception_handler
        jsrd    r8
         ld     r0,sp
 
        restore_regs
 
        ret_swi
         nop
 
FUNC_END  __default_swi_vsr
 
##------------------------------------------------------------------------------
## Default interrupt VSR.
## Saves machine state and calls appropriate ISR. When done, calls
## interrupt_end() to finish up and possibly reschedule.
 
FUNC_START __default_fiq_vsr
        switch_stack_and_save_regs __fiq_temp
 
        ldw     r8,#hal_interrupt_data
        ldw     r1,@[r8 + 0]
        ldw     r8,#hal_interrupt_handlers
        ldw     r8,@[r8 + 0]
 
        // call fiq handler
        jsrd    r8
         ld     r0,#0
 
        restore_regs
 
        ret_fiq
         nop
FUNC_END   __default_fiq_vsr
 
FUNC_START __default_irq_vsr
        switch_stack_and_save_regs __irq_temp
 
        ldw     r8,#hal_interrupt_data
        ldw     r1,@[r8 + 4]
        ldw     r8,#hal_interrupt_handlers
        ldw     r8,@[r8 + 4]
 
        // call fiq handler
        jsrd    r8
         ld     r0,#1
 
        restore_regs
 
        ret_irq
         nop
FUNC_END   __default_irq_vsr
 
##-----------------------------------------------------------------------------
## Execute pending DSRs on the interrupt stack with interrupts enabled.
## Note: this can only be called from code running on a thread stack
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
        .extern cyg_interrupt_call_pending_DSRs
 
FUNC_START hal_interrupt_stack_call_pending_DSRs
FUNC_END hal_interrupt_stack_call_pending_DSRs
#endif
 
##-----------------------------------------------------------------------------
## Short circuit in case any code tries to use "__gccmain()"
 
FUNC_START __gccmain
        jmpd    lr
         nop
FUNC_END __gccmain
 
##-----------------------------------------------------------------------------
## Interrupt Stack.
## Used during intialization and for executing ISRs.
 
        .section ".bss"
 
        .balign 16
        .global cyg_interrupt_stack_base
cyg_interrupt_stack_base:
__interrupt_stack_base:
        .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
        .byte 0
        .endr
        .balign 16
        .global cyg_interrupt_stack
cyg_interrupt_stack:
__interrupt_stack:
 
        .long   0
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        .balign 16
__GDB_stack_base:
        .rept 0x400
        .byte 0
        .endr
__GDB_stack:
        .long   0
#endif
        .balign 16
__startup_stack_base:
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
        .rept 512
#else
        .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#endif
        .byte 0
        .endr
        .balign 16
__startup_stack:
        .long   0
 
        .balign 16
__user_stack_base:
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
        .rept 512
#else
        .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#endif
        .byte 0
        .endr
        .balign 16
__user_stack:
        .long   0
 
__expt_temp:
        .long   0
__swi_temp:
        .long   0
__irq_temp:
        .long   0
__fiq_temp:
        .long   0
 
 
##-----------------------------------------------------------------------------
## VSR table.
## The main interrupt code indirects through here to find the VSR
## to execute for each architecture defined interrupt.
## This is only used for simulated targets, on real targets a fixed location VSR
## table is now allocated at 0x80000100.
 
#ifndef CYG_HAL_CALM32_VSR_TABLE_DEFINED
 
##      .section ".vsr_table","a"
 
        .data
 
        .globl  hal_vsr_table
hal_vsr_table:
        .long   __default_fiq_vsr       // FIQ
        .long   __default_irq_vsr       // IRQ
        .long   __default_exception_vsr // COP
        .long   __default_exception_vsr // DABRT
        .long   __default_exception_vsr // IABRT
        .long   __default_exception_vsr // PRIV
        .long   __default_exception_vsr // UNIMPL
        .long   __default_exception_vsr // TRACE
        .long   __default_swi_vsr       // SWI
#endif
 
        .balign 16
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
        ## Vectors used to communicate between eCos and ROM environments
        .globl  hal_virtual_vector_table
hal_virtual_vector_table:
        .rept   64
        .long   0
        .endr
#endif
 
#------------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
# hal_interrupt_level contains the interrupt level set by
# HAL_INTERRUPT_CONFIGURE().
# This is a default set that provide support only for the single external
# interrupt. Platforms or boards are expected to define their own versions
# of these if they have their own interrupt mappings.
 
#ifndef CYG_HAL_CALM32_ISR_TABLES_DEFINED
 
        .extern hal_default_isr
 
        .data
 
        .globl  hal_interrupt_handlers
hal_interrupt_handlers:
        .long   hal_default_isr
        .long   hal_default_isr
 
 
        .globl  hal_interrupt_data
hal_interrupt_data:
        .long   0
        .long   0
 
        .globl  hal_interrupt_objects
hal_interrupt_objects:
        .long   0
        .long   0
#endif
 
        .data
        .globl __break_inst_in_data
__break_inst_in_data:
        .short 0x80e0
 
 
##-----------------------------------------------------------------------------
## end of vectors.S
 
 

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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [calmrisc32/] [arch/] [current/] [src/] [vectors.S] - Blame information for rev 786

Line No.	Rev	Author	Line
1	786	skrzyp	`##=============================================================================`
2			`##`
3			`## vectors.S`
4			`##`
5			`## CalmRISC32 exception vectors`
6			`##`
7			`##=============================================================================`
8			`## ####ECOSGPLCOPYRIGHTBEGIN####`
9			`## -------------------------------------------`
10			`## This file is part of eCos, the Embedded Configurable Operating System.`
11			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.`
12			`##`
13			`## eCos is free software; you can redistribute it and/or modify it under`
14			`## the terms of the GNU General Public License as published by the Free`
15			`## Software Foundation; either version 2 or (at your option) any later`
16			`## version.`
17			`##`
18			`## eCos is distributed in the hope that it will be useful, but WITHOUT`
19			`## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
20			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
21			`## for more details.`
22			`##`
23			`## You should have received a copy of the GNU General Public License`
24			`## along with eCos; if not, write to the Free Software Foundation, Inc.,`
25			`## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
26			`##`
27			`## As a special exception, if other files instantiate templates or use`
28			`## macros or inline functions from this file, or you compile this file`
29			`## and link it with other works to produce a work based on this file,`
30			`## this file does not by itself cause the resulting work to be covered by`
31			`## the GNU General Public License. However the source code for this file`
32			`## must still be made available in accordance with section (3) of the GNU`
33			`## General Public License v2.`
34			`##`
35			`## This exception does not invalidate any other reasons why a work based`
36			`## on this file might be covered by the GNU General Public License.`
37			`## -------------------------------------------`
38			`## ####ECOSGPLCOPYRIGHTEND####`
39			`##=============================================================================`
40			`#######DESCRIPTIONBEGIN####`
41			`##`
42			`## Author(s): msalter`
43			`## Contributors: msalter`
44			`## Date: 2001-02-12`
45			`## Purpose: CalmRISC32 exception vectors`
46			`## Description: This file defines the code placed into the exception`
47			`## vectors. It also contains the first level default VSRs`
48			`## that save and restore state for both exceptions and`
49			`## interrupts.`
50			`##`
51			`######DESCRIPTIONEND####`
52			`##`
53			`##=============================================================================`
54
55			`#include`
56			`#include`
57			`#include`
58
59			`#ifdef CYGPKG_KERNEL`
60			`# include`
61			`#else`
62			`# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT`
63			`# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
64			`#endif`
65
66			`#include`
67			`#include`
68
69			`.macro txreg reg`
70			`99:`
71			`cld r0,fr29`
72			`cmp eq r0,#0`
73			`brfd 99b`
74			`nop`
75			`cld fr30,\reg`
76			`ld r0,#1`
77			`cld fr29,r0`
78			`.endm`
79
80			`.extern cyg_instrument`
81
82			`##-----------------------------------------------------------------------------`
83			`## Hardware supplied vectors`
84
85			`.macro cpu_vector vsr_nr`
86			`setsr bs`
87			`clrsr rs0`
88			`clrsr rs1`
89			`nop`
90			`push r8`
91			`brad __exc_trampoline`
92			`ld r8,#\vsr_nr`
93			`.endm`
94
95			`##==========================================================================`
96			`## Hardware exception vectors.`
97			`##`
98			`.section ".vectors","ax"`
99			`.global reset_vector`
100			`reset_vector:`
101			`ldw r0,#_start`
102			`jmpd r0`
103			`nop`
104
105			`# 0x20 - FIQ`
106			`.p2align 5`
107			`cpu_vector 0`
108
109			`# 0x40 - IRQ`
110			`.p2align 5`
111			`cpu_vector 1`
112
113			`# 0x50 - COP`
114			`.p2align 4`
115			`cpu_vector 2`
116
117			`# 0x60 - DABRT`
118			`.p2align 4`
119			`cpu_vector 3`
120
121			`# 0x70 - IABRT`
122			`.p2align 4`
123			`cpu_vector 4`
124
125			`# 0x80 - PRIV`
126			`.p2align 4`
127			`cpu_vector 5`
128
129			`# 0xA0 - UNIMPL`
130			`.p2align 5`
131			`cpu_vector 6`
132
133			`# 0xC0 - TRACE`
134			`.p2align 5`
135			`cpu_vector 7`
136
137			`# 0x100 - SWI 0`
138			`.p2align 6`
139			`cpu_vector 8`
140
141			`# SWI 1`
142			`.p2align 4`
143			`cpu_vector 8`
144
145			`# SWI 2`
146			`.p2align 4`
147			`cpu_vector 8`
148
149			`# SWI 3`
150			`.p2align 4`
151			`cpu_vector 8`
152
153			`# SWI 4`
154			`.p2align 4`
155			`cpu_vector 8`
156
157			`# SWI 5`
158			`.p2align 4`
159			`cpu_vector 8`
160
161			`# SWI 6`
162			`.p2align 4`
163			`cpu_vector 8`
164
165			`# SWI 7`
166			`.p2align 4`
167			`cpu_vector 8`
168
169			`# SWI 8`
170			`.p2align 4`
171			`cpu_vector 8`
172
173			`# SWI 9`
174			`.p2align 4`
175			`cpu_vector 8`
176
177			`# SWI 10`
178			`.p2align 4`
179			`cpu_vector 8`
180
181			`# SWI 11`
182			`.p2align 4`
183			`cpu_vector 8`
184
185			`# SWI 12`
186			`.p2align 4`
187			`cpu_vector 8`
188
189			`# SWI 13`
190			`.p2align 4`
191			`cpu_vector 8`
192
193			`# SWI 14`
194			`.p2align 4`
195			`cpu_vector 8`
196
197			`# SWI 15`
198			`.p2align 4`
199			`cpu_vector 8`
200
201			`__exc_trampoline:`
202			`push r8 // vsr number`
203			`sl2 r8 // offset into vsr table`
204			`ldw r8,@[r8 + 0]`
205			`jmpd r8`
206			`pop r8`
207
208			`##-----------------------------------------------------------------------------`
209			`## Startup code`
210
211			`.text`
212
213			`FUNC_START _start`
214			`# default vector table`
215			`ld r0,#0`
216			`ld vbr,r0`
217
218			`# ensure privileged mode with all bank1 register view`
219			`setsr pm`
220			`setsr bs`
221			`clrsr rs0`
222			`clrsr rs1`
223
224			`# Initialize hardware`
225			`hal_cpu_init`
226			`hal_diag_init`
227			`hal_memc_init`
228			`hal_cache_init`
229			`hal_timer_init`
230
231			`# load initial stack pointer`
232			`ldw sp,#__startup_stack`
233
234			`clrsr bs`
235			`nop`
236			`ldw sp,#__user_stack`
237			`setsr bs`
238			`nop`
239
240			`hal_mon_init`
241
242			`#ifdef CYG_HAL_STARTUP_ROM`
243			`# Copy data from ROM to RAM`
244
245			`.extern hal_copy_data`
246			`ldw r0,#hal_copy_data`
247			`jsrd r0`
248			`nop`
249			`#endif`
250
251			`# Zero BSS`
252
253			`.extern hal_zero_bss`
254			`ldw r0,#hal_zero_bss`
255			`jsrd r0`
256			`nop`
257
258			`# Call variant and platform HAL`
259			`# initialization routines.`
260
261			`.extern hal_variant_init`
262			`ldw r0,#hal_variant_init`
263			`jsrd r0`
264			`nop`
265
266			`.extern hal_platform_init`
267			`ldw r0,#hal_platform_init`
268			`jsrd r0`
269			`nop`
270
271			`# Call constructors`
272			`.extern cyg_hal_invoke_constructors`
273			`ldw r0,#cyg_hal_invoke_constructors`
274			`jsrd r0`
275			`nop`
276
277			`#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)`
278			`.extern initialize_stub`
279			`ldw r0,#initialize_stub`
280			`jsrd r0`
281			`nop`
282			`#endif`
283
284			`#if defined(CYGDBG_HAL_CALM32_DEBUG_GDB_CTRLC_SUPPORT)`
285			`.extern hal_ctrlc_isr_init`
286			`ldw r0,#hal_ctrlc_isr_init`
287			`jsrd r0`
288			`nop`
289			`#endif`
290
291			`# Call cyg_start`
292
293			`.extern cyg_start`
294			`#if 0`
295			`clrsr pm`
296			`nop`
297			`clrsr bs`
298			`nop`
299			`#endif`
300			`ld fp,sp`
301
302			`ldw lr,#_start`
303			`ldw r0,#cyg_start`
304			`jmpd r0`
305			`nop`
306			`FUNC_END _start`
307
308
309			`.macro switch_stack_and_save_regs tmpvar`
310			`// save vector number temporarily`
311			`push r9`
312			`ldw r9,#\tmpvar`
313			`ldw @[r9 + 0],r8`
314			`pop r9`
315
316			`// Make sure we use the gdb stack`
317			`ldw r8,#__GDB_stack`
318			`cmpu gt sp,r8`
319			`brtd 0f`
320			`nop`
321			`ldw r8,#__GDB_stack_base`
322			`cmpu gt sp,r8`
323			`brtd 1f`
324			`nop`
325			`0:`
326			`// need to switch stack`
327			`ld r8,sp`
328			`add r8,#4`
329			`ldw sp,#__GDB_stack`
330			`push r8`
331			`push r14`
332			`push r13`
333			`push r12`
334			`sub r8,#4`
335			`brad 2f`
336			`ldw r8,@[r8+0]`
337			`1:`
338			`// already using gdb stack`
339			`pop r8`
340			`// save bank 1 regs`
341			`push q3`
342			`2:`
343			`// save rest of bank1 regs`
344			`push q2`
345			`push q1`
346			`push q0`
347
348			`// save bank 0 regs`
349			`setsr rs1`
350			`nop`
351			`push q1`
352			`push q0`
353			`clrsr rs1`
354			`setsr rs0`
355			`nop`
356			`push q1`
357			`push q0`
358			`clrsr rs0`
359			`nop`
360			`// save special regs`
361			`ld r0,ssr_expt`
362			`push r0`
363			`ld r0,ssr_swi`
364			`push r0`
365			`ld r0,ssr_fiq`
366			`push r0`
367			`ld r0,ssr_irq`
368			`push r0`
369			`ld r0,spc_expt`
370			`push r0`
371			`ld r0,spc_swi`
372			`push r0`
373			`ld r0,spc_fiq`
374			`push r0`
375			`ld r0,spc_irq`
376			`push r0`
377			`ld r0,vbr`
378			`push r0`
379
380			`ldw r8,#\tmpvar`
381			`ldw r8,@[r8+0]`
382			`push r8`
383			`.endm`
384
385			`.macro restore_regs`
386			`// discard vector`
387			`pop r0`
388			`// restore special regs`
389			`pop r0`
390			`ld vbr,r0`
391			`pop r0`
392			`ld spc_irq,r0`
393			`pop r0`
394			`ld spc_fiq,r0`
395			`pop r0`
396			`ld spc_swi,r0`
397			`pop r0`
398			`ld spc_expt,r0`
399			`pop r0`
400			`ld ssr_irq,r0`
401			`pop r0`
402			`ld ssr_fiq,r0`
403			`pop r0`
404			`ld ssr_swi,r0`
405			`pop r0`
406			`ld ssr_expt,r0`
407			`// restore bank 0 regs`
408			`setsr rs1`
409			`nop`
410			`pop q0`
411			`pop q1`
412			`clrsr rs1`
413			`setsr rs0`
414			`nop`
415			`pop q0`
416			`pop q1`
417			`clrsr rs0`
418			`nop`
419			`// restore bank 1 regs`
420			`pop q0`
421			`pop q1`
422			`pop q2`
423			`pop q3`
424			`.endm`
425
426
427			`##-----------------------------------------------------------------------------`
428			`## Default exception VSR.`
429			`## Saves machine state and calls external handling code.`
430			`## On entry, the original R8 has been pushed on the stack and R8 now`
431			`## contains the vector number.`
432
433			`FUNC_START __default_exception_vsr`
434
435			`switch_stack_and_save_regs __expt_temp`
436
437			`// call exception handler`
438			`ldw r8,#cyg_hal_exception_handler`
439			`jsrd r8`
440			`ld r0,sp`
441
442			`restore_regs`
443
444			`ret_expt`
445			`nop`
446
447			`FUNC_END __default_exception_vsr`
448
449			`##-----------------------------------------------------------------------------`
450			`## Default swi VSR.`
451			`## Saves machine state and calls external handling code.`
452			`## On entry, the original R8 has been pushed on the stack and R8 now`
453			`## contains the vector number.`
454
455			`FUNC_START __default_swi_vsr`
456
457			`switch_stack_and_save_regs __swi_temp`
458
459			`// call exception handler`
460			`ldw r8,#cyg_hal_exception_handler`
461			`jsrd r8`
462			`ld r0,sp`
463
464			`restore_regs`
465
466			`ret_swi`
467			`nop`
468
469			`FUNC_END __default_swi_vsr`
470
471			`##------------------------------------------------------------------------------`
472			`## Default interrupt VSR.`
473			`## Saves machine state and calls appropriate ISR. When done, calls`
474			`## interrupt_end() to finish up and possibly reschedule.`
475
476			`FUNC_START __default_fiq_vsr`
477			`switch_stack_and_save_regs __fiq_temp`
478
479			`ldw r8,#hal_interrupt_data`
480			`ldw r1,@[r8 + 0]`
481			`ldw r8,#hal_interrupt_handlers`
482			`ldw r8,@[r8 + 0]`
483
484			`// call fiq handler`
485			`jsrd r8`
486			`ld r0,#0`
487
488			`restore_regs`
489
490			`ret_fiq`
491			`nop`
492			`FUNC_END __default_fiq_vsr`
493
494			`FUNC_START __default_irq_vsr`
495			`switch_stack_and_save_regs __irq_temp`
496
497			`ldw r8,#hal_interrupt_data`
498			`ldw r1,@[r8 + 4]`
499			`ldw r8,#hal_interrupt_handlers`
500			`ldw r8,@[r8 + 4]`
501
502			`// call fiq handler`
503			`jsrd r8`
504			`ld r0,#1`
505
506			`restore_regs`
507
508			`ret_irq`
509			`nop`
510			`FUNC_END __default_irq_vsr`
511
512			`##-----------------------------------------------------------------------------`
513			`## Execute pending DSRs on the interrupt stack with interrupts enabled.`
514			`## Note: this can only be called from code running on a thread stack`
515
516			`#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
517			`.extern cyg_interrupt_call_pending_DSRs`
518
519			`FUNC_START hal_interrupt_stack_call_pending_DSRs`
520			`FUNC_END hal_interrupt_stack_call_pending_DSRs`
521			`#endif`
522
523			`##-----------------------------------------------------------------------------`
524			`## Short circuit in case any code tries to use "__gccmain()"`
525
526			`FUNC_START __gccmain`
527			`jmpd lr`
528			`nop`
529			`FUNC_END __gccmain`
530
531			`##-----------------------------------------------------------------------------`
532			`## Interrupt Stack.`
533			`## Used during intialization and for executing ISRs.`
534
535			`.section ".bss"`
536
537			`.balign 16`
538			`.global cyg_interrupt_stack_base`
539			`cyg_interrupt_stack_base:`
540			`__interrupt_stack_base:`
541			`.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE`
542			`.byte 0`
543			`.endr`
544			`.balign 16`
545			`.global cyg_interrupt_stack`
546			`cyg_interrupt_stack:`
547			`__interrupt_stack:`
548
549			`.long 0`
550
551			`#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS`
552			`.balign 16`
553			`__GDB_stack_base:`
554			`.rept 0x400`
555			`.byte 0`
556			`.endr`
557			`__GDB_stack:`
558			`.long 0`
559			`#endif`
560			`.balign 16`
561			`__startup_stack_base:`
562			`#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
563			`.rept 512`
564			`#else`
565			`.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE`
566			`#endif`
567			`.byte 0`
568			`.endr`
569			`.balign 16`
570			`__startup_stack:`
571			`.long 0`
572
573			`.balign 16`
574			`__user_stack_base:`
575			`#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
576			`.rept 512`
577			`#else`
578			`.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE`
579			`#endif`
580			`.byte 0`
581			`.endr`
582			`.balign 16`
583			`__user_stack:`
584			`.long 0`
585
586			`__expt_temp:`
587			`.long 0`
588			`__swi_temp:`
589			`.long 0`
590			`__irq_temp:`
591			`.long 0`
592			`__fiq_temp:`
593			`.long 0`
594
595
596			`##-----------------------------------------------------------------------------`
597			`## VSR table.`
598			`## The main interrupt code indirects through here to find the VSR`
599			`## to execute for each architecture defined interrupt.`
600			`## This is only used for simulated targets, on real targets a fixed location VSR`
601			`## table is now allocated at 0x80000100.`
602
603			`#ifndef CYG_HAL_CALM32_VSR_TABLE_DEFINED`
604
605			`## .section ".vsr_table","a"`
606
607			`.data`
608
609			`.globl hal_vsr_table`
610			`hal_vsr_table:`
611			`.long __default_fiq_vsr // FIQ`
612			`.long __default_irq_vsr // IRQ`
613			`.long __default_exception_vsr // COP`
614			`.long __default_exception_vsr // DABRT`
615			`.long __default_exception_vsr // IABRT`
616			`.long __default_exception_vsr // PRIV`
617			`.long __default_exception_vsr // UNIMPL`
618			`.long __default_exception_vsr // TRACE`
619			`.long __default_swi_vsr // SWI`
620			`#endif`
621
622			`.balign 16`
623			`#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT`
624			`## Vectors used to communicate between eCos and ROM environments`
625			`.globl hal_virtual_vector_table`
626			`hal_virtual_vector_table:`
627			`.rept 64`
628			`.long 0`
629			`.endr`
630			`#endif`
631
632			`#------------------------------------------------------------------------------`
633			`# Interrupt vector tables.`
634			`# These tables contain the isr, data and object pointers used to deliver`
635			`# interrupts to user code.`
636			`# hal_interrupt_level contains the interrupt level set by`
637			`# HAL_INTERRUPT_CONFIGURE().`
638			`# This is a default set that provide support only for the single external`
639			`# interrupt. Platforms or boards are expected to define their own versions`
640			`# of these if they have their own interrupt mappings.`
641
642			`#ifndef CYG_HAL_CALM32_ISR_TABLES_DEFINED`
643
644			`.extern hal_default_isr`
645
646			`.data`
647
648			`.globl hal_interrupt_handlers`
649			`hal_interrupt_handlers:`
650			`.long hal_default_isr`
651			`.long hal_default_isr`
652
653
654			`.globl hal_interrupt_data`
655			`hal_interrupt_data:`
656			`.long 0`
657			`.long 0`
658
659			`.globl hal_interrupt_objects`
660			`hal_interrupt_objects:`
661			`.long 0`
662			`.long 0`
663			`#endif`
664
665			`.data`
666			`.globl __break_inst_in_data`
667			`__break_inst_in_data:`
668			`.short 0x80e0`
669
670
671			`##-----------------------------------------------------------------------------`
672			`## end of vectors.S`
673
674