OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [coldfire/] [arch/] [current/] [src/] [coldfire_stub.c] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
//========================================================================
2
//
3
//      coldfire_stub.c
4
//
5
//      Helper functions for stub
6
//
7
//========================================================================
8
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
9
// -------------------------------------------                              
10
// This file is part of eCos, the Embedded Configurable Operating System.   
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under    
14
// the terms of the GNU General Public License as published by the Free     
15
// Software Foundation; either version 2 or (at your option) any later      
16
// version.                                                                 
17
//
18
// eCos is distributed in the hope that it will be useful, but WITHOUT      
19
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
20
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
21
// for more details.                                                        
22
//
23
// You should have received a copy of the GNU General Public License        
24
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
25
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
26
//
27
// As a special exception, if other files instantiate templates or use      
28
// macros or inline functions from this file, or you compile this file      
29
// and link it with other works to produce a work based on this file,       
30
// this file does not by itself cause the resulting work to be covered by   
31
// the GNU General Public License. However the source code for this file    
32
// must still be made available in accordance with section (3) of the GNU   
33
// General Public License v2.                                               
34
//
35
// This exception does not invalidate any other reasons why a work based    
36
// on this file might be covered by the GNU General Public License.         
37
// -------------------------------------------                              
38
// ####ECOSGPLCOPYRIGHTEND####                                              
39
//========================================================================
40
//#####DESCRIPTIONBEGIN####
41
//
42
// Author(s):     Enrico Piria
43
// Contributors:
44
// Date:          2005-25-06
45
// Purpose:       Helper functions for stub, generic to all ColdFire
46
//                processors.
47
//
48
//####DESCRIPTIONEND####
49
//========================================================================
50
 
51
#include <stddef.h>
52
#include <string.h>                     // memcpy, memset
53
 
54
#include <pkgconf/hal.h>
55
 
56
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
57
#include <cyg/hal/hal_stub.h>
58
 
59
#include <cyg/hal/hal_stub.h>
60
#include <cyg/hal/hal_arch.h>
61
#include <cyg/hal/hal_intr.h>
62
 
63
#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
64
#include <cyg/hal/dbg-threads-api.h>    // dbg_currthread_id
65
#endif
66
 
67
// Given a trap value TRAP, return the corresponding signal.
68
int __computeSignal (unsigned int trap_number)
69
{
70
    switch (trap_number)
71
    {
72
 
73
        case CYGNUM_HAL_VECTOR_BUSERR:
74
        case CYGNUM_HAL_VECTOR_ADDRERR:
75
            return SIGBUS;
76
 
77
        case CYGNUM_HAL_VECTOR_ILLINST:
78
        case CYGNUM_HAL_VECTOR_UNSUPINST:
79
            return SIGILL;
80
 
81
        case CYGNUM_HAL_VECTOR_ZERODIV:
82
        case CYGNUM_HAL_VECTOR_FP_BRANCH:
83
        case CYGNUM_HAL_VECTOR_FP_INEXACT:
84
        case CYGNUM_HAL_VECTOR_FP_ZERODIV:
85
        case CYGNUM_HAL_VECTOR_FP_UNDERFLOW:
86
        case CYGNUM_HAL_VECTOR_FP_OPERAND:
87
        case CYGNUM_HAL_VECTOR_FP_OVERFLOW:
88
        case CYGNUM_HAL_VECTOR_FP_NAN:
89
        case CYGNUM_HAL_VECTOR_FP_DENORM:
90
            // Although not quite accurate, use this signal also for
91
            // integer division.
92
            return SIGFPE;
93
 
94
        case CYGNUM_HAL_VECTOR_PRIVVIOLATION:
95
            return SIGILL;
96
        case CYGNUM_HAL_VECTOR_TRACE:
97
            // Instruction trace
98
            return SIGTRAP;
99
 
100
        case CYGNUM_HAL_VECTOR_L1010:
101
        case CYGNUM_HAL_VECTOR_L1111:
102
        case CYGNUM_HAL_VECTOR_UNINITINT:
103
        case CYGNUM_HAL_VECTOR_SPURINT:
104
            return SIGTRAP;
105
 
106
        case CYGNUM_HAL_VECTOR_TRAPFIRST ... CYGNUM_HAL_VECTOR_TRAPLAST:
107
            return SIGTRAP;
108
 
109
        case CYGNUM_HAL_VECTOR_AUTOVEC1 ... CYGNUM_HAL_VECTOR_AUTOVEC7:
110
        case CYGNUM_HAL_VECTOR_USERINTRFIRST ... CYGNUM_HAL_VECTOR_USERINTRLAST:
111
            // External interrupt
112
            return SIGINT;
113
 
114
        default:
115
            return SIGTERM;
116
    }
117
}
118
 
119
 
120
// Return the trap number corresponding to the last-taken trap.
121
int __get_trap_number (void)
122
{
123
    // The vector is not not part of the GDB register set so get it
124
    // directly from the saved context.
125
    return HAL_CF_EXCEPTION_VECTOR(_hal_registers->fmt_vec_word);
126
}
127
 
128
 
129
// Set the currently-saved pc register value to PC.
130
void set_pc (target_register_t pc)
131
{
132
    put_register (PC, pc);
133
}
134
 
135
 
136
// Return the offset of a register in the GDB_Registers structure.
137
static int reg_offset(regnames_t reg)
138
{
139
    switch(reg)
140
    {
141
        case D0 ... A7:
142
            return reg * 4;
143
 
144
        case SR:
145
            return offsetof(GDB_Registers, sr);
146
 
147
        default:
148
        case PC:
149
            return offsetof(GDB_Registers, pc);
150
    }
151
}
152
 
153
 
154
// Return the currently-saved value corresponding to register REG of
155
// the exception context.
156
target_register_t get_register(regnames_t reg)
157
{
158
    target_register_t val;
159
    int offset = reg_offset(reg);
160
 
161
    if (REGSIZE(reg) > sizeof(target_register_t))
162
        return -1;
163
 
164
    val = _registers[offset/sizeof(target_register_t)];
165
 
166
    return val;
167
}
168
 
169
 
170
// Store VALUE in the register corresponding to WHICH in the exception
171
// context.
172
void put_register(regnames_t which, target_register_t value)
173
{
174
    int offset = reg_offset(which);
175
 
176
    if (REGSIZE(which) > sizeof(target_register_t))
177
        return;
178
 
179
    _registers[offset/sizeof(target_register_t)] = value;
180
}
181
 
182
 
183
// Write the contents of register WHICH into VALUE as raw bytes. This
184
// is only used for registers larger than sizeof(target_register_t).
185
// Return non-zero if it is a valid register.
186
int get_register_as_bytes(regnames_t which, char *value)
187
{
188
    int offset = reg_offset(which);
189
 
190
    memcpy (value, (char *)_registers + offset, REGSIZE(which));
191
    return 1;
192
}
193
 
194
 
195
// Alter the contents of saved register WHICH to contain VALUE. This
196
// is only used for registers larger than sizeof(target_register_t).
197
// Return non-zero if it is a valid register.
198
int put_register_as_bytes(regnames_t which, char *value)
199
{
200
    int offset = reg_offset(which);
201
 
202
    memcpy ((char *)_registers + offset, value, REGSIZE(which));
203
    return 1;
204
}
205
 
206
 
207
// ---------------------------------------------------------------------
208
// Single-step support
209
 
210
// Set things up so that the next user resume will execute one instruction.
211
// This may be done by setting breakpoints or setting a single step flag
212
// in the saved user registers, for example.
213
 
214
#define SR_TRACE 0x8000
215
 
216
void __single_step(void)
217
{
218
    target_register_t sr = get_register (SR);
219
 
220
    // Set trace flag in the exception context.
221
    sr |= SR_TRACE;
222
 
223
    put_register (SR, sr);
224
}
225
 
226
 
227
// Clear the single-step state.
228
void __clear_single_step(void)
229
{
230
    target_register_t sr = get_register (SR);
231
 
232
    // Clear single-step flag in the exception context.
233
    sr &= ~SR_TRACE;
234
 
235
    put_register (SR, sr);
236
}
237
 
238
 
239
void __install_breakpoints(void)
240
{
241
    // NOP since single-step HW exceptions are used instead of
242
    // breakpoints.
243
}
244
 
245
 
246
void __clear_breakpoints(void)
247
{
248
    // NOP since single-step HW exceptions are used instead of
249
    // breakpoints.
250
}
251
 
252
 
253
// If the breakpoint we hit is in the breakpoint() instruction, return a
254
// non-zero value.
255
int __is_breakpoint_function(void)
256
{
257
    return (get_register(PC) == (target_register_t) &CYG_LABEL_NAME(_breakinst));
258
}
259
 
260
 
261
// Skip the current instruction. Since this is only called by the
262
// stub when the PC points to a breakpoint or trap instruction,
263
// we can safely just skip 2.
264
void __skipinst(void)
265
{
266
    put_register (PC, get_register (PC) + HAL_BREAKINST_SIZE);
267
}
268
 
269
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.