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#ifndef CYGONCE_HAL_VAR_INTR_H
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#define CYGONCE_HAL_VAR_INTR_H
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//==========================================================================
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//
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// var_intr.h
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//
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// MCF5272 processor variant interrupt, exception and clock support
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//
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2006 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Enrico Piria
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// Contributors: Wade Jensen
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// Date: 2005-25-06
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// Purpose: Provide interrupt, exception and clock definitions specific
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// to the MCF5272 processor.
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// Usage: Included via "hal_intr.h". Do not use directly.
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//
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//####DESCRIPTIONEND####
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//========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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// Include any platform specific interrupt definitions.
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#include <cyg/hal/plf_intr.h>
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// Include for the device addresses (MCF5272_DEVS).
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#include <cyg/hal/var_arch.h>
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// Include for HAL I/O macros
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#include <cyg/hal/hal_io.h>
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// --------------------------------------------------------------------------
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// Interrupt controller management
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// This chip has a programmable interrupt vector base which is different
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// from the vector base register (VBR). All interrupts from the interrupt
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// controller are offset from the programmable interrupt vector register
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// (PIVR). However, the only legal value is 64.
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#define HAL_PROG_INT_VEC_BASE 64
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// Vector numbers defined by the interrupt controller.
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// These are all relative to the interrupt vector base number.
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#define CYGNUM_HAL_INTERRUPT_USR_SPURINT (0 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_EXTINT1 (1 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_EXTINT2 (2 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_EXTINT3 (3 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_EXTINT4 (4 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_TMR0 (5 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_TMR1 (6 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_TMR2 (7 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_TMR3 (8 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_UART1 (9 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_UART2 (10 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_PLIP (11 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_PLIA (12 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_USB0 (13 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_USB1 (14 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_USB2 (15 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_USB3 (16 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_USB4 (17 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_USB5 (18 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_USB6 (19 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_USB7 (20 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_DMA (21 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_ERX (22 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_ETX (23 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_ENTC (24 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_QSPI (25 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_EXTINT5 (26 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_EXTINT6 (27 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_SWTO (28 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_RES1 (29 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_RES2 (30 + HAL_PROG_INT_VEC_BASE)
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#define CYGNUM_HAL_INTERRUPT_RES3 (31 + HAL_PROG_INT_VEC_BASE)
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// -------------------------------------------------------------------------
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// Interrupt and exception vector table definitions. We need to redifine
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// CYGNUM_HAL_ISR_MIN because the first usable vector is 65
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#define CYGNUM_HAL_ISR_RANGE_DEFINED
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#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_EXTINT1
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#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_RES3
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#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
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// -------------------------------------------------------------------------
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// Spurious interrupt definition. The MCF5272 returns vector number 64,
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// instead of 24, for spurious interrupts
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#define CYGNUM_HAL_SPURIOUS_INTERRUPT CYGNUM_HAL_INTERRUPT_USR_SPURINT
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// --------------------------------------------------------------------------
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// Interrupt controller definitions.
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// Interrupt priority tables
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externC volatile cyg_uint8 cyg_hal_ILVL_table[CYGNUM_HAL_ISR_COUNT];
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externC volatile cyg_uint8 cyg_hal_IMASK_table[CYGNUM_HAL_ISR_COUNT];
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externC void hal_interrupt_set_level(int vector, int level);
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externC void hal_interrupt_mask(int vector);
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externC void hal_interrupt_unmask(int vector);
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// Mask the interrupt associated with the given vector.
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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hal_interrupt_mask(_vector_)
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// Unmask the interrupt associated with the given vector.
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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hal_interrupt_unmask(_vector_)
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// Set the priority level of an interrupt.
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _prilevel_ ) \
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hal_interrupt_set_level(_vector_, _prilevel_)
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// Acknowledge the interrupt by writing a 1 to the corresponding
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// interrupt pending bit. Write 0 to all other interrupt pending bits. Leave
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// all priority levels unchanged. Disable all interrupts while we access the
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// hardware registers.
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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CYG_MACRO_START \
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cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
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cyg_uint32 _icr = _vec_offset / 8; \
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cyg_uint32 _icr_msk = 0x80000000 >> ((_vec_offset % 8) * 4); \
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cyg_uint32 _icr_oldval; \
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CYG_INTERRUPT_STATE _intr_state; \
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\
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HAL_DISABLE_INTERRUPTS(_intr_state); \
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HAL_READ_UINT32(&MCF5272_DEVS->intc.icr[_icr], _icr_oldval); \
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HAL_WRITE_UINT32(&MCF5272_DEVS->intc.icr[_icr], \
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_icr_oldval & (_icr_msk | 0x77777777)); \
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HAL_RESTORE_INTERRUPTS(_intr_state); \
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CYG_MACRO_END
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// Set/clear the interrupt transition register bit. Disable all
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// interrupts while we access the hardware registers.
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _leveltriggered_, _up_ ) \
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CYG_MACRO_START \
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if (!(_leveltriggered_)) \
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{ \
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cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
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cyg_uint32 _itr_bit = 0x80000000 >> _vec_offset; \
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cyg_uint32 _pitr_oldval; \
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CYG_INTERRUPT_STATE _intr_state; \
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\
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HAL_DISABLE_INTERRUPTS(_intr_state); \
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HAL_READ_UINT32(&MCF5272_DEVS->intc.pitr, _pitr_oldval); \
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if (_up_) \
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{ \
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HAL_WRITE_UINT32(&MCF5272_DEVS->intc.pitr, _pitr_oldval | _itr_bit); \
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} \
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else \
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{ \
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HAL_WRITE_UINT32(&MCF5272_DEVS->intc.pitr, _pitr_oldval & (~_itr_bit)); \
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} \
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HAL_RESTORE_INTERRUPTS(_intr_state); \
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} \
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CYG_MACRO_END
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// --------------------------------------------------------------------------
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// Clock control
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// The MCF5272 has 4 timers, numbered 0...3. Define the timer number that we
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// want to use for the OS clock.
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#define CYGNUM_HAL_RTC_TIMER_NUM (3)
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// The vector used by the real-time clock
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#define CYGNUM_HAL_INTERRUPT_RTC (CYGNUM_HAL_INTERRUPT_TMR3)
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// Initialize the timer to generate an interrupt every 10 ms. Use the
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// system clock divided by 16 as the source. Using 10 as the prescaler
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// gives a 2.4 us counter. When this counter reaches _period_, generate
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// an interrupt.
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#define HAL_CLOCK_INITIALIZE(_period_) \
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CYG_MACRO_START \
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HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tmr, \
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0x0000); \
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HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].trr, \
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(_period_)); \
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HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn, 0); \
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HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].ter, 0x0003); \
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HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tmr, \
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(((10)-1) << MCF5272_TIMER_TMR_PS_BIT) | \
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(0 << MCF5272_TIMER_TMR_CE_BIT) | \
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(0 << MCF5272_TIMER_TMR_OM_BIT) | \
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(1 << MCF5272_TIMER_TMR_ORI_BIT) | \
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(0 << MCF5272_TIMER_TMR_FRR_BIT) | \
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(2 << MCF5272_TIMER_TMR_CLK_BIT) | \
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(1 << MCF5272_TIMER_TMR_RST_BIT)); \
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CYG_MACRO_END
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// We must clear the bit in the timer event register before we can get
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// another interrupt.
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#define HAL_CLOCK_RESET( _vector_, _period_ ) \
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CYG_MACRO_START \
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HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn, 0); \
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HAL_WRITE_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].ter, 0x0002); \
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CYG_MACRO_END
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// Read the current counter from the timer
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#define HAL_CLOCK_READ( _pvalue_ ) \
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CYG_MACRO_START \
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HAL_READ_UINT16(&MCF5272_DEVS->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn, \
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*(_pvalue_)); \
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CYG_MACRO_END
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// Measure clock latency
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#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
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#define HAL_CLOCK_LATENCY( _pvalue_ ) \
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CYG_MACRO_START \
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register cyg_int32 result; \
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HAL_CLOCK_READ( &result ); \
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*_pvalue_ = result - CYGNUM_HAL_RTC_PERIOD; \
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CYG_MACRO_END
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#endif
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// ---------------------------------------------------------------------------
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// End of var_intr.h
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#endif // ifndef CYGONCE_HAL_VAR_INTR_H
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