OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [cortexm/] [arch/] [current/] [src/] [cortexm_stub.c] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
/*==========================================================================
2
//
3
//      cortexm_stub.c
4
//
5
//      Cortex-M GDB stub support
6
//
7
//==========================================================================
8
// ####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 2008 Free Software Foundation, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later
16
// version.
17
//
18
// eCos is distributed in the hope that it will be useful, but WITHOUT
19
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
21
// for more details.
22
//
23
// You should have received a copy of the GNU General Public License
24
// along with eCos; if not, write to the Free Software Foundation, Inc.,
25
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
26
//
27
// As a special exception, if other files instantiate templates or use
28
// macros or inline functions from this file, or you compile this file
29
// and link it with other works to produce a work based on this file,
30
// this file does not by itself cause the resulting work to be covered by
31
// the GNU General Public License. However the source code for this file
32
// must still be made available in accordance with section (3) of the GNU
33
// General Public License v2.
34
//
35
// This exception does not invalidate any other reasons why a work based
36
// on this file might be covered by the GNU General Public License.
37
// -------------------------------------------
38
// ####ECOSGPLCOPYRIGHTEND####
39
//==========================================================================
40
//#####DESCRIPTIONBEGIN####
41
//
42
// Author(s):    nickg
43
// Date:         2008-07-30
44
//
45
//####DESCRIPTIONEND####
46
//
47
//========================================================================*/
48
 
49
#include <stddef.h>
50
 
51
#include <pkgconf/hal.h>
52
 
53
#ifdef CYGPKG_REDBOOT
54
#include <pkgconf/redboot.h>
55
#endif
56
 
57
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
58
 
59
#include <cyg/hal/hal_arch.h>
60
#include <cyg/hal/hal_intr.h>
61
#include <cyg/hal/hal_stub.h>
62
 
63
//==========================================================================
64
 
65
#ifndef FALSE
66
#define FALSE 0
67
#define TRUE  1
68
#endif
69
 
70
#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
71
#include <cyg/hal/dbg-threads-api.h>    // dbg_currthread_id
72
#endif
73
 
74
//==========================================================================
75
/* Given a trap value TRAP, return the corresponding signal. */
76
 
77
int __computeSignal (unsigned int trap_number)
78
{
79
    switch (trap_number)
80
    {
81
    case CYGNUM_HAL_VECTOR_BUS_FAULT:      // Fall through
82
    case CYGNUM_HAL_VECTOR_MEMORY_MAN:     // Fall through
83
        return SIGBUS;
84
    case CYGNUM_HAL_VECTOR_NMI:
85
    case CYGNUM_HAL_VECTOR_SYS_TICK:
86
        return SIGINT;
87
    default:
88
        return SIGTRAP;
89
    }
90
}
91
 
92
 
93
//==========================================================================
94
/* Return the trap number corresponding to the last-taken trap. */
95
 
96
int __get_trap_number (void)
97
{
98
    // The vector is not not part of the GDB register set so get it
99
    // directly from the save context.
100
    return _hal_registers->u.exception.vector;
101
}
102
 
103
 
104
//==========================================================================
105
/* Set the currently-saved pc register value to PC. */
106
 
107
void set_pc (target_register_t pc)
108
{
109
    put_register (PC, pc);
110
}
111
 
112
//==========================================================================
113
// Calculate byte offset a given register from start of register save area.
114
 
115
static int
116
reg_offset(regnames_t reg)
117
{
118
    int base_offset;
119
 
120
    if (reg < F0)
121
        return reg * 4;
122
 
123
    base_offset = 16 * 4;
124
 
125
    if (reg < FPS)
126
        return base_offset + ((reg - F0) * 12);
127
 
128
    base_offset += (8 * 12);
129
 
130
    if (reg <= PS)
131
        return base_offset + ((reg - FPS) * 4);
132
 
133
    return -1;  // Should never happen!
134
}
135
 
136
 
137
//==========================================================================
138
// Return the currently-saved value corresponding to register REG of
139
// the exception context.
140
 
141
target_register_t
142
get_register (regnames_t reg)
143
{
144
    target_register_t val;
145
    int offset = reg_offset(reg);
146
 
147
    if (REGSIZE(reg) > sizeof(target_register_t) || offset == -1)
148
        return -1;
149
 
150
    val = _registers[offset/sizeof(target_register_t)];
151
 
152
    return val;
153
}
154
 
155
//==========================================================================
156
// Store VALUE in the register corresponding to WHICH in the exception
157
// context.
158
 
159
void
160
put_register (regnames_t which, target_register_t value)
161
{
162
    int offset = reg_offset(which);
163
 
164
    if (REGSIZE(which) > sizeof(target_register_t) || offset == -1)
165
        return;
166
 
167
    _registers[offset/sizeof(target_register_t)] = value;
168
}
169
 
170
//==========================================================================
171
// Write the contents of register WHICH into VALUE as raw bytes. This
172
// is only used for registers larger than sizeof(target_register_t).
173
// Return non-zero if it is a valid register.
174
 
175
int
176
get_register_as_bytes (regnames_t which, char *value)
177
{
178
    int offset = reg_offset(which);
179
 
180
    if (offset != -1) {
181
        memcpy (value, (char *)_registers + offset, REGSIZE(which));
182
        return 1;
183
    }
184
    return 0;
185
}
186
 
187
//==========================================================================
188
// Alter the contents of saved register WHICH to contain VALUE. This
189
// is only used for registers larger than sizeof(target_register_t).
190
// Return non-zero if it is a valid register.
191
 
192
int
193
put_register_as_bytes (regnames_t which, char *value)
194
{
195
    int offset = reg_offset(which);
196
 
197
    if (offset != -1) {
198
        memcpy ((char *)_registers + offset, value, REGSIZE(which));
199
        return 1;
200
    }
201
    return 0;
202
}
203
 
204
//==========================================================================
205
// Single step the processor.
206
//
207
// We do this by setting the MON_STEP bit in the DEMCR. So long as we
208
// are in a DebugMonitor exception this will single step the CPU on
209
// return.
210
// We also need to block all pending interrupts by setting basepri
211
// before doing the step. Otherwise an interrupt may be delivered
212
// before the step happens, and may cause unpleasant things to happen.
213
 
214
cyg_uint32 __single_step_basepri = 0;
215
 
216
void __single_step (void)
217
{
218
    CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE;
219
    cyg_uint32 demcr;
220
 
221
    // Save basepri and set it to mask all interrupts.
222
    __single_step_basepri = _hal_registers->u.exception.basepri;
223
    _hal_registers->u.exception.basepri = CYGNUM_HAL_CORTEXM_PRIORITY_MAX;
224
 
225
    // Set MON_STEP
226
    HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
227
    demcr |= CYGARC_REG_DEBUG_DEMCR_MON_STEP;
228
    HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
229
 
230
    // Clear any bits set in DFSR
231
    base = CYGARC_REG_NVIC_BASE;
232
    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );
233
 
234
}
235
 
236
//==========================================================================
237
// Clear the single-step state.
238
 
239
void __clear_single_step (void)
240
{
241
    CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE;
242
    cyg_uint32 demcr;
243
 
244
    // Restore basepri
245
    _hal_registers->u.exception.basepri = __single_step_basepri;
246
 
247
    // Clear MON_STEP
248
    HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
249
    demcr &= ~CYGARC_REG_DEBUG_DEMCR_MON_STEP;
250
    HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
251
 
252
    // Clear any bits set in DFSR
253
    base = CYGARC_REG_NVIC_BASE;
254
    HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_DFSR, 0xFFFFFFFF );
255
}
256
 
257
//==========================================================================
258
 
259
void __install_breakpoints (void)
260
{
261
    __install_breakpoint_list();
262
}
263
 
264
//--------------------------------------------------------------------------
265
 
266
void __clear_breakpoints (void)
267
{
268
    __clear_breakpoint_list();
269
}
270
 
271
//--------------------------------------------------------------------------
272
/* If the breakpoint we hit is in the breakpoint() instruction, return a
273
   non-zero value. */
274
 
275
int
276
__is_breakpoint_function ()
277
{
278
    return get_register (PC) == (target_register_t)&_breakinst;
279
}
280
 
281
 
282
//--------------------------------------------------------------------------
283
/* Skip the current instruction.  Since this is only called by the
284
   stub when the PC points to a breakpoint or trap instruction,
285
   we can safely just skip 2. */
286
 
287
void __skipinst (void)
288
{
289
    unsigned long pc = get_register(PC);
290
 
291
    pc += 2;
292
 
293
    put_register(PC, pc);
294
}
295
 
296
//==========================================================================
297
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.