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//==========================================================================
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//
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// twr_k60n512_misc.c
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//
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// Cortex-M4 TWR-K60N512 EVAL HAL functions
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2011 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): ilijak
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// Contributor(s):
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// Date: 2011-02-05
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <pkgconf/hal_cortexm.h>
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#include <pkgconf/hal_cortexm_kinetis.h>
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#include <pkgconf/hal_cortexm_kinetis_twr_k60n512.h>
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#ifdef CYGPKG_KERNEL
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#include <pkgconf/kernel.h>
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#endif
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#include <cyg/infra/diag.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/hal/hal_arch.h> // HAL header
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#include <cyg/hal/hal_intr.h> // HAL header
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static inline void hal_gpio_init(void);
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// DATA and BSS locations
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__externC cyg_uint32 __ram_data_start;
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__externC cyg_uint32 __ram_data_end;
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__externC cyg_uint32 __rom_data_start;
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__externC cyg_uint32 __sram_data_start;
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__externC cyg_uint32 __sram_data_end;
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__externC cyg_uint32 __srom_data_start;
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__externC cyg_uint32 __bss_start;
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__externC cyg_uint32 __bss_end;
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//==========================================================================
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// System init
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//
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// This is run to set up the basic system, including GPIO setting,
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// clock feeds, power supply, and memory initialization. This code
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// runs before the DATA is copied from ROM and the BSS cleared, hence
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// it cannot make use of static variables or data tables.
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__externC void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
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hal_system_init( void )
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{
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#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_SRAM)
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hal_wdog_disable();
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hal_gpio_init();
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hal_start_clocks();
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#endif
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#if defined(CYG_HAL_STARTUP_SRAM) && !defined(CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED)
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// Note: For CYG_HAL_STARTUP_SRAM, the SRAM_L bank simulates ROM
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// Relocate data from ROM to RAM
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{
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register cyg_uint32 *ram_p, *rom_p;
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for( ram_p = &__ram_data_start, rom_p = &__rom_data_start;
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ram_p < &__ram_data_end;
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ram_p++, rom_p++ )
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*ram_p = *rom_p;
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}
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// Relocate data from ROM to SRAM
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{
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register cyg_uint32 *ram_p, *sram_p;
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for( ram_p = &__sram_data_start, sram_p = &__srom_data_start;
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ram_p < &__sram_data_end;
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ram_p++, sram_p++ )
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*ram_p = *sram_p;
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}
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#endif
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}
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//===========================================================================
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// hal_gpio_init
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//===========================================================================
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static inline void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
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hal_gpio_init(void)
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{
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cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
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cyghwr_hal_kinetis_mpu_t *mpu_p = CYGHWR_HAL_KINETIS_MPU_P;
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// Enable clocks on all ports.
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sim_p->scgc1 = CYGHWR_HAL_KINETIS_SIM_SCGC1_ALL_M;
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sim_p->scgc2 = CYGHWR_HAL_KINETIS_SIM_SCGC2_ALL_M;
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sim_p->scgc3 = CYGHWR_HAL_KINETIS_SIM_SCGC3_ALL_M;
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sim_p->scgc4 = CYGHWR_HAL_KINETIS_SIM_SCGC4_ALL_M;
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sim_p->scgc5 = CYGHWR_HAL_KINETIS_SIM_SCGC5_ALL_M;
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sim_p->scgc6 = CYGHWR_HAL_KINETIS_SIM_SCGC6_ALL_M;
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sim_p->scgc7 = CYGHWR_HAL_KINETIS_SIM_SCGC7_ALL_M;
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// Disable MPU
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mpu_p->cesr = 0;
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}
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//==========================================================================
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__externC void hal_platform_init( void )
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{
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}
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//==========================================================================
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#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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#include CYGHWR_MEMORY_LAYOUT_H
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//--------------------------------------------------------------------------
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// Accesses to areas not backed by real devices or memory can cause
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// the CPU to hang.
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//
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// The following table defines the memory areas that GDB is allowed to
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// touch. All others are disallowed.
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// This table needs to be kept up to date with the set of memory areas
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// that are available on the board.
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static struct {
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CYG_ADDRESS start; // Region start address
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CYG_ADDRESS end; // End address (last byte)
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} hal_data_access[] =
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{
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{ CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // Main RAM
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#ifdef CYGMEM_REGION_sram
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{ CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM
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#endif
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#ifdef CYGMEM_REGION_flash
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{ CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash
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#endif
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#ifdef CYGMEM_REGION_rom
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{ CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash
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#endif
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{ 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals
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{ 0x40000000, 0x60000000-1 }, // Chip specific peripherals
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};
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__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count )
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{
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int i;
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for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) {
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if( (addr >= hal_data_access[i].start) &&
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(addr+count) <= hal_data_access[i].end)
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return true;
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}
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return false;
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}
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#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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//==========================================================================
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#ifdef CYGPKG_REDBOOT
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#include <redboot.h>
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#include CYGHWR_MEMORY_LAYOUT_H
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//--------------------------------------------------------------------------
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// Memory layout
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//
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// We report the on-chip SRAM and external SRAM.
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void
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cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
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{
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switch (seg) {
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case 0:
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*start = (unsigned char *)CYGMEM_REGION_ram;
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*end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
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break;
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#ifdef CYGMEM_REGION_sram
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case 1:
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*start = (unsigned char *)CYGMEM_REGION_sram;
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*end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE);
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break;
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#endif
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default:
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*start = *end = NO_MEMORY;
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break;
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}
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} // cyg_plf_memory_segment()
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#endif // CYGPKG_REDBOOT
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//==========================================================================
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// EOF twr_k60n512_misc.c
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