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##==========================================================================
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##
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## hal_cortexm_kinetis.cdl
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##
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## Cortex-M Freescale Kinetis variant HAL configuration data
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##
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##==========================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 2010, 2011 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##==========================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): Ilija Kocho
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## Date: 2010-12-05
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##
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######DESCRIPTIONEND####
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##
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##==========================================================================
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cdl_package CYGPKG_HAL_CORTEXM_KINETIS {
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display "Freescale Kinetis Cortex-M4 Variant"
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parent CYGPKG_HAL_CORTEXM
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hardware
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include_dir cyg/hal
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define_header hal_cortexm_kinetis.h
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description "
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This package provides generic support for the Freescale Cortex-M4
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based Kinetis microcontroller family.
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It is also necessary to select a variant and platform HAL package."
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compile hal_diag.c kinetis_misc.c kinetis_clocking.c
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implements CYGINT_HAL_DEBUG_GDB_STUBS
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implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
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requires { CYGHWR_HAL_CORTEXM == "M4" }
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define_proc {
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puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H "
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puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H "
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}
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cdl_component CYGHWR_HAL_CORTEXM_KINETIS {
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display "Kinetis part"
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flavor data
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calculated { "MK" . CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM .
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(CYGHWR_HAL_CORTEXM_KINETIS_FPU ? "F" : "D") .
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(CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM ? "X" : "N") .
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CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME }
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description "
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Kinetis family has several sub-families, with various peripheral
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sets and CPU options. Each sub-family consists of several
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members differing by sizes of on-chip FLASH and SRAM. This
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control, enables the user to build Kinetis member part and so
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tailor HAL for a specific microcontroller by selection of
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microcontroller's properties such as microcontroller sub-family,
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memory options, etc."
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cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SUBFAM {
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display "Sub-family"
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flavor data
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default_value { 60 }
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legal_values { 10 20 30 40 50 60 70 }
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description "
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Kinetis family consists of several sub-families differing by
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features and CPU power."
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}
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cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FPU {
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display "Floating Point Unit option"
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implements CYGINT_HAL_CORTEXM_FPU
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flavor bool
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default_value { 0 }
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description "Select whether the chip has Floating Point Unit."
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}
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cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME {
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display "Flash name segment"
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flavor data
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default_value { 512 }
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legal_values { 32 64 96 128 256 512 "1M0" }
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description "
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Flash size is represented in part name encoded as KiB
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(e.g. 512) or MiB (e.g. 1M0)."
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}
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cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM {
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display "FlexNVM option"
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flavor bool
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default_value { 0 }
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description "Select whether the chip has FlexNVM."
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}
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}
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cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
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display "CPU exception priority level bits"
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flavor data
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default_value 4
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description "
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This option defines the number of bits used to encode the
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exception priority levels that this variant of the Cortex-M
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CPU implements."
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}
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cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING {
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display "Clocking"
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flavor data
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no_define
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calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG
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description "Configure system clock and subsystem clocking."
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cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP {
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display "System frequency clock setpoint"
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flavor data
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legal_values 32768 to 220000000
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default_value 96000000
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description "Desired system clock frequency"
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}
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script kinetis_clocking.cdl
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}
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cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
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display "Clock interrupt ISR priority"
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flavor data
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calculated CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP
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description "Set clock ISR priority. Default setting is lowest priority."
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}
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cdl_component CYGNUM_HAL_RTC_CONSTANTS {
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display "Real-time clock constants"
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flavor none
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no_define
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cdl_option CYGNUM_HAL_RTC_NUMERATOR {
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display "Real-time clock numerator"
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flavor data
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default_value 1000000000
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}
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cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
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display "Real-time clock denominator"
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flavor data
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default_value 100
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}
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cdl_option CYGNUM_HAL_RTC_PERIOD {
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display "Real-time clock period"
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flavor data
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default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
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description "
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The period defined here is something of a fake, it is
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expressed in terms of a notional 1MHz clock. The value
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actually installed in the hardware is calculated from
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the current settings of the clock generation hardware."
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}
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}
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cdl_option CYG_HAL_STARTUP_VAR {
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display "By variant"
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flavor data
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parent CYG_HAL_STARTUP_ENV
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default_value {
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(CYG_HAL_STARTUP_PLF) && (CYG_HAL_STARTUP_PLF!="ByVariant") ?
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"ByPlatform" : "ROM" }
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legal_values { "ROM" "SRAM" }
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active_if ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant"))
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description "
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'ROM' startup builds a stand-alone application which will
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be placed into flash. SRAM startup builds application
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intended for loading in on-chip SRAM by means of JTAG/SWD.
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Note: Variant Startup Type can be overriden/overloaded by
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Platform Startup Type."
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}
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cdl_component CYG_HAL_STARTUP {
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display "Startup type calculator"
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flavor data
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parent CYG_HAL_STARTUP_ENV
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calculated {
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(CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ?
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CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR
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}
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no_define
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define -file system.h CYG_HAL_STARTUP
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description "
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Startup type defines what type of application shall be built.
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Startup type can be defined by variant (CYG_HAL_STARTUP_VAR)
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or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF
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is defined and not equal to 'ByVariant' then it shall
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override CYG_HAL_STARTUP_VAR."
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}
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cdl_component CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_CONF {
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display "FlexNVM configuration"
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flavor none
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no_define
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active_if CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM
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requires {
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CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <=
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CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
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}
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cdl_component CYGHWR_HAL_CORTEXM_KINETIS_EEE {
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display "Enhanced EEPROM (EEE)"
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flavor bool;
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cdl_option CYGHWR_HAL_KINETIS_EEE_SIZE {
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display "EEE Size \[Bytes\]"
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flavor data
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legal_values { 32 64 128 256 512 1024 2048 4096 }
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default_value 4096
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}
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cdl_component CYGHWR_HAL_KINETIS_EEE_SPLIT {
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display "EEE Split ratio"
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flavor data
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legal_values { 0 2 4 8 }
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default_value 0
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description "
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Enhanced EEPROM is split in two partitions that are
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represented by separate sections in MLT files.
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The split, CYGHWR_HAL_KINETIS_EEE_SPLIT, represents
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partition size ratio where EEE0 partition size is
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1/CYGHWR_HAL_KINETIS_EEE_SPLIT of EEE size, and EEE1
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is the rest. As a special arrangement
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(CYGHWR_HAL_KINETIS_EEE_SPLIT == 0) is a PHONY, where
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split equals 2 but in MLT files whole EEE is counted
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as a single section."
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cdl_option CYGHWR_HAL_KINETIS_EEE0_SIZE {
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display "e_eeprom0 section size \[Bytes\]"
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flavor data
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calculated { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 ?
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CYGHWR_HAL_KINETIS_EEE_SIZE /
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CYGHWR_HAL_KINETIS_EEE_SPLIT :
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CYGHWR_HAL_KINETIS_EEE_SIZE }
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}
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cdl_option CYGHWR_HAL_KINETIS_EEE1_SIZE {
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display "e_eeprom1 section size \[Bytes\]"
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flavor data
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active_if { CYGHWR_HAL_KINETIS_EEE_SPLIT > 0 }
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calculated { CYGHWR_HAL_KINETIS_EEE_SIZE -
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CYGHWR_HAL_KINETIS_EEE0_SIZE }
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}
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}
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cdl_option CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB {
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display "FlexNVM partition used for EEE \[KiB\]"
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flavor data
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default_value 32
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legal_values { 32 64 128 192 224 256 }
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}
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}
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cdl_component CYGHWR_HAL_KINETIS_FLEXNVM_DFLASH_SIZE {
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display "FlexNVM D Flash"
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flavor data
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active_if { CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB <
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CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB}
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calculated {
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1024 * ( CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB -
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CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)
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}
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}
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cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_RAM {
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display "Flexram ordinary RAM"
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flavor data
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active_if { !CYGHWR_HAL_CORTEXM_KINETIS_EEE }
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calculated CYGHWR_HAL_KINETIS_FLEXRAM_SIZE
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}
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cdl_component CYGHWR_HAL_KINETIS_FLEXRAM_SIZE {
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display "Flexram size"
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flavor data
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default_value 4096
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}
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307 |
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cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM_KIB {
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display "FlexNVM size \[KiB\]"
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flavor data
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calculated CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
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}
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}
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cdl_component CYGHWR_MEMORY_LAYOUT {
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display "Memory layout"
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flavor data
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no_define
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parent CYG_HAL_STARTUP_ENV
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calculated {
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(CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF :
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(CYG_HAL_STARTUP == "ROM" ) ? "kinetis_"
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. CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_rom" :
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(CYG_HAL_STARTUP == "SRAM") ? "kinetis_"
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. CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT . "_sram" :
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"undefined" }
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description "
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328 |
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Combination of 'Startup type' and 'Kinetis part'
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329 |
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produces the memory layout."
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330 |
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cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
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display "Memory layout linker script fragment"
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333 |
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flavor data
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334 |
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no_define
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335 |
|
|
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
|
336 |
|
|
calculated { "" }
|
337 |
|
|
}
|
338 |
|
|
|
339 |
|
|
cdl_option CYGHWR_MEMORY_LAYOUT_H {
|
340 |
|
|
display "Memory layout header file"
|
341 |
|
|
flavor data
|
342 |
|
|
no_define
|
343 |
|
|
define -file system.h CYGHWR_MEMORY_LAYOUT_H
|
344 |
|
|
calculated { "" }
|
345 |
|
|
}
|
346 |
|
|
}
|
347 |
|
|
|
348 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED {
|
349 |
|
|
display "Unified on chip SRAM region"
|
350 |
|
|
flavor bool
|
351 |
|
|
default_value { 1 }
|
352 |
|
|
description "
|
353 |
|
|
Kinetis have two equal SRAM banks SRAM_L and SRAM_U that
|
354 |
|
|
occupy consecutive memory blocks with \(possibility for
|
355 |
|
|
simultaneous\) access from on separate buses.
|
356 |
|
|
SRAM_L is placed below 0x20000000 and SRAM_U above 0x20000000.
|
357 |
|
|
This option provides for selection between memory layout with
|
358 |
|
|
single (unified) (S)RAM region and layout with two separate
|
359 |
|
|
(S)RAM regions."
|
360 |
|
|
}
|
361 |
|
|
|
362 |
|
|
cdl_option CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION {
|
363 |
|
|
display "Utilize \".kinetis_misc\" section for HAL"
|
364 |
|
|
flavor bool
|
365 |
|
|
default_value { CYG_HAL_STARTUP == "ROM" }
|
366 |
|
|
active_if { CYG_HAL_STARTUP == "ROM" }
|
367 |
|
|
description "
|
368 |
|
|
Kinetis use FLASH locations between 0x400 and 0x40F for FLASH
|
369 |
|
|
security configuration. This leaves FLASH area below 0x400
|
370 |
|
|
out of standard linker sections. Special section
|
371 |
|
|
\".kinetis_misc\" provides linker access to this area.
|
372 |
|
|
Setting this option instructs linker to place some HAL
|
373 |
|
|
(variant/platform) \"misc.\" functions in this area."
|
374 |
|
|
}
|
375 |
|
|
|
376 |
|
|
cdl_option CYGOPT_HAL_KINETIS_DIAG_IN_MISC_FLASH_SECTION {
|
377 |
|
|
display "HAL diag. in \".kinetis_misc\" section"
|
378 |
|
|
flavor bool
|
379 |
|
|
active_if CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION
|
380 |
|
|
default_value 0
|
381 |
|
|
description "
|
382 |
|
|
By default only misc. HAL functions are stored in
|
383 |
|
|
\".kinetis_misc\" section. In addition HAL diagnostc
|
384 |
|
|
functions may be placed as well."
|
385 |
|
|
}
|
386 |
|
|
|
387 |
|
|
cdl_component CYGHWR_HAL_KINETIS_MEMORY_RESOURCES {
|
388 |
|
|
display "On chip memory resources"
|
389 |
|
|
flavor none
|
390 |
|
|
no_define
|
391 |
|
|
description "
|
392 |
|
|
View and manage on-chip memory resources.
|
393 |
|
|
Output is used for naming of 'mlt' files."
|
394 |
|
|
|
395 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB {
|
396 |
|
|
display "On chip Flash option \[KiB\]"
|
397 |
|
|
flavor data
|
398 |
|
|
calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME == "1M0")
|
399 |
|
|
? 1024 : CYGHWR_HAL_CORTEXM_KINETIS_FLASH_NAME
|
400 |
|
|
}
|
401 |
|
|
}
|
402 |
|
|
|
403 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB {
|
404 |
|
|
display "Kinetis on chip SRAM size \[KiB\]"
|
405 |
|
|
flavor data
|
406 |
|
|
calculated {
|
407 |
|
|
(CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 1024 ||
|
408 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 512) ? 128 :
|
409 |
|
|
(CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 256) ? 64 :
|
410 |
|
|
(CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 128) ? 32 :
|
411 |
|
|
(CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 96 ||
|
412 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 64) ? 16 :
|
413 |
|
|
(CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB == 32) ? 8 :
|
414 |
|
|
"Unknown"
|
415 |
|
|
}
|
416 |
|
|
}
|
417 |
|
|
|
418 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT {
|
419 |
|
|
display "SRAM layout"
|
420 |
|
|
flavor data
|
421 |
|
|
no_define
|
422 |
|
|
calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_UNIFIED ?
|
423 |
|
|
"unisram" :
|
424 |
|
|
"sram2s"
|
425 |
|
|
}
|
426 |
|
|
}
|
427 |
|
|
|
428 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OC_MEM_LAYOUT {
|
429 |
|
|
display "On-chip memory layout"
|
430 |
|
|
flavor data
|
431 |
|
|
no_define
|
432 |
|
|
calculated {(CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM ? "flexnvm_": "flash_")
|
433 |
|
|
. CYGHWR_HAL_CORTEXM_KINETIS_SRAM_LAYOUT }
|
434 |
|
|
}
|
435 |
|
|
|
436 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLASH_SIZE {
|
437 |
|
|
display "Kinetis on chip FLASH size"
|
438 |
|
|
flavor data
|
439 |
|
|
calculated { CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB * 0x400 }
|
440 |
|
|
}
|
441 |
|
|
|
442 |
|
|
cdl_option CYGHWR_HAL_KINETIS_SRAM_SIZE {
|
443 |
|
|
display "Kinetis on chip SRAM size"
|
444 |
|
|
flavor data
|
445 |
|
|
calculated { CYGHWR_HAL_CORTEXM_KINETIS_SRAM_KIB * 0x400 }
|
446 |
|
|
}
|
447 |
|
|
|
448 |
|
|
cdl_option CYGHWR_HAL_KINETIS_SRAM_BANK_SIZE {
|
449 |
|
|
display "Kinetis onchip RAM bank size"
|
450 |
|
|
flavor data
|
451 |
|
|
calculated { CYGHWR_HAL_KINETIS_SRAM_SIZE/2 }
|
452 |
|
|
}
|
453 |
|
|
|
454 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLASH_SIZE {
|
455 |
|
|
display "Kinetis on chip FLASH size"
|
456 |
|
|
flavor data
|
457 |
|
|
calculated { (CYGHWR_HAL_CORTEXM_KINETIS_FLASH_KIB
|
458 |
|
|
- CYGHWR_HAL_CORTEXM_KINETIS_EEE_NVM_PART_KIB)* 0x400 }
|
459 |
|
|
}
|
460 |
|
|
|
461 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLEXNVM_FLEXRAM_SIZE {
|
462 |
|
|
display "Kinetis on chip FlexRAM size"
|
463 |
|
|
flavor data
|
464 |
|
|
active_if { CYGHWR_HAL_CORTEXM_KINETIS_FLEXNVM &
|
465 |
|
|
!CYGHWR_HAL_CORTEXM_KINETIS_EEE }
|
466 |
|
|
calculated { 4096 }
|
467 |
|
|
}
|
468 |
|
|
|
469 |
|
|
}
|
470 |
|
|
|
471 |
|
|
cdl_interface CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS {
|
472 |
|
|
display "Platform uses FlexBus"
|
473 |
|
|
flavor bool
|
474 |
|
|
description "
|
475 |
|
|
This interface will be implemented if the specific
|
476 |
|
|
controller being used provides FlexBus and if FlexBus is
|
477 |
|
|
used on target hardware"
|
478 |
|
|
}
|
479 |
|
|
|
480 |
|
|
cdl_component CYGPKG_HAL_CORTEXM_KINETIS_FLEXBUS {
|
481 |
|
|
display "FlexBus"
|
482 |
|
|
flavor bool
|
483 |
|
|
active_if CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
|
484 |
|
|
default_value CYGINT_HAL_CORTEXM_KINETIS_FLEXBUS
|
485 |
|
|
description "FlexBus provides access for external memory."
|
486 |
|
|
|
487 |
|
|
for { set ::chipsel 0 } { $::chipsel < 6 } { incr ::chipsel } {
|
488 |
|
|
|
489 |
|
|
cdl_interface CYGINT_HAL_KINETIS_FB_CS[set ::chipsel] {
|
490 |
|
|
display "Platform uses Chip select [set ::chipsel]"
|
491 |
|
|
flavor bool
|
492 |
|
|
description "
|
493 |
|
|
This interface will be implemented if the specific
|
494 |
|
|
controller being used provides chip select [set ::chipsel], and if
|
495 |
|
|
that chip select is used on target hardware."
|
496 |
|
|
}
|
497 |
|
|
|
498 |
|
|
cdl_component CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel] {
|
499 |
|
|
display "Chip select [set ::chipsel]"
|
500 |
|
|
flavor bool
|
501 |
|
|
active_if CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
|
502 |
|
|
default_value CYGINT_HAL_KINETIS_FB_CS[set ::chipsel]
|
503 |
|
|
description "
|
504 |
|
|
This option includes initialization data for
|
505 |
|
|
chip select [set ::chipsel]."
|
506 |
|
|
|
507 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PS {
|
508 |
|
|
display "Port size (encoded)"
|
509 |
|
|
flavor data
|
510 |
|
|
calculated ( \
|
511 |
|
|
CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 32 ? 0 : \
|
512 |
|
|
CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 8 ? 1 : \
|
513 |
|
|
CYGHWR_HAL_KINETIS_FB_CS[set ::chipsel]_CR_PSB == 16 ? 2 : 3)
|
514 |
|
|
}
|
515 |
|
|
}
|
516 |
|
|
}
|
517 |
|
|
}
|
518 |
|
|
|
519 |
|
|
cdl_component CYGHWR_HAL_KINETIS_FLASH_CONF {
|
520 |
|
|
display "Flash configuration field"
|
521 |
|
|
flavor none
|
522 |
|
|
no_define
|
523 |
|
|
|
524 |
|
|
active_if { CYG_HAL_STARTUP == "ROM" }
|
525 |
|
|
|
526 |
|
|
description "
|
527 |
|
|
The program flash memory contains a 16-byte flash
|
528 |
|
|
configuration field that stores default protection settings
|
529 |
|
|
(loaded on reset) and security information that allows the MCU to
|
530 |
|
|
restrict access to the flash module.
|
531 |
|
|
Note: Changing some values in Flash configuration field may make
|
532 |
|
|
flash inaccessible and disable further re-programming of the flash
|
533 |
|
|
permanently. Consult respective Kinetis' documentation before dealing
|
534 |
|
|
with the Flash configuration field. Default values are equal
|
535 |
|
|
to the factory values."
|
536 |
|
|
|
537 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_BACKDOOR_KEY {
|
538 |
|
|
display "Backdoor comparison key"
|
539 |
|
|
flavor data
|
540 |
|
|
default_value { "\{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff \}" }
|
541 |
|
|
}
|
542 |
|
|
|
543 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FPROT {
|
544 |
|
|
display "Program flash protection"
|
545 |
|
|
flavor data
|
546 |
|
|
default_value { "\{ 0xff, 0xff, 0xff, 0xff \}" }
|
547 |
|
|
}
|
548 |
|
|
|
549 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FSEC {
|
550 |
|
|
display "Flash security byte"
|
551 |
|
|
flavor data
|
552 |
|
|
default_value 0xfe
|
553 |
|
|
|
554 |
|
|
description "
|
555 |
|
|
Note: FSEC default value is deliberately set to
|
556 |
|
|
0xfe in order to disable chip lockout."
|
557 |
|
|
}
|
558 |
|
|
|
559 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FOPT {
|
560 |
|
|
display "Flash nonvolatile option byte"
|
561 |
|
|
flavor data
|
562 |
|
|
default_value 0xff
|
563 |
|
|
}
|
564 |
|
|
|
565 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FDPROT {
|
566 |
|
|
display "Data flash protection byte"
|
567 |
|
|
flavor data
|
568 |
|
|
default_value 0xff
|
569 |
|
|
}
|
570 |
|
|
|
571 |
|
|
cdl_option CYGHWR_HAL_KINETIS_FLASH_CONF_FEPROT {
|
572 |
|
|
display "EEPROM protection byte"
|
573 |
|
|
flavor data
|
574 |
|
|
default_value 0xff
|
575 |
|
|
}
|
576 |
|
|
}
|
577 |
|
|
|
578 |
|
|
for { set ::channel 0 } { $::channel < 6 } { incr ::channel } {
|
579 |
|
|
|
580 |
|
|
cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] {
|
581 |
|
|
display "Platform provides UART [set ::channel] HAL"
|
582 |
|
|
flavor bool
|
583 |
|
|
description "
|
584 |
|
|
This interface will be implemented if the specific
|
585 |
|
|
controller being used has on-chip UART [set ::channel],
|
586 |
|
|
and if that UART is accessible on the target hardware."
|
587 |
|
|
}
|
588 |
|
|
|
589 |
|
|
cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel]_RTSCTS {
|
590 |
|
|
display "Platform provides HAL for UART[set ::channel] hardware flow control."
|
591 |
|
|
flavor bool
|
592 |
|
|
description "
|
593 |
|
|
This interface will be implemented if the specific
|
594 |
|
|
on-chip UART [set ::channel] has RTS/CTS flow control
|
595 |
|
|
that is accessible on the target hardware."
|
596 |
|
|
}
|
597 |
|
|
}
|
598 |
|
|
|
599 |
|
|
cdl_interface CYGINT_HAL_DMA {
|
600 |
|
|
display "Platform uses DMA"
|
601 |
|
|
flavor bool
|
602 |
|
|
description "
|
603 |
|
|
This interface will be implemented if the specific
|
604 |
|
|
controller being used provides DMA and if DMA is
|
605 |
|
|
used on target hardware"
|
606 |
|
|
}
|
607 |
|
|
|
608 |
|
|
cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR {
|
609 |
|
|
display "Variant IRQ priority defaults"
|
610 |
|
|
no_define
|
611 |
|
|
flavor none
|
612 |
|
|
parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME
|
613 |
|
|
description "
|
614 |
|
|
Interrupt priorities defined by Kinetis variant"
|
615 |
|
|
script kinetis_irq_scheme.cdl
|
616 |
|
|
}
|
617 |
|
|
|
618 |
|
|
cdl_component CYGPKG_HAL_CORTEXM_KINETIS_OPTIONS {
|
619 |
|
|
display "Build options"
|
620 |
|
|
flavor none
|
621 |
|
|
no_define
|
622 |
|
|
description "
|
623 |
|
|
Package specific build options including control over
|
624 |
|
|
compiler flags used only in building this package."
|
625 |
|
|
|
626 |
|
|
cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_ADD {
|
627 |
|
|
display "Additional compiler flags"
|
628 |
|
|
flavor data
|
629 |
|
|
no_define
|
630 |
|
|
default_value { "" }
|
631 |
|
|
description "
|
632 |
|
|
This option modifies the set of compiler flags for
|
633 |
|
|
building the Kinetis variant HAL package. These flags
|
634 |
|
|
are used in addition to the set of global flags."
|
635 |
|
|
}
|
636 |
|
|
|
637 |
|
|
cdl_option CYGPKG_HAL_CORTEXM_KINETIS_CFLAGS_REMOVE {
|
638 |
|
|
display "Suppressed compiler flags"
|
639 |
|
|
flavor data
|
640 |
|
|
no_define
|
641 |
|
|
default_value { "" }
|
642 |
|
|
description "
|
643 |
|
|
This option modifies the set of compiler flags for
|
644 |
|
|
building the Kinetis variant HAL package. These flags
|
645 |
|
|
are removed from the set of global flags if present."
|
646 |
|
|
}
|
647 |
|
|
}
|
648 |
|
|
}
|
649 |
|
|
|
650 |
|
|
# EOF hal_cortexm_kinetis.cdl
|