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##==========================================================================
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##
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## kinetis_clocking.cdl
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##
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## Cortex-M Freescale Kinetis Clocking
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##
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##==========================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 2011 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##==========================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): Ilija Kocho
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## Date: 2011-10-19
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##
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######DESCRIPTIONEND####
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##
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##==========================================================================
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# cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLOCKING
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# display "Clocking"
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cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ {
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display "System frequency actual value"
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flavor data
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calculated {
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CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC ?
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CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC :
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CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC ?
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CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC :
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CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL ?
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CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV :
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CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL ?
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CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV :
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}
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description "Operating system clock frequency."
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}
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cdl_component CYGHWR_HAL_CORTEXM_KINETIS_MCG {
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display "MCG"
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flavor data
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no_define
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calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK . " " .
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((CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ+500000)/1000000) . "MHz, " . (
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(CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK") ?
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CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS :
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CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC)
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}
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description "Multipurpose Clock Generator"
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cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK {
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display "System clock source"
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flavor data
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default_value { "PLL" }
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legal_values {
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"PLL" "FLL" "EXT_REFCLK"
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}
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description "
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Select one of 3 options for MCG output clock:
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PLL or FLL oscillator or External reference clock."
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}
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cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT {
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display "EXT_REFCLK source clock settings"
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flavor none
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no_define
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active_if {
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(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK") ||
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(CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "EXT_REFCLK")
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}
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description "Set External Reference Clock frequency and type."
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cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS {
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display "Clock type"
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flavor data
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default_value { "OSC" }
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legal_values { "OSC" "XTAL" "RTC"}
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requires {
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(CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "OSC") implies
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(CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 50000000)
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}
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requires {
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(CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL") implies
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(((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 3000000) &&
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(CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 32000000)) ||
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((CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ >= 32000) &&
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(CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ <= 40000)))
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}
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requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
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implies (CYGHWR_HAL_CORTEXM_KINETIS_RTC == 1)
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}
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requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
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implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
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}
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requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "RTC")
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implies (CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ == 32768)
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}
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description "
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Ext reference can be External oscillator or a crystal
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for the on-chip oscillator or Real Time Clock."
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}
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cdl_option CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ {
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display "Clock frequency"
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flavor data
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legal_values 0 to 50000000
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default_value {
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is_active(CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ) ?
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CYGHWR_HAL_CORTEXM_KINETIS_PLF_XTAL_OR_OSC_FREQ :
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4000000
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}
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description "External oscillator or crystal reference in Hz."
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}
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cdl_option CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP {
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display "XTAL parallel C \[pF\]"
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flavor data
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active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS == "XTAL" }
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legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 }
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default_value 0
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description "
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The oscillator has 4 on-chip capacitors that combined
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produce capacitance in parallel to the crystal."
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}
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}
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cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL {
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display "FLL / PLL configuration"
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flavor none
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no_define
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description "
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PLL / FLL parameters are being calculated on a
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base of required system frequrncy and output as well as
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reference oscillator/frequency settings."
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cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP {
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display "PLL/FLL output frequency set point"
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flavor data
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legal_values 32768 to 220000000
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calculated CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ_SP
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description "Desired PLL output frequency."
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}
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cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC {
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display "Reference clock source for FLL or PLL"
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flavor data
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default_value { "EXT_REFCLK" }
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requires { (CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC == "INT_RC_32KHZ")
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implies (CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL")
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}
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legal_values { "INT_RC_32KHZ" "EXT_REFCLK" }
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description "
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PLL/FLL oscillators can use one of 3 clock
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references: External Reference Clock or Low (32768 Hz)
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or High (2MHz) Frequency Internal oscillator"
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}
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cdl_component CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ {
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display "Reference frequency."
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flavor data
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calculated { is_active (CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT) ?
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CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ :
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(CYGOPT_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REFSRC
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== "INT_RC_32KHZ" ? 32768 : 2000000 )
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}
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}
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cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_FLL {
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display "FLL oscillator"
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flavor none
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no_define
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active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ||
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CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" ||
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CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK"
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}
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cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE {
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display "Reference frequency range"
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flavor data
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legal_values 0 1 2
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calculated {
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CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ > 8000000 ? 2 :
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CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 1000000 ? 1 :
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((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ >= 32000) &&
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ <= 40000)) ? 0 :
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-1
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}
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}
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cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV {
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display "Calculated FLL divider"
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flavor data
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calculated {
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CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE >= 1 ?
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((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+32768*16) / (32768*32)) :
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ?
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((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ+16384) / 32768) : -1)
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}
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}
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cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG {
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display "FLL divider register value"
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| 241 |
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flavor data
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| 242 |
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legal_values 0 1 2 3 4 5 6 7
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default_value {
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| 244 |
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CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0 ?
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) :
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| 246 |
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) <= 5 ?
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| 247 |
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV/2) : 5
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}
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}
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cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS {
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display "DCO Range Select"
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| 253 |
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flavor data
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| 254 |
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legal_values 0 1 2 3
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default_value {
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| 256 |
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 80000000 ? 3 :
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| 257 |
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 60000000 ? 2 :
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP) >= 40000000 ? 1 : 0
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| 259 |
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}
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| 260 |
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}
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| 261 |
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cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 {
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| 263 |
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display "DCO max. frequency with 32768 reference"
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| 264 |
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flavor data
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| 265 |
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legal_values 0 0x80
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| 266 |
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default_value {
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| 267 |
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((CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 96000000) ||
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| 268 |
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 72000000) ||
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 48000000) ||
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| 270 |
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(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP == 24000000)) ?
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| 271 |
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0x80 : 0x00
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| 272 |
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}
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| 273 |
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}
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| 274 |
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| 275 |
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cdl_option CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT {
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| 276 |
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display "FLL factor"
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| 277 |
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flavor data
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| 278 |
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calculated {
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| 279 |
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(CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 == 0x80) ?
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| 280 |
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((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ? 732 :
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| 281 |
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(CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1464 :
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| 282 |
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(CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 2197 : 2929 ) :
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| 283 |
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((CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 0 ) ? 640 :
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| 284 |
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(CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 1 ) ? 1280 :
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| 285 |
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(CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS == 2 ) ? 1920 : 2560 )
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| 286 |
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}
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| 287 |
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}
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| 288 |
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| 289 |
|
|
cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN {
|
| 290 |
|
|
display "DCO input frequency"
|
| 291 |
|
|
flavor data
|
| 292 |
|
|
calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
|
| 293 |
|
|
( CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG == 0 ?
|
| 294 |
|
|
((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 1 : 32 ) :
|
| 295 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG *
|
| 296 |
|
|
((CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE == 0) ? 2 : 64)))
|
| 297 |
|
|
}
|
| 298 |
|
|
}
|
| 299 |
|
|
|
| 300 |
|
|
cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN_CHECK {
|
| 301 |
|
|
display "DCO input frequency check"
|
| 302 |
|
|
flavor data
|
| 303 |
|
|
no_define
|
| 304 |
|
|
legal_values { "OK" "NOK" "not applicable" }
|
| 305 |
|
|
calculated {
|
| 306 |
|
|
CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" ?
|
| 307 |
|
|
((CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) &&
|
| 308 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063) ?
|
| 309 |
|
|
"OK" : "NOK" ) :
|
| 310 |
|
|
"NotApplicable"
|
| 311 |
|
|
}
|
| 312 |
|
|
active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "FLL" }
|
| 313 |
|
|
requires {
|
| 314 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN >= 31250) &&
|
| 315 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN <= 39063)
|
| 316 |
|
|
}
|
| 317 |
|
|
}
|
| 318 |
|
|
|
| 319 |
|
|
cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV {
|
| 320 |
|
|
display "FLL output frequency actual value"
|
| 321 |
|
|
flavor data
|
| 322 |
|
|
calculated {CYGNUM_HAL_CORTEXM_KINETIS_MCG_DCO_IN *
|
| 323 |
|
|
CYGNUM_HAL_CORTEXM_MCG_DCO_FLL_FACT }
|
| 324 |
|
|
}
|
| 325 |
|
|
}
|
| 326 |
|
|
|
| 327 |
|
|
cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL {
|
| 328 |
|
|
display "PLL oscillator"
|
| 329 |
|
|
flavor none
|
| 330 |
|
|
no_define
|
| 331 |
|
|
active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "PLL" ||
|
| 332 |
|
|
CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK"
|
| 333 |
|
|
}
|
| 334 |
|
|
|
| 335 |
|
|
cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X {
|
| 336 |
|
|
display "Phase detector proposed input frequency"
|
| 337 |
|
|
no_define
|
| 338 |
|
|
flavor data
|
| 339 |
|
|
calculated {
|
| 340 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 180000000) ?
|
| 341 |
|
|
3800000 :
|
| 342 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP > 110000000) ?
|
| 343 |
|
|
3000000 :
|
| 344 |
|
|
!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 3) ? 2000000 :
|
| 345 |
|
|
!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 4) ? 2000000 :
|
| 346 |
|
|
!(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP % 5) ? 2500000 :
|
| 347 |
|
|
300000
|
| 348 |
|
|
}
|
| 349 |
|
|
}
|
| 350 |
|
|
|
| 351 |
|
|
cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV {
|
| 352 |
|
|
display "PLL External Reference Divider"
|
| 353 |
|
|
flavor data
|
| 354 |
|
|
legal_values 1 to 25
|
| 355 |
|
|
default_value {
|
| 356 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X ?
|
| 357 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
|
| 358 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ_X ) : -1
|
| 359 |
|
|
}
|
| 360 |
|
|
}
|
| 361 |
|
|
|
| 362 |
|
|
cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ {
|
| 363 |
|
|
display "Phase detector input frequency"
|
| 364 |
|
|
no_define
|
| 365 |
|
|
flavor data
|
| 366 |
|
|
legal_values 2000000 to 4000000
|
| 367 |
|
|
calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV ?
|
| 368 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
|
| 369 |
|
|
CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV) : -1
|
| 370 |
|
|
}
|
| 371 |
|
|
}
|
| 372 |
|
|
|
| 373 |
|
|
cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV {
|
| 374 |
|
|
display "VCO Divider"
|
| 375 |
|
|
flavor data
|
| 376 |
|
|
legal_values 24 to 55
|
| 377 |
|
|
default_value { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ ?
|
| 378 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_FREQ_SP /
|
| 379 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_PLL_INFREQ) : -1
|
| 380 |
|
|
}
|
| 381 |
|
|
}
|
| 382 |
|
|
|
| 383 |
|
|
cdl_option CYGNUM_HAL_CORTEXM_KINETIS_MCG_PLL_FREQ_AV {
|
| 384 |
|
|
display "PLL output frequency actual value"
|
| 385 |
|
|
flavor data
|
| 386 |
|
|
calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV ?
|
| 387 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
|
| 388 |
|
|
CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV *
|
| 389 |
|
|
CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV) : -1
|
| 390 |
|
|
}
|
| 391 |
|
|
}
|
| 392 |
|
|
}
|
| 393 |
|
|
}
|
| 394 |
|
|
|
| 395 |
|
|
cdl_component CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC {
|
| 396 |
|
|
display "Internal Reference Clock"
|
| 397 |
|
|
flavor data
|
| 398 |
|
|
calculated { CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI ? 2000000 : 32768 }
|
| 399 |
|
|
active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "INT_REFCLK" }
|
| 400 |
|
|
|
| 401 |
|
|
cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_INT_RC_HI {
|
| 402 |
|
|
display "Use highh frequency internal osc."
|
| 403 |
|
|
flavor bool
|
| 404 |
|
|
default_value 1
|
| 405 |
|
|
}
|
| 406 |
|
|
}
|
| 407 |
|
|
|
| 408 |
|
|
cdl_option CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC {
|
| 409 |
|
|
display "External Reference Clock"
|
| 410 |
|
|
flavor data
|
| 411 |
|
|
calculated CYGHWR_HAL_CORTEXM_KINETIS_MCG_REF_EXT_FREQ
|
| 412 |
|
|
active_if { CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK == "EXT_REFCLK" }
|
| 413 |
|
|
}
|
| 414 |
|
|
}
|
| 415 |
|
|
|
| 416 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_DIST {
|
| 417 |
|
|
display "Subsystem clocking"
|
| 418 |
|
|
flavor none
|
| 419 |
|
|
no_define
|
| 420 |
|
|
|
| 421 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS {
|
| 422 |
|
|
display "Peripheral bus"
|
| 423 |
|
|
flavor data
|
| 424 |
|
|
calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 425 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS
|
| 426 |
|
|
}
|
| 427 |
|
|
|
| 428 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX {
|
| 429 |
|
|
display "Frequency limit"
|
| 430 |
|
|
flavor data
|
| 431 |
|
|
default_value 50000000
|
| 432 |
|
|
}
|
| 433 |
|
|
|
| 434 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP {
|
| 435 |
|
|
display "Calculated value"
|
| 436 |
|
|
flavor data
|
| 437 |
|
|
default_value {
|
| 438 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
|
| 439 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX ?
|
| 440 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
|
| 441 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX
|
| 442 |
|
|
}
|
| 443 |
|
|
legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_MAX
|
| 444 |
|
|
}
|
| 445 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS {
|
| 446 |
|
|
display "Divider"
|
| 447 |
|
|
flavor data
|
| 448 |
|
|
legal_values 1 to 16
|
| 449 |
|
|
|
| 450 |
|
|
default_value { !(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
|
| 451 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP) ?
|
| 452 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 453 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP) :
|
| 454 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 455 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_PER_BUS_SP + 1)
|
| 456 |
|
|
}
|
| 457 |
|
|
}
|
| 458 |
|
|
}
|
| 459 |
|
|
|
| 460 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH {
|
| 461 |
|
|
display "Flash"
|
| 462 |
|
|
flavor data
|
| 463 |
|
|
calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 464 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH
|
| 465 |
|
|
}
|
| 466 |
|
|
|
| 467 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX {
|
| 468 |
|
|
display "Frequency limit"
|
| 469 |
|
|
flavor data
|
| 470 |
|
|
default_value 25000000
|
| 471 |
|
|
}
|
| 472 |
|
|
|
| 473 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP {
|
| 474 |
|
|
display "Calculated value"
|
| 475 |
|
|
flavor data
|
| 476 |
|
|
default_value {
|
| 477 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
|
| 478 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX ?
|
| 479 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
|
| 480 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX
|
| 481 |
|
|
}
|
| 482 |
|
|
legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_MAX
|
| 483 |
|
|
}
|
| 484 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH {
|
| 485 |
|
|
display "Divider"
|
| 486 |
|
|
flavor data
|
| 487 |
|
|
legal_values 1 to 16
|
| 488 |
|
|
|
| 489 |
|
|
default_value {
|
| 490 |
|
|
!(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
|
| 491 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP) ?
|
| 492 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 493 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP) :
|
| 494 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 495 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLASH_SP + 1)
|
| 496 |
|
|
}
|
| 497 |
|
|
}
|
| 498 |
|
|
}
|
| 499 |
|
|
|
| 500 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS {
|
| 501 |
|
|
display "Flex bus"
|
| 502 |
|
|
flavor data
|
| 503 |
|
|
calculated { CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 504 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS
|
| 505 |
|
|
}
|
| 506 |
|
|
|
| 507 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX {
|
| 508 |
|
|
display "Frequency limit"
|
| 509 |
|
|
flavor data
|
| 510 |
|
|
default_value 50000000
|
| 511 |
|
|
}
|
| 512 |
|
|
|
| 513 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP {
|
| 514 |
|
|
display "Calculated value"
|
| 515 |
|
|
flavor data
|
| 516 |
|
|
default_value {
|
| 517 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <=
|
| 518 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX ?
|
| 519 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ :
|
| 520 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX
|
| 521 |
|
|
}
|
| 522 |
|
|
legal_values 0 to CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_MAX
|
| 523 |
|
|
}
|
| 524 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS {
|
| 525 |
|
|
display "Divider"
|
| 526 |
|
|
flavor data
|
| 527 |
|
|
legal_values 1 to 16
|
| 528 |
|
|
|
| 529 |
|
|
default_value {
|
| 530 |
|
|
!(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ %
|
| 531 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP) ?
|
| 532 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 533 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP) :
|
| 534 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ /
|
| 535 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_FLEX_BUS_SP + 1)
|
| 536 |
|
|
}
|
| 537 |
|
|
}
|
| 538 |
|
|
}
|
| 539 |
|
|
|
| 540 |
|
|
|
| 541 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB {
|
| 542 |
|
|
display "USB clock"
|
| 543 |
|
|
flavor data
|
| 544 |
|
|
calculated { CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
|
| 545 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
|
| 546 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV
|
| 547 |
|
|
}
|
| 548 |
|
|
|
| 549 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX {
|
| 550 |
|
|
display "Frequency limit"
|
| 551 |
|
|
flavor data
|
| 552 |
|
|
default_value 48000000
|
| 553 |
|
|
}
|
| 554 |
|
|
|
| 555 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC {
|
| 556 |
|
|
display "Fractional Divider"
|
| 557 |
|
|
flavor data
|
| 558 |
|
|
legal_values 1 to 2
|
| 559 |
|
|
default_value {
|
| 560 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ <
|
| 561 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_MAX ? 1 :
|
| 562 |
|
|
((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN) >
|
| 563 |
|
|
(CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP * 4) ? 1 :
|
| 564 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN %
|
| 565 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP ? 2 : 1))
|
| 566 |
|
|
}
|
| 567 |
|
|
}
|
| 568 |
|
|
|
| 569 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV {
|
| 570 |
|
|
display "Divider"
|
| 571 |
|
|
flavor data
|
| 572 |
|
|
legal_values 1 to 8
|
| 573 |
|
|
default_value { !((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
|
| 574 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC) %
|
| 575 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) ?
|
| 576 |
|
|
(CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
|
| 577 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
|
| 578 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) :
|
| 579 |
|
|
((CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN *
|
| 580 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC /
|
| 581 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP) +1)
|
| 582 |
|
|
}
|
| 583 |
|
|
}
|
| 584 |
|
|
|
| 585 |
|
|
cdl_option CYGNUM_HAL_CORTEXM_KINETIS_CLK_USB_IN {
|
| 586 |
|
|
display "USB divider input frequency"
|
| 587 |
|
|
flavor data
|
| 588 |
|
|
calculated {
|
| 589 |
|
|
CYGNUM_HAL_CORTEXM_KINETIS_MCGOUT_FREQ
|
| 590 |
|
|
}
|
| 591 |
|
|
}
|
| 592 |
|
|
|
| 593 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_CLK_USB_SP {
|
| 594 |
|
|
display "Desired"
|
| 595 |
|
|
flavor data
|
| 596 |
|
|
calculated 48000000
|
| 597 |
|
|
}
|
| 598 |
|
|
}
|
| 599 |
|
|
|
| 600 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK {
|
| 601 |
|
|
display "Trace clock source"
|
| 602 |
|
|
flavor data
|
| 603 |
|
|
default_value { "CORE" }
|
| 604 |
|
|
legal_values { "CORE" "MCGOUT" }
|
| 605 |
|
|
|
| 606 |
|
|
}
|
| 607 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT {
|
| 608 |
|
|
display "Enable Trace Clock out"
|
| 609 |
|
|
flavor bool
|
| 610 |
|
|
default_value 0
|
| 611 |
|
|
}
|
| 612 |
|
|
}
|
| 613 |
|
|
|
| 614 |
|
|
cdl_interface CYGINT_HAL_CORTEXM_KINETIS_RTC {
|
| 615 |
|
|
}
|
| 616 |
|
|
|
| 617 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_KINETIS_RTC {
|
| 618 |
|
|
display "Real Time Clock"
|
| 619 |
|
|
flavor bool
|
| 620 |
|
|
default_value CYGINT_HAL_CORTEXM_KINETIS_RTC
|
| 621 |
|
|
|
| 622 |
|
|
|
| 623 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP {
|
| 624 |
|
|
display "RTC XTAL parallel C \[pF\]"
|
| 625 |
|
|
flavor data
|
| 626 |
|
|
legal_values { 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
|
| 627 |
|
|
30 32 }
|
| 628 |
|
|
default_value 0
|
| 629 |
|
|
description "
|
| 630 |
|
|
The Real Time Clock oscillator has 4 capacitors that
|
| 631 |
|
|
combined produce capacitance in parallel to the crystal."
|
| 632 |
|
|
}
|
| 633 |
|
|
}
|
| 634 |
|
|
|
| 635 |
|
|
# EOF kinetis_clocking.cdl
|
