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#ifndef CYGONCE_HAL_VAR_INTR_H
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#define CYGONCE_HAL_VAR_INTR_H
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//==========================================================================
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//
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// var_intr.h
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//
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// HAL Interrupt and clock assignments for Kinetis variants
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2011 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): ilijak
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// Date: 2011-02-05
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// Purpose: Define Interrupt support
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// Description: The interrupt specifics for Freescale Kinetis variants are
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// defined here.
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//
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// Usage: #include <cyg/hal/var_intr.h>
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// However applications should include using <cyg/hal/hal_intr.h>
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// instead to allow for platform overrides.
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <cyg/hal/plf_intr.h>
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//==========================================================================
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typedef enum {
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CYGNUM_HAL_INTERRUPT_DMA0
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= CYGNUM_HAL_INTERRUPT_EXTERNAL, // DMA Channel 0 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA1, // DMA Channel 1 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA2, // DMA Channel 2 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA3, // DMA Channel 3 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA4, // DMA Channel 4 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA5, // DMA Channel 5 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA6, // DMA Channel 6 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA7, // DMA Channel 7 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA8, // DMA Channel 8 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA9, // DMA Channel 9 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA10, // DMA Channel 10 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA11, // DMA Channel 11 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA12, // DMA Channel 12 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA13, // DMA Channel 13 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA14, // DMA Channel 14 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA15, // DMA Channel 15 Transfer Complete
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CYGNUM_HAL_INTERRUPT_DMA_ERROR, // DMA Error Int
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CYGNUM_HAL_INTERRUPT_MCM, // Normal Int
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CYGNUM_HAL_INTERRUPT_FTFL, // FTFL Int
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CYGNUM_HAL_INTERRUPT_READ_COLLISION, // Read Collision Int
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CYGNUM_HAL_INTERRUPT_LVD_LVW, // Low Volt Detect, Low Volt Warn
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CYGNUM_HAL_INTERRUPT_LLW, // Low Leakage Wakeup
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CYGNUM_HAL_INTERRUPT_WDOG, // WDOG Int
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CYGNUM_HAL_INTERRUPT_RNGB, // RNGB Int
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CYGNUM_HAL_INTERRUPT_I2C0, // I2C0 int
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CYGNUM_HAL_INTERRUPT_I2C1, // I2C1 int
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CYGNUM_HAL_INTERRUPT_SPI0, // SPI0 Int
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CYGNUM_HAL_INTERRUPT_SPI1, // SPI1 Int
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CYGNUM_HAL_INTERRUPT_SPI2, // SPI2 Int
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CYGNUM_HAL_INTERRUPT_CAN0_ORED_MESSAGE_BUFFER,// CAN0 OR'd Msg Buffs Int
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CYGNUM_HAL_INTERRUPT_CAN0_BUS_OFF, // CAN0 Bus Off Int
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CYGNUM_HAL_INTERRUPT_CAN0_ERROR, // CAN0 Error Int
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CYGNUM_HAL_INTERRUPT_CAN0_TX_WARNING, // CAN0 Tx Warning Int
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CYGNUM_HAL_INTERRUPT_CAN0_RX_WARNING, // CAN0 Rx Warning Int
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CYGNUM_HAL_INTERRUPT_CAN0_WAKE_UP, // CAN0 Wake Up Int
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CYGNUM_HAL_INTERRUPT_CAN0_IMEU, // CAN0 Ind. Match El Update (IMEU) Int
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CYGNUM_HAL_INTERRUPT_CAN0_LOST_RX, // CAN0 Lost Receive Int
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CYGNUM_HAL_INTERRUPT_CAN1_ORED_MESSAGE_BUFFER, // CAN1 OR'd Msg Buffs Int
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CYGNUM_HAL_INTERRUPT_CAN1_BUS_OFF, // CAN1 Bus Off Int
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CYGNUM_HAL_INTERRUPT_CAN1_ERROR, // CAN1 Error Int
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CYGNUM_HAL_INTERRUPT_CAN1_TX_WARNING, // CAN1 Tx Warning Int
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CYGNUM_HAL_INTERRUPT_CAN1_RX_WARNING, // CAN1 Rx Warning Int
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CYGNUM_HAL_INTERRUPT_CAN1_WAKE_UP, // CAN1 Wake Up Int
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CYGNUM_HAL_INTERRUPT_CAN1_IMEU, // CAN1 Ind. Match El Update (IMEU) Int
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CYGNUM_HAL_INTERRUPT_CAN1_LOST_RX, // CAN1 Lost Receive Int
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CYGNUM_HAL_INTERRUPT_UART0_RX_TX, // UART0 Receive/Transmit int
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CYGNUM_HAL_INTERRUPT_UART0_ERR, // UART0 Error int
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CYGNUM_HAL_INTERRUPT_UART1_RX_TX, // UART1 Receive/Transmit int
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CYGNUM_HAL_INTERRUPT_UART1_ERR, // UART1 Error int
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CYGNUM_HAL_INTERRUPT_UART2_RX_TX, // UART2 Receive/Transmit int
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CYGNUM_HAL_INTERRUPT_UART2_ERR, // UART2 Error int
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CYGNUM_HAL_INTERRUPT_UART3_RX_TX, // UART3 Receive/Transmit int
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CYGNUM_HAL_INTERRUPT_UART3_ERR, // UART3 Error int
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CYGNUM_HAL_INTERRUPT_UART4_RX_TX, // UART4 Receive/Transmit int
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CYGNUM_HAL_INTERRUPT_UART4_ERR, // UART4 Error int
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CYGNUM_HAL_INTERRUPT_UART5_RX_TX, // UART5 Receive/Transmit int
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CYGNUM_HAL_INTERRUPT_UART5_ERR, // UART5 Error int
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CYGNUM_HAL_INTERRUPT_ADC0, // ADC0 int
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CYGNUM_HAL_INTERRUPT_ADC1, // ADC1 int
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CYGNUM_HAL_INTERRUPT_CMP0, // CMP0 int
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CYGNUM_HAL_INTERRUPT_CMP1, // CMP1 int
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CYGNUM_HAL_INTERRUPT_CMP2, // CMP2 int
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CYGNUM_HAL_INTERRUPT_FTM0, // FTM0 fault, overflow and channels int
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CYGNUM_HAL_INTERRUPT_FTM1, // FTM1 fault, overflow and channels int
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CYGNUM_HAL_INTERRUPT_FTM2, // FTM2 fault, overflow and channels int
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CYGNUM_HAL_INTERRUPT_CMT, // CMT int
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CYGNUM_HAL_INTERRUPT_RTC, // RTC int
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CYGNUM_HAL_INTERRUPT_Reserved83, // Reserved int 83
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CYGNUM_HAL_INTERRUPT_PIT0, // PIT timer channel 0 int
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CYGNUM_HAL_INTERRUPT_PIT1, // PIT timer channel 1 int
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CYGNUM_HAL_INTERRUPT_PIT2, // PIT timer channel 2 int
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CYGNUM_HAL_INTERRUPT_PIT3, // PIT timer channel 3 int
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CYGNUM_HAL_INTERRUPT_PDB0, // PDB0 Int
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CYGNUM_HAL_INTERRUPT_USB0, // USB0 int
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CYGNUM_HAL_INTERRUPT_USBDCD, // USBDCD Int
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CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER, // ENET MAC IEEE 1588 Timer Int
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CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT, // ENET MAC Transmit Int
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CYGNUM_HAL_INTERRUPT_ENET_RECEIVE, // ENET MAC Receive Int
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CYGNUM_HAL_INTERRUPT_ENET_ERROR, // ENET MAC Error and miscelaneous Int
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CYGNUM_HAL_INTERRUPT_I2S0, // I2S0 Int
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CYGNUM_HAL_INTERRUPT_SDHC, // SDHC Int
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CYGNUM_HAL_INTERRUPT_DAC0, // DAC0 int
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CYGNUM_HAL_INTERRUPT_DAC1, // DAC1 int
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CYGNUM_HAL_INTERRUPT_TSI0, // TSI0 Int
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CYGNUM_HAL_INTERRUPT_MCG, // MCG Int
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CYGNUM_HAL_INTERRUPT_LPTIMER, // LPTimer int
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CYGNUM_HAL_INTERRUPT_LCD, // Segment LCD int
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CYGNUM_HAL_INTERRUPT_PORTA, // Port A int
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CYGNUM_HAL_INTERRUPT_PORTB, // Port B int
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CYGNUM_HAL_INTERRUPT_PORTC, // Port C int
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CYGNUM_HAL_INTERRUPT_PORTD, // Port D int
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CYGNUM_HAL_INTERRUPT_PORTE, // Port E int
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CYGNUM_HAL_INTERRUPT_Reserved108, // Reserved int 108
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CYGNUM_HAL_INTERRUPT_Reserved109, // Reserved int 109
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CYGNUM_HAL_INTERRUPT_Reserved110, // Reserved int 110
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CYGNUM_HAL_INTERRUPT_Reserved111, // Reserved int 111
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CYGNUM_HAL_INTERRUPT_Reserved112, // Reserved int 112
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CYGNUM_HAL_INTERRUPT_Reserved113, // Reserved int 113
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CYGNUM_HAL_INTERRUPT_Reserved114, // Reserved int 114
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CYGNUM_HAL_INTERRUPT_Reserved115, // Reserved int 115
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CYGNUM_HAL_INTERRUPT_Reserved116, // Reserved int 116
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CYGNUM_HAL_INTERRUPT_Reserved117, // Reserved int 117
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CYGNUM_HAL_INTERRUPT_Reserved118, // Reserved int 118
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CYGNUM_HAL_INTERRUPT_Reserved119 // Reserved int 119
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} KinetisExtInterrupt_e;
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#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_Reserved119)
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_Reserved119
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#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
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#define CYGNUM_HAL_VSR_MIN 0
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#ifndef CYGNUM_HAL_VSR_MAX
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# define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+ \
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CYGNUM_HAL_INTERRUPT_NVIC_MAX)
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#endif
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#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1)
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//==========================================================================
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// Interrupt mask and config for variant-specific devices
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// PORT Pin interrupts
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#define CYGHWR_HAL_KINETIS_PIN_IRQ_VECTOR(__pin) \
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(CYGNUM_HAL_INTERRUPT_PORTA + CYGHWR_HAL_KINETIS_PIN_PORT(__pin))
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//===========================================================================
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// Interrupt resources exported by HAL to device drivers
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// Export Interrupt vectors to serial driver.
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#define CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_UART0_RX_TX
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#define CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_UART1_RX_TX
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#define CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_UART2_RX_TX
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#define CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_UART3_RX_TX
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#define CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_UART4_RX_TX
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#define CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_UART5_RX_TX
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// Export Interrupt vectors to ENET driver.
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#define CYGNUM_FREESCALE_ENET0_1588_TIMER_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER
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#define CYGNUM_FREESCALE_ENET0_TRANSMIT_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT
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#define CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_ENET_RECEIVE
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#define CYGNUM_FREESCALE_ENET0_ERROR_INT_VECTOR \
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CYGNUM_HAL_INTERRUPT_ENET_ERROR
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//----------------------------------------------------------------------------
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#endif // CYGONCE_HAL_VAR_INTR_H
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// EOF var_intr.h
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