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#ifndef CYGONCE_HAL_VAR_IO_FLEXBUS_H
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#define CYGONCE_HAL_VAR_IO_FLEXBUS_H
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//===========================================================================
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//
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// var_io_flexbus.h
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//
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// Kinetis FlexBus specific registers
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//
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//===========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2011 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//===========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Ilija Kocho <ilijak@siva.com.mk>
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// Date: 2011-02-05
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// Purpose: Kinetis variant specific registers
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// Description:
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// Usage: #include <cyg/hal/var_io.h> // var_io.h includes this file
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================
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//---------------------------------------------------------------------------
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// FlexBus
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// FlexBus chip select control registers
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typedef struct cyghwr_hal_kinetis_fbcs_s{
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cyg_uint32 csar; // Chip select address register
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cyg_uint32 csmr; // Chip select mask register
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cyg_uint32 cscr; // Chip select control register
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} cyghwr_hal_kinetis_fbcs_t;
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#define CYGNUM_HAL_KINETIS_FBCS_N 6 // Kinetis has up to 6 chip selects
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// FlexBus control
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typedef volatile struct cyghwr_hal_kinetis_fb_s {
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cyghwr_hal_kinetis_fbcs_t csel[CYGNUM_HAL_KINETIS_FBCS_N]; //Chip Selects
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cyg_uint8 reserved[24];
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cyg_uint32 cspmcr; //Chip select port multiplexing control register
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} cyghwr_hal_kinetis_fb_t;
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#define CYGHWR_HAL_KINETIS_FB_P ((cyghwr_hal_kinetis_fb_t *) 0x4000C000)
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// CSAR - Chip Select Address Register
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// CSAR Bit Fields
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#define CYGHWR_HAL_FB_CSAR_BA_M 0xFFFF0000
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#define CYGHWR_HAL_FB_CSAR_BA_S 16
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#define CYGHWR_HAL_FB_CS_AR_BA(__val) VALUE_(CYGHWR_HAL_FB_CSAR_BA_S, __val)
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// CSMR - Chup Select Mask Register
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// CSMR Bit Fields
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#define CYGHWR_HAL_FB_CSMR_V_M 0x1
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#define CYGHWR_HAL_FB_CSMR_V_S 0
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#define CYGHWR_HAL_FB_CSMR_WP_M 0x100
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#define CYGHWR_HAL_FB_CSMR_WP_S 8
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#define CYGHWR_HAL_FB_CSMR_BAM_M 0xFFFF0000
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#define CYGHWR_HAL_FB_CSMR_BAM_S 16
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#define CYGHWR_HAL_FB_CS_MR_BAM(__val) VALUE_(CYGHWR_HAL_FB_CSMR_BAM_S, __val)
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// CSCR - Chip Select Control register
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// CSCR Bit Fields
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#define CYGHWR_HAL_FB_CSCR_BSTW_M 0x8
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#define CYGHWR_HAL_FB_CSCR_BSTW_S 3
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#define CYGHWR_HAL_FB_CSCR_BSTR_M 0x10
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#define CYGHWR_HAL_FB_CSCR_BSTR_S 4
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#define CYGHWR_HAL_FB_CSCR_BEM_M 0x20
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#define CYGHWR_HAL_FB_CSCR_BEM_S 5
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#define CYGHWR_HAL_FB_CSCR_PS_M 0xC0
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#define CYGHWR_HAL_FB_CSCR_PS_S 6
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#define CYGHWR_HAL_FB_CSCR_AA_M 0x100
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#define CYGHWR_HAL_FB_CSCR_AA_S 8
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#define CYGHWR_HAL_FB_CSCR_BLS_M 0x200
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#define CYGHWR_HAL_FB_CSCR_BLS_S 9
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#define CYGHWR_HAL_FB_CSCR_WS_M 0xFC00
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#define CYGHWR_HAL_FB_CSCR_WS_S 10
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#define CYGHWR_HAL_FB_CSCR_WRAH_M 0x30000
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#define CYGHWR_HAL_FB_CSCR_WRAH_S 16
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#define CYGHWR_HAL_FB_CSCR_RDAH_M 0xC0000
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#define CYGHWR_HAL_FB_CSCR_RDAH_S 18
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#define CYGHWR_HAL_FB_CSCR_ASET_M 0x300000
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#define CYGHWR_HAL_FB_CSCR_ASET_S 20
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#define CYGHWR_HAL_FB_CSCR_EXALE_M 0x400000
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#define CYGHWR_HAL_FB_CSCR_EXALE_S 22
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#define CYGHWR_HAL_FB_CSCR_SWSEN_M 0x800000
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#define CYGHWR_HAL_FB_CSCR_SWSEN_S 23
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#define CYGHWR_HAL_FB_CSCR_SWS_M 0xFC000000
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#define CYGHWR_HAL_FB_CSCR_SWS_S 26
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// CSPMCR Bit Fields
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#define CYGHWR_HAL_FB_CSPMCR_G5_M 0xF000
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#define CYGHWR_HAL_FB_CSPMCR_G5_S 12
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#define CYGHWR_HAL_FB_CSPMCR_G4_M 0xF0000
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#define CYGHWR_HAL_FB_CSPMCR_G4_S 16
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#define CYGHWR_HAL_FB_CSPMCR_G3_M 0xF00000
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#define CYGHWR_HAL_FB_CSPMCR_G3_S 20
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#define CYGHWR_HAL_FB_CSPMCR_G2_M 0xF000000
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#define CYGHWR_HAL_FB_CSPMCR_G2_S 24
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#define CYGHWR_HAL_FB_CSPMCR_G1_M 0xF0000000
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#define CYGHWR_HAL_FB_CSPMCR_G1_S 28
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// FlexBus control pin multiplexing
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#define CYGHWR_HAL_FB_CSPMCR(__group, __val) VALUE_(__group, __val)
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#define CYGHWR_HAL_FB_CSPMCR_G1_ALE \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 0)
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#define CYGHWR_HAL_FB_CSPMCR_G1_CS1 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 1)
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#define CYGHWR_HAL_FB_CSPMCR_G1_TS \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G1_S, 2)
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#define CYGHWR_HAL_FB_CSPMCR_G2_CS4 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 0)
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#define CYGHWR_HAL_FB_CSPMCR_G2_TSIZ0 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 1)
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#define CYGHWR_HAL_FB_CSPMCR_G2_BE_31_24 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G2_S, 2)
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#define CYGHWR_HAL_FB_CSPMCR_G3_CS5 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 0)
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#define CYGHWR_HAL_FB_CSPMCR_G3_TSIZ1 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 1)
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#define CYGHWR_HAL_FB_CSPMCR_G3_BE_23_16 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G3_S, 2)
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#define CYGHWR_HAL_FB_CSPMCR_G4_TST \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 0)
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#define CYGHWR_HAL_FB_CSPMCR_G4_CS2 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 1)
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#define CYGHWR_HAL_FB_CSPMCR_G4_BE_15_8 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G4_S, 2)
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#define CYGHWR_HAL_FB_CSPMCR_G5_TA \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 0)
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#define CYGHWR_HAL_FB_CSPMCR_G5_CS3 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 1)
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#define CYGHWR_HAL_FB_CSPMCR_G5_BE_7_0 \
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CYGHWR_HAL_FB_CSPMCR(CYGHWR_HAL_FB_CSPMCR_G5_S, 2)
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//-----------------------------------------------------------------------------
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// end of var_io_flexbus.h
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#endif // CYGONCE_HAL_VAR_IO_FLEXBUS_H
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