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//==========================================================================
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//
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// kinetis_clocking.c
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//
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// Cortex-M Kinetis HAL functions
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2010 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Ilija kocho <ilijak@siva.com.mk>
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// Date: 2011-10-19
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================
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#include <pkgconf/hal.h>
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#include <pkgconf/hal_cortexm.h>
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#include <pkgconf/hal_cortexm_kinetis.h>
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#ifdef CYGPKG_KERNEL
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#include <pkgconf/kernel.h>
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#endif
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#include <cyg/infra/diag.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/hal/cortexm_endian.h>
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#include <cyg/hal/hal_arch.h> // HAL header
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#include <cyg/hal/hal_intr.h> // HAL header
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#include <cyg/hal/hal_if.h> // HAL header
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#include <cyg/io/ser_freescale_uart.h>
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//===========================================================================
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// Forward declarations
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//===========================================================================
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cyg_uint32 hal_cortexm_systick_clock;
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cyg_uint32 hal_kinetis_sysclk;
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cyg_uint32 hal_kinetis_busclk;
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cyg_uint32 hal_get_cpu_clock(void);
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void hal_start_main_clock(void);
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void hal_set_clock_dividers(void);
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#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
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void hal_start_rtc_clock(void);
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#endif
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//==========================================================================
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// Setup up system clocks
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//
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// Set up clocks from configuration. In the future this should be extended so
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// that clock rates can be changed at runtime.
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void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
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hal_start_clocks( void )
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{
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cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
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#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT
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cyghwr_hal_kinetis_port_t *port_p = CYGHWR_HAL_KINETIS_PORTA_P;
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#endif
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#if !defined(CYG_HAL_STARTUP_RAM)
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# ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
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// Real Time Clock
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hal_start_rtc_clock();
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# endif
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// Main clock - MCG
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hal_start_main_clock();
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#endif
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// Trace clock
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#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACECLK_CORE
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sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M;
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#else
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sim_p->sopt2 &= ~CYGHWR_HAL_KINETIS_SIM_SOPT2_TRACECLKSEL_M;
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#endif
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#ifdef CYGHWR_HAL_CORTEXM_KINETIS_TRACE_CLKOUT
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port_p->pcr[6] = CYGHWR_HAL_KINETIS_PORT_PCR_MUX(0x7);
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#endif
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}
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#define MCG_WAIT_WHILE(_condition_) do{}while(_condition_)
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// Setup MCG
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// Note: Currently only PBE mode is supported and tested.
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void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
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hal_start_main_clock(void)
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{
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cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P;
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#if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL ||\
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defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
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cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
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#endif
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#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
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# if defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL || \
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defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC
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volatile cyg_uint8 *osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_P;
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# endif
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# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
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// Set the main oscillator
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*osc_cr_p = CYGHWR_HAL_CORTEXM_KINETIS_OSC_CAP / 2;
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# elif defined CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_OSC
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// Select exteranal oscillator
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*osc_cr_p = CYGHWR_HAL_KINETIS_OSC_CR_ERCLKEN_M |
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CYGHWR_HAL_KINETIS_OSC_CR_EREFSTEN_M;
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# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
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# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
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// Select RTC clock source for MCG reference
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sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_MCGCLKSEL_M;
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# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
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#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
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#if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
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defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) || \
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defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
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// Enter FBE mode
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mcg_p->c2 = CYGHWR_HAL_KINETIS_MCG_C2_RANGE(
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CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FREQ_RANGE)
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# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
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| CYGHWR_HAL_KINETIS_MCG_C2_EREFS_M | CYGHWR_HAL_KINETIS_MCG_C2_HGO_M
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# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
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;
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mcg_p->c1 = CYGHWR_HAL_KINETIS_MCG_C1_FRDIV(
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CYGNUM_HAL_CORTEXM_KINETIS_MCG_REF_FRDIV_REG)
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# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
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defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
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|CYGHWR_HAL_KINETIS_MCG_C1_CLKS(CYGHWR_HAL_KINETIS_MCG_C1_CLKS_EXT_REF)
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# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL
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;
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# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_XTAL
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// Wait for oscillator start up
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MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_OSCINIT_M));
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# endif
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# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
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// Wait for reference clock to switch to external reference
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MCG_WAIT_WHILE(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_IREFST_M);
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// Wait for status flags update
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MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
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# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
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defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
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CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT
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# else
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CYGHWR_HAL_KINETIS_MCG_S_CLKST_FLL
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# endif
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);
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# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT
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// Set peripheral dividers before switching to high frequency.
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hal_set_clock_dividers();
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# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL
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// Configure FLL
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mcg_p->c4 = (mcg_p->c4 & 0x1f) |
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(CYGNUM_HAL_CORTEXM_MCG_DCO_DMX32 |
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CYGHWR_HAL_KINETIS_MCG_C4_DRST_DRS(
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CYGNUM_HAL_CORTEXM_MCG_DCO_DRST_DRS));
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# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL
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# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL
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// Configure PLL and enter PBE mode
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mcg_p->c5 = CYGHWR_HAL_KINETIS_MCG_C5_PRDIV(
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CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_PRDIV-1) |
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CYGHWR_HAL_KINETIS_MCG_C5_PLLSTEN_M;
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mcg_p->c6 = CYGHWR_HAL_KINETIS_MCG_C6_VDIV(
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CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_PLL_VDIV-24);
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// Switch to PBE mode
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mcg_p->c6 |= CYGHWR_HAL_KINETIS_MCG_C6_PLLS_M;
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MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
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CYGHWR_HAL_KINETIS_MCG_S_CLKST_EXT);
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MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_PLLST_M));
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MCG_WAIT_WHILE(!(mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_LOCK_M));
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// Enter PEE mode
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mcg_p->c1 &= ~CYGHWR_HAL_KINETIS_MCG_C1_CLKS_M;
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MCG_WAIT_WHILE((mcg_p->status & CYGHWR_HAL_KINETIS_MCG_S_CLKST_M) !=
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CYGHWR_HAL_KINETIS_MCG_S_CLKST_PLL);
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# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL
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# if defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) || \
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defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
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sim_p->sopt2 |= CYGHWR_HAL_KINETIS_SIM_SOPT2_PLLFLLSEL_M;
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# endif
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#endif // defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL) ||
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// defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL) ||
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// defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
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}
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cyg_uint32 CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
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hal_get_cpu_clock(void)
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{
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cyg_uint32 freq;
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#ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_PLL
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cyghwr_hal_kinetis_mcg_t *mcg_p = CYGHWR_HAL_KINETIS_MCG_P;
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freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_PLL_REF_FREQ /
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((mcg_p->c5 & CYGHWR_HAL_KINETIS_MCG_C5_PRDIV_M)+1) *
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((mcg_p->c6 & CYGHWR_HAL_KINETIS_MCG_C6_VDIV_M)+24);
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#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_FLL)
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freq = CYGNUM_HAL_CORTEXM_KINETIS_MCG_FLL_FREQ_AV;
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#elif defined(CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_EXT_REFCLK)
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freq = CYGOPT_HAL_CORTEXM_KINETIS_MCGOUT_EXT_RC;
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#else // ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_none
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#endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_MCGOUTCLK_end
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return freq;
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}
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void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
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hal_set_clock_dividers(void)
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| 251 |
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{
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cyghwr_hal_kinetis_sim_t *sim_p = CYGHWR_HAL_KINETIS_SIM_P;
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sim_p->clk_div1 = CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV1(0) |
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CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV2(
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CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS-1) |
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CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV3(
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CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLEX_BUS-1) |
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CYGHWR_HAL_KINETIS_SIM_CLKDIV1_OUTDIV4(
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CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_FLASH-1);
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sim_p->clk_div2 = CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBDIV(
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CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_DIV-1) |
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| 264 |
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|
(CYGHWR_HAL_CORTEXM_KINETIS_USBCLK_FRAC==2 ?
|
| 265 |
|
|
CYGHWR_HAL_KINETIS_SIM_CLKDIV2_USBFRAC_M : 0);
|
| 266 |
|
|
}
|
| 267 |
|
|
|
| 268 |
|
|
#ifdef CYGHWR_HAL_CORTEXM_KINETIS_RTC
|
| 269 |
|
|
void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
|
| 270 |
|
|
hal_start_rtc_clock(void)
|
| 271 |
|
|
{
|
| 272 |
|
|
cyghwr_hal_kinetis_rtc_t *rtc_p = CYGHWR_HAL_KINETIS_RTC_P;
|
| 273 |
|
|
|
| 274 |
|
|
rtc_p->ier=0; // Disable RTC interrupts
|
| 275 |
|
|
|
| 276 |
|
|
//Start RTC clock if not already started
|
| 277 |
|
|
if(!(rtc_p->cr & CYGHWR_HAL_KINETIS_RTC_CR_OSCE)){
|
| 278 |
|
|
rtc_p->cr = CYGHWR_HAL_KINETIS_RTC_CR_OSCE |
|
| 279 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_RTC_OSC_CAP;
|
| 280 |
|
|
# ifdef CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
|
| 281 |
|
|
{
|
| 282 |
|
|
volatile cyg_uint32 busycnt;
|
| 283 |
|
|
for(busycnt=1000000; busycnt; busycnt--)
|
| 284 |
|
|
__asm__ volatile ("nop\n");
|
| 285 |
|
|
}
|
| 286 |
|
|
# endif // CYGOPT_HAL_CORTEXM_KINETIS_MCG_REF_EXT_IS_RTC
|
| 287 |
|
|
}
|
| 288 |
|
|
}
|
| 289 |
|
|
#endif
|
| 290 |
|
|
|
| 291 |
|
|
|
| 292 |
|
|
//==========================================================================
|
| 293 |
|
|
// UART baud rate
|
| 294 |
|
|
//
|
| 295 |
|
|
// Set the baud rate divider of a UART based on the requested rate and
|
| 296 |
|
|
// the current clock settings.
|
| 297 |
|
|
|
| 298 |
|
|
|
| 299 |
|
|
void CYGOPT_HAL_KINETIS_MISC_FLASH_SECTION_ATTR
|
| 300 |
|
|
hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud)
|
| 301 |
|
|
{
|
| 302 |
|
|
cyg_uint32 sbr, brfa;
|
| 303 |
|
|
cyg_uint32 regval;
|
| 304 |
|
|
|
| 305 |
|
|
switch(uart_p) {
|
| 306 |
|
|
case CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE:
|
| 307 |
|
|
case CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE:
|
| 308 |
|
|
sbr = hal_kinetis_sysclk/(16*baud);
|
| 309 |
|
|
break;
|
| 310 |
|
|
case CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE:
|
| 311 |
|
|
case CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE:
|
| 312 |
|
|
case CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE:
|
| 313 |
|
|
case CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE:
|
| 314 |
|
|
sbr = hal_kinetis_busclk/(16*baud);
|
| 315 |
|
|
break;
|
| 316 |
|
|
default:
|
| 317 |
|
|
sbr=0;
|
| 318 |
|
|
break;
|
| 319 |
|
|
}
|
| 320 |
|
|
if(sbr) {
|
| 321 |
|
|
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval);
|
| 322 |
|
|
regval &= 0xE0;
|
| 323 |
|
|
regval |= sbr >> 8;
|
| 324 |
|
|
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval);
|
| 325 |
|
|
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDL, (sbr & 0xFF));
|
| 326 |
|
|
brfa = (((32*hal_kinetis_busclk)/(16*baud))-(32*sbr));
|
| 327 |
|
|
HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval);
|
| 328 |
|
|
regval &= 0xE0;
|
| 329 |
|
|
regval |= brfa & 0x1f;
|
| 330 |
|
|
HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval);
|
| 331 |
|
|
}
|
| 332 |
|
|
}
|
| 333 |
|
|
|
| 334 |
|
|
|
| 335 |
|
|
void hal_update_clock_var(void)
|
| 336 |
|
|
{
|
| 337 |
|
|
hal_kinetis_sysclk=hal_get_cpu_clock();
|
| 338 |
|
|
hal_kinetis_busclk=hal_kinetis_sysclk /
|
| 339 |
|
|
CYGHWR_HAL_CORTEXM_KINETIS_CLKDIV_PER_BUS;
|
| 340 |
|
|
hal_cortexm_systick_clock=hal_kinetis_sysclk;
|
| 341 |
|
|
}
|
| 342 |
|
|
|
| 343 |
|
|
|
| 344 |
|
|
cyg_uint32 hal_get_peripheral_clock(void)
|
| 345 |
|
|
{
|
| 346 |
|
|
return hal_kinetis_busclk;
|
| 347 |
|
|
}
|
| 348 |
|
|
|
| 349 |
|
|
//==========================================================================
|
| 350 |
|
|
// EOF kinetis_clocking.c
|
