URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [cortexm/] [lm3s/] [var/] [current/] [src/] [lm3s_misc.c] - Blame information for rev 838

Go to most recent revision | Details | Compare with Previous | View Log


//==========================================================================
//
//      lm3s_misc.c
//
//      Stellaris Cortex-M3 variant HAL functions
//
//==========================================================================
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
// -------------------------------------------                              
// This file is part of eCos, the Embedded Configurable Operating System.   
// Copyright (C) 2011 Free Software Foundation, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under    
// the terms of the GNU General Public License as published by the Free     
// Software Foundation; either version 2 or (at your option) any later      
// version.                                                                 
//
// eCos is distributed in the hope that it will be useful, but WITHOUT      
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
// for more details.                                                        
//
// You should have received a copy of the GNU General Public License        
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
//
// As a special exception, if other files instantiate templates or use      
// macros or inline functions from this file, or you compile this file      
// and link it with other works to produce a work based on this file,       
// this file does not by itself cause the resulting work to be covered by   
// the GNU General Public License. However the source code for this file    
// must still be made available in accordance with section (3) of the GNU   
// General Public License v2.                                               
//
// This exception does not invalidate any other reasons why a work based    
// on this file might be covered by the GNU General Public License.         
// -------------------------------------------                              
// ####ECOSGPLCOPYRIGHTEND####                                              
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    ccoutand
// Date:         2011-01-18
// Description:  
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#endif
 
#include <cyg/infra/diag.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_trac.h>        // Tracing macros
#include <cyg/infra/cyg_ass.h>         // Assertion macros
 
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_if.h>
 
//==========================================================================
// Initialization
//
__externC void  hal_start_clocks(void);
 
// Clock computation must be done per Variant basis
cyg_uint32      hal_cortexm_systick_clock;
cyg_uint32      hal_lm3s_sysclk;
 
 
void
hal_variant_init(void)
{
#if !defined(CYG_HAL_STARTUP_RAM)
    hal_start_clocks();
#endif
 
    // All LM3S devices use PORTA 0/1 for UART0
#if CYGINT_HAL_CORTEXM_LM3S_UART0>0
    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0, 1);
    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0_GPIO, 1);
#endif
 
#if CYGINT_HAL_CORTEXM_LM3S_UART1>0
 
# ifdef CYGHWR_HAL_LM3S_P_UART1_GPIO
    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1, 1);
    CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1_GPIO, 1);
# else
#  error "Variant/Platform does not specify UART1 GPIO Port"
# endif
 
#endif
 
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
    hal_if_init();
#endif
}
 
//==========================================================================
// GPIO support
//
// These functions provide configuration and IO for GPIO pins.
//
 
__externC void
hal_lm3s_gpio_set(cyg_uint32 pin)
{
    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
    cyg_uint32      bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
    cyg_uint32      cm = CYGHWR_HAL_LM3S_GPIO_CFG(pin);
    cyg_uint32      mode = CYGHWR_HAL_LM3S_GPIO_MODE(pin);
    cyg_uint32      irq = CYGHWR_HAL_LM3S_GPIO_IRQ(pin);
    cyg_uint32      st = CYGHWR_HAL_LM3S_GPIO_STRENGTH(pin);
    cyg_uint32      reg,
                    dir,
                    im,
                    dr2r,
                    dr4r,
                    dr8r;
 
    if (pin == CYGHWR_HAL_LM3S_GPIO_NONE)
        return;
 
    /*
     *  Handle IO mode settings
     */
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, reg);
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, dir);
 
    HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg & ~(bit)));
    if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_IN)
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir & ~(bit)));
    else if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_OUT)
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir | bit));
    else
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg | bit));
 
    /*
     *  Handle IO configuration
     */
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, reg);
    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP ||
        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP ||
        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) {
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg | bit));
    } else
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg & ~(bit)));
 
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, reg);
    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLUP ||
        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP) {
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg | bit));
    } else
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg & ~(bit)));
 
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, reg);
    if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLDOWN ||
        cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) {
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg | bit));
    } else
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg & ~(bit)));
 
    /*
     *  Handle IO strength
     */
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, dr2r);
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, dr4r);
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, dr8r);
    if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_2_MA) {
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit)));
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit)));
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r | bit));
    } else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_4_MA) {
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit)));
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit)));
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r | bit));
    } else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_8_MA) {
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit)));
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit)));
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r | bit));
    }
 
    /*
     *  Handle interrupt settings
     */
    HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, im);
    HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im & ~(bit)));
    if (irq != CYGHWR_HAL_LM3S_GPIO_IRQ_DISABLE) {
        HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, reg);
 
        if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL ||
            irq == CYGHWR_HAL_LM3S_GPIO_IRQ_HIGH_LEVEL)
            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg | bit));
        else
            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg & ~(bit)));
 
        HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, reg);
        if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_BOTH_EDGES) {
            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg | bit));
        } else {
            HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg & ~(bit)));
 
            HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV, reg);
            if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL ||
                irq == CYGHWR_HAL_LM3S_GPIO_IRQ_FALLING_EDGE)
                HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV,
                                 (reg & ~(bit)));
            else
                HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV,
                                 (reg | bit));
        }
 
        HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im | bit));
    }
}
 
__externC void
hal_lm3s_gpio_out(cyg_uint32 pin, int val)
{
    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
    int             bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
 
    port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2));
 
    HAL_WRITE_UINT32(port, (val ? bit : 0));
}
 
__externC void
hal_lm3s_gpio_in(cyg_uint32 pin, int *val)
{
    cyg_uint32      port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);
    int             bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));
    cyg_uint32      pd;
 
    port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2));
 
    HAL_READ_UINT32(port, pd);
    *val = pd;
}
 
 
//==========================================================================
// Peripheral support
//
 
__externC void
hal_lm3s_periph_set(cyg_uint32 periph, cyg_uint32 on_off)
{
    cyg_uint32      reg;
 
    if (CYGHWR_HAL_LM3S_PERIPH_GC0 & periph) {
        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg);
        if (on_off)
            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0);
        else
            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0);
        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg);
    }
 
    if (CYGHWR_HAL_LM3S_PERIPH_GC1 & periph) {
        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg);
        if (on_off)
            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1);
        else
            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1);
        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg);
    }
 
    if (CYGHWR_HAL_LM3S_PERIPH_GC2 & periph) {
        HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg);
        if (on_off)
            reg |= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2);
        else
            reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2);
        HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg);
    }
 
}
 
 
//==========================================================================
// UART baud rate
//
// Set the baud rate divider of a UART based on the requested rate and
// the current APB clock settings.
//
 
__externC void
hal_lm3s_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)
{
    cyg_uint32      int_div,
                    frac_div;
 
    int_div = ((((hal_cortexm_systick_clock << 3) / baud) + 1) >> 1);
 
    frac_div = int_div % 64;
    int_div = int_div >> 6;
 
    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IBRD, int_div);
    HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_FBRD, frac_div);
}
 
 
//==========================================================================
// I2C clock rate
//
__externC cyg_uint32
hal_lm3s_i2c_clock(void)
{
    return hal_lm3s_sysclk;
}
 
//==========================================================================
// Timer clock rate
//
__externC cyg_uint32
hal_lm3s_timer_clock(void)
{
    return hal_lm3s_sysclk;
}
 
//==========================================================================
// EOF lm3s_misc_misc.c

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [cortexm/] [lm3s/] [var/] [current/] [src/] [lm3s_misc.c] - Blame information for rev 838

Line No.	Rev	Author	Line
1	786	skrzyp	`//==========================================================================`
2			`//`
3			`// lm3s_misc.c`
4			`//`
5			`// Stellaris Cortex-M3 variant HAL functions`
6			`//`
7			`//==========================================================================`
8			`// ####ECOSGPLCOPYRIGHTBEGIN####`
9			`// -------------------------------------------`
10			`// This file is part of eCos, the Embedded Configurable Operating System.`
11			`// Copyright (C) 2011 Free Software Foundation, Inc.`
12			`//`
13			`// eCos is free software; you can redistribute it and/or modify it under`
14			`// the terms of the GNU General Public License as published by the Free`
15			`// Software Foundation; either version 2 or (at your option) any later`
16			`// version.`
17			`//`
18			`// eCos is distributed in the hope that it will be useful, but WITHOUT`
19			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
20			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
21			`// for more details.`
22			`//`
23			`// You should have received a copy of the GNU General Public License`
24			`// along with eCos; if not, write to the Free Software Foundation, Inc.,`
25			`// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
26			`//`
27			`// As a special exception, if other files instantiate templates or use`
28			`// macros or inline functions from this file, or you compile this file`
29			`// and link it with other works to produce a work based on this file,`
30			`// this file does not by itself cause the resulting work to be covered by`
31			`// the GNU General Public License. However the source code for this file`
32			`// must still be made available in accordance with section (3) of the GNU`
33			`// General Public License v2.`
34			`//`
35			`// This exception does not invalidate any other reasons why a work based`
36			`// on this file might be covered by the GNU General Public License.`
37			`// -------------------------------------------`
38			`// ####ECOSGPLCOPYRIGHTEND####`
39			`//==========================================================================`
40			`//#####DESCRIPTIONBEGIN####`
41			`//`
42			`// Author(s): ccoutand`
43			`// Date: 2011-01-18`
44			`// Description:`
45			`//`
46			`//####DESCRIPTIONEND####`
47			`//`
48			`//==========================================================================`
49
50			`#include <pkgconf/hal.h>`
51
52			`#ifdef CYGPKG_KERNEL`
53			`# include <pkgconf/kernel.h>`
54			`#endif`
55
56			`#include <cyg/infra/diag.h>`
57			`#include <cyg/infra/cyg_type.h>`
58			`#include <cyg/infra/cyg_trac.h> // Tracing macros`
59			`#include <cyg/infra/cyg_ass.h> // Assertion macros`
60
61			`#include <cyg/hal/hal_arch.h>`
62			`#include <cyg/hal/hal_intr.h>`
63			`#include <cyg/hal/hal_if.h>`
64
65			`//==========================================================================`
66			`// Initialization`
67			`//`
68			`__externC void hal_start_clocks(void);`
69
70			`// Clock computation must be done per Variant basis`
71			`cyg_uint32 hal_cortexm_systick_clock;`
72			`cyg_uint32 hal_lm3s_sysclk;`
73
74
75			`void`
76			`hal_variant_init(void)`
77			`{`
78			`#if !defined(CYG_HAL_STARTUP_RAM)`
79			`hal_start_clocks();`
80			`#endif`
81
82			`// All LM3S devices use PORTA 0/1 for UART0`
83			`#if CYGINT_HAL_CORTEXM_LM3S_UART0>0`
84			`CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0, 1);`
85			`CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART0_GPIO, 1);`
86			`#endif`
87
88			`#if CYGINT_HAL_CORTEXM_LM3S_UART1>0`
89
90			`# ifdef CYGHWR_HAL_LM3S_P_UART1_GPIO`
91			`CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1, 1);`
92			`CYGHWR_HAL_LM3S_PERIPH_SET(CYGHWR_HAL_LM3S_P_UART1_GPIO, 1);`
93			`# else`
94			`# error "Variant/Platform does not specify UART1 GPIO Port"`
95			`# endif`
96
97			`#endif`
98
99			`#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT`
100			`hal_if_init();`
101			`#endif`
102			`}`
103
104			`//==========================================================================`
105			`// GPIO support`
106			`//`
107			`// These functions provide configuration and IO for GPIO pins.`
108			`//`
109
110			`__externC void`
111			`hal_lm3s_gpio_set(cyg_uint32 pin)`
112			`{`
113			`cyg_uint32 port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);`
114			`cyg_uint32 bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));`
115			`cyg_uint32 cm = CYGHWR_HAL_LM3S_GPIO_CFG(pin);`
116			`cyg_uint32 mode = CYGHWR_HAL_LM3S_GPIO_MODE(pin);`
117			`cyg_uint32 irq = CYGHWR_HAL_LM3S_GPIO_IRQ(pin);`
118			`cyg_uint32 st = CYGHWR_HAL_LM3S_GPIO_STRENGTH(pin);`
119			`cyg_uint32 reg,`
120			`dir,`
121			`im,`
122			`dr2r,`
123			`dr4r,`
124			`dr8r;`
125
126			`if (pin == CYGHWR_HAL_LM3S_GPIO_NONE)`
127			`return;`
128
129			`/*`
130			`* Handle IO mode settings`
131			`*/`
132			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, reg);`
133			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, dir);`
134
135			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg & ~(bit)));`
136			`if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_IN)`
137			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir & ~(bit)));`
138			`else if (mode == CYGHWR_HAL_LM3S_GPIO_MODE_OUT)`
139			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DIR, (dir \| bit));`
140			`else`
141			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_AFSEL, (reg \| bit));`
142
143			`/*`
144			`* Handle IO configuration`
145			`*/`
146			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, reg);`
147			`if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP \|\|`
148			`cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP \|\|`
149			`cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) {`
150			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg \| bit));`
151			`} else`
152			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_ODR, (reg & ~(bit)));`
153
154			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, reg);`
155			`if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLUP \|\|`
156			`cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLUP) {`
157			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg \| bit));`
158			`} else`
159			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PUR, (reg & ~(bit)));`
160
161			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, reg);`
162			`if (cm == CYGHWR_HAL_LM3S_GPIO_CNF_PULLDOWN \|\|`
163			`cm == CYGHWR_HAL_LM3S_GPIO_CNF_OP_PULLDOWN) {`
164			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg \| bit));`
165			`} else`
166			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_PDR, (reg & ~(bit)));`
167
168			`/*`
169			`* Handle IO strength`
170			`*/`
171			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, dr2r);`
172			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, dr4r);`
173			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, dr8r);`
174			`if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_2_MA) {`
175			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit)));`
176			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit)));`
177			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r \| bit));`
178			`} else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_4_MA) {`
179			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit)));`
180			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r & ~(bit)));`
181			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r \| bit));`
182			`} else if (st == CYGHWR_HAL_LM3S_GPIO_STRENGTH_8_MA) {`
183			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR2R, (dr2r & ~(bit)));`
184			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR4R, (dr4r & ~(bit)));`
185			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_DR8R, (dr8r \| bit));`
186			`}`
187
188			`/*`
189			`* Handle interrupt settings`
190			`*/`
191			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, im);`
192			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im & ~(bit)));`
193			`if (irq != CYGHWR_HAL_LM3S_GPIO_IRQ_DISABLE) {`
194			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, reg);`
195
196			`if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL \|\|`
197			`irq == CYGHWR_HAL_LM3S_GPIO_IRQ_HIGH_LEVEL)`
198			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg \| bit));`
199			`else`
200			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IS, (reg & ~(bit)));`
201
202			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, reg);`
203			`if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_BOTH_EDGES) {`
204			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg \| bit));`
205			`} else {`
206			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IBE, (reg & ~(bit)));`
207
208			`HAL_READ_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV, reg);`
209			`if (irq == CYGHWR_HAL_LM3S_GPIO_IRQ_LOW_LEVEL \|\|`
210			`irq == CYGHWR_HAL_LM3S_GPIO_IRQ_FALLING_EDGE)`
211			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV,`
212			`(reg & ~(bit)));`
213			`else`
214			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IEV,`
215			`(reg \| bit));`
216			`}`
217
218			`HAL_WRITE_UINT32(port + CYGHWR_HAL_LM3S_GPIO_IM, (im \| bit));`
219			`}`
220			`}`
221
222			`__externC void`
223			`hal_lm3s_gpio_out(cyg_uint32 pin, int val)`
224			`{`
225			`cyg_uint32 port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);`
226			`int bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));`
227
228			`port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2));`
229
230			`HAL_WRITE_UINT32(port, (val ? bit : 0));`
231			`}`
232
233			`__externC void`
234			`hal_lm3s_gpio_in(cyg_uint32 pin, int *val)`
235			`{`
236			`cyg_uint32 port = CYGHWR_HAL_LM3S_GPIO_PORT(pin);`
237			`int bit = (1 << CYGHWR_HAL_LM3S_GPIO_BIT(pin));`
238			`cyg_uint32 pd;`
239
240			`port += (CYGHWR_HAL_LM3S_GPIO_DATA + (bit << 2));`
241
242			`HAL_READ_UINT32(port, pd);`
243			`*val = pd;`
244			`}`
245
246
247			`//==========================================================================`
248			`// Peripheral support`
249			`//`
250
251			`__externC void`
252			`hal_lm3s_periph_set(cyg_uint32 periph, cyg_uint32 on_off)`
253			`{`
254			`cyg_uint32 reg;`
255
256			`if (CYGHWR_HAL_LM3S_PERIPH_GC0 & periph) {`
257			`HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg);`
258			`if (on_off)`
259			`reg \|= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0);`
260			`else`
261			`reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC0);`
262			`HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC0, reg);`
263			`}`
264
265			`if (CYGHWR_HAL_LM3S_PERIPH_GC1 & periph) {`
266			`HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg);`
267			`if (on_off)`
268			`reg \|= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1);`
269			`else`
270			`reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC1);`
271			`HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC1, reg);`
272			`}`
273
274			`if (CYGHWR_HAL_LM3S_PERIPH_GC2 & periph) {`
275			`HAL_READ_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg);`
276			`if (on_off)`
277			`reg \|= (periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2);`
278			`else`
279			`reg &= ~(periph & ~CYGHWR_HAL_LM3S_PERIPH_GC2);`
280			`HAL_WRITE_UINT32(CYGHWR_HAL_LM3S_SC + CYGHWR_HAL_LM3S_SC_RCGC2, reg);`
281			`}`
282
283			`}`
284
285
286			`//==========================================================================`
287			`// UART baud rate`
288			`//`
289			`// Set the baud rate divider of a UART based on the requested rate and`
290			`// the current APB clock settings.`
291			`//`
292
293			`__externC void`
294			`hal_lm3s_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)`
295			`{`
296			`cyg_uint32 int_div,`
297			`frac_div;`
298
299			`int_div = ((((hal_cortexm_systick_clock << 3) / baud) + 1) >> 1);`
300
301			`frac_div = int_div % 64;`
302			`int_div = int_div >> 6;`
303
304			`HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_IBRD, int_div);`
305			`HAL_WRITE_UINT32(base + CYGHWR_HAL_LM3S_UART_FBRD, frac_div);`
306			`}`
307
308
309			`//==========================================================================`
310			`// I2C clock rate`
311			`//`
312			`__externC cyg_uint32`
313			`hal_lm3s_i2c_clock(void)`
314			`{`
315			`return hal_lm3s_sysclk;`
316			`}`
317
318			`//==========================================================================`
319			`// Timer clock rate`
320			`//`
321			`__externC cyg_uint32`
322			`hal_lm3s_timer_clock(void)`
323			`{`
324			`return hal_lm3s_sysclk;`
325			`}`
326
327			`//==========================================================================`
328			`// EOF lm3s_misc_misc.c`