| 1 |
786 |
skrzyp |
##==========================================================================
|
| 2 |
|
|
##
|
| 3 |
|
|
## hal_cortexm_lpc17xx.cdl
|
| 4 |
|
|
##
|
| 5 |
|
|
## Cortex-M LPC 1700 variant HAL configuration data
|
| 6 |
|
|
##
|
| 7 |
|
|
##==========================================================================
|
| 8 |
|
|
## ####ECOSGPLCOPYRIGHTBEGIN####
|
| 9 |
|
|
## -------------------------------------------
|
| 10 |
|
|
## This file is part of eCos, the Embedded Configurable Operating System.
|
| 11 |
|
|
## Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
| 12 |
|
|
##
|
| 13 |
|
|
## eCos is free software; you can redistribute it and/or modify it under
|
| 14 |
|
|
## the terms of the GNU General Public License as published by the Free
|
| 15 |
|
|
## Software Foundation; either version 2 or (at your option) any later
|
| 16 |
|
|
## version.
|
| 17 |
|
|
##
|
| 18 |
|
|
## eCos is distributed in the hope that it will be useful, but WITHOUT
|
| 19 |
|
|
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 20 |
|
|
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 21 |
|
|
## for more details.
|
| 22 |
|
|
##
|
| 23 |
|
|
## You should have received a copy of the GNU General Public License
|
| 24 |
|
|
## along with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 25 |
|
|
## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 26 |
|
|
##
|
| 27 |
|
|
## As a special exception, if other files instantiate templates or use
|
| 28 |
|
|
## macros or inline functions from this file, or you compile this file
|
| 29 |
|
|
## and link it with other works to produce a work based on this file,
|
| 30 |
|
|
## this file does not by itself cause the resulting work to be covered by
|
| 31 |
|
|
## the GNU General Public License. However the source code for this file
|
| 32 |
|
|
## must still be made available in accordance with section (3) of the GNU
|
| 33 |
|
|
## General Public License v2.
|
| 34 |
|
|
##
|
| 35 |
|
|
## This exception does not invalidate any other reasons why a work based
|
| 36 |
|
|
## on this file might be covered by the GNU General Public License.
|
| 37 |
|
|
## -------------------------------------------
|
| 38 |
|
|
## ####ECOSGPLCOPYRIGHTEND####
|
| 39 |
|
|
##==========================================================================
|
| 40 |
|
|
#######DESCRIPTIONBEGIN####
|
| 41 |
|
|
##
|
| 42 |
|
|
## Author(s): ilijak
|
| 43 |
|
|
## Date: 2010-12-05
|
| 44 |
|
|
##
|
| 45 |
|
|
######DESCRIPTIONEND####
|
| 46 |
|
|
##
|
| 47 |
|
|
##==========================================================================
|
| 48 |
|
|
|
| 49 |
|
|
cdl_package CYGPKG_HAL_CORTEXM_LPC17XX {
|
| 50 |
|
|
display "Cortex-M3 LPC 17XX Variant"
|
| 51 |
|
|
parent CYGPKG_HAL_CORTEXM
|
| 52 |
|
|
hardware
|
| 53 |
|
|
include_dir cyg/hal
|
| 54 |
|
|
define_header hal_cortexm_lpc17xx.h
|
| 55 |
|
|
description "
|
| 56 |
|
|
This package provides generic support for the NXP Cortex-M based
|
| 57 |
|
|
LPC17xx microcontroller family. It is also necessary to select
|
| 58 |
|
|
a variant and platform HAL package."
|
| 59 |
|
|
|
| 60 |
|
|
compile hal_diag.c lpc17xx_misc.c
|
| 61 |
|
|
|
| 62 |
|
|
implements CYGINT_HAL_DEBUG_GDB_STUBS
|
| 63 |
|
|
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
|
| 64 |
|
|
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
|
| 65 |
|
|
implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
|
| 66 |
|
|
|
| 67 |
|
|
requires { CYGHWR_HAL_CORTEXM == "M3" }
|
| 68 |
|
|
|
| 69 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX {
|
| 70 |
|
|
display "LPC17xx member in use"
|
| 71 |
|
|
flavor data
|
| 72 |
|
|
default_value { "1766" }
|
| 73 |
|
|
legal_values {
|
| 74 |
|
|
"1751" "1752" "1754" "1756" "1758" "1759" "1763" "1764"
|
| 75 |
|
|
"1765" "1766" "1767" "1768" "1769" }
|
| 76 |
|
|
description "
|
| 77 |
|
|
The LPC17xx has several variants, the main differences being
|
| 78 |
|
|
in the size of on-chip FLASH and SRAM and numbers of some
|
| 79 |
|
|
peripherals. This option allows the platform HAL to select
|
| 80 |
|
|
the specific microcontroller fitted."
|
| 81 |
|
|
}
|
| 82 |
|
|
|
| 83 |
|
|
cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
|
| 84 |
|
|
display "CPU priority levels"
|
| 85 |
|
|
flavor data
|
| 86 |
|
|
calculated 5
|
| 87 |
|
|
description "
|
| 88 |
|
|
This option defines the number of bits used to encode the
|
| 89 |
|
|
exception priority levels that this variant of the Cortex-M
|
| 90 |
|
|
CPU implements."
|
| 91 |
|
|
}
|
| 92 |
|
|
|
| 93 |
|
|
cdl_option CYGNUM_HAL_IRQ_PRIORITY_MIN {
|
| 94 |
|
|
display "minimal interrupt priority"
|
| 95 |
|
|
flavor data
|
| 96 |
|
|
no_define
|
| 97 |
|
|
calculated 0xFFFF&\
|
| 98 |
|
|
((((1<
|
| 99 |
|
|
<<8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
|
| 100 |
|
|
}
|
| 101 |
|
|
|
| 102 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING {
|
| 103 |
|
|
display "Clocking"
|
| 104 |
|
|
flavor none
|
| 105 |
|
|
|
| 106 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_MAIN_CLOCK {
|
| 107 |
|
|
display "Main clock"
|
| 108 |
|
|
flavor none
|
| 109 |
|
|
|
| 110 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL {
|
| 111 |
|
|
display "PLL multiplier"
|
| 112 |
|
|
flavor data
|
| 113 |
|
|
legal_values 6 to 32767
|
| 114 |
|
|
default_value { 12 }
|
| 115 |
|
|
}
|
| 116 |
|
|
|
| 117 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV {
|
| 118 |
|
|
display "PLL divider"
|
| 119 |
|
|
flavor data
|
| 120 |
|
|
legal_values 1 to 32
|
| 121 |
|
|
default_value { 1 }
|
| 122 |
|
|
}
|
| 123 |
|
|
|
| 124 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_OUTPUT {
|
| 125 |
|
|
display "PLL output (MHz)"
|
| 126 |
|
|
flavor data
|
| 127 |
|
|
legal_values 275000000 to 550000000
|
| 128 |
|
|
calculated { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL *
|
| 129 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
|
| 130 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV }
|
| 131 |
|
|
description "
|
| 132 |
|
|
Normally the PLL output must be in the range of
|
| 133 |
|
|
275MHz to 550MHz."
|
| 134 |
|
|
}
|
| 135 |
|
|
|
| 136 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED {
|
| 137 |
|
|
display "CPU clock speed"
|
| 138 |
|
|
flavor data
|
| 139 |
|
|
calculated { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL *
|
| 140 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
|
| 141 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV /
|
| 142 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV }
|
| 143 |
|
|
description "
|
| 144 |
|
|
The core CPU clock speed is the PLL output divided
|
| 145 |
|
|
by the CPU clock divider."
|
| 146 |
|
|
|
| 147 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV {
|
| 148 |
|
|
display "CPU clock divider"
|
| 149 |
|
|
flavor data
|
| 150 |
|
|
legal_values 2 to 256
|
| 151 |
|
|
default_value { 3 }
|
| 152 |
|
|
description "
|
| 153 |
|
|
The CPU clock divider controls the division of
|
| 154 |
|
|
the PLL output before it is used by the CPU. When
|
| 155 |
|
|
the PLL is bypassed, the division may be by
|
| 156 |
|
|
1. When the PLL is running, the output must be
|
| 157 |
|
|
divided in order to bring the CPU clock frequency
|
| 158 |
|
|
(CCLK) within operating limits. An 8 bit divider
|
| 159 |
|
|
allows a range of options, including slowing
|
| 160 |
|
|
CPU operation to a low rate for temporary power
|
| 161 |
|
|
savings without turning off the PLL."
|
| 162 |
|
|
}
|
| 163 |
|
|
}
|
| 164 |
|
|
}
|
| 165 |
|
|
|
| 166 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_USB_CLOCK {
|
| 167 |
|
|
display "USB clock"
|
| 168 |
|
|
flavor none
|
| 169 |
|
|
|
| 170 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL {
|
| 171 |
|
|
display "PLL multiplier"
|
| 172 |
|
|
flavor data
|
| 173 |
|
|
calculated { 48000000 / CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ }
|
| 174 |
|
|
}
|
| 175 |
|
|
|
| 176 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV {
|
| 177 |
|
|
display "PLL divider"
|
| 178 |
|
|
flavor data
|
| 179 |
|
|
legal_values 1 2 3 4
|
| 180 |
|
|
default_value { 2 }
|
| 181 |
|
|
}
|
| 182 |
|
|
|
| 183 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_OUTPUT {
|
| 184 |
|
|
display "PLL output (MHz)"
|
| 185 |
|
|
flavor data
|
| 186 |
|
|
legal_values 156000000 to 320000000
|
| 187 |
|
|
calculated { 2 * 48000000 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV }
|
| 188 |
|
|
description "
|
| 189 |
|
|
Normally the PLL output must be in the range of
|
| 190 |
|
|
156MHz to 320MHz."
|
| 191 |
|
|
}
|
| 192 |
|
|
|
| 193 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_USB_CLOCK_SPEED {
|
| 194 |
|
|
display "USB clock speed"
|
| 195 |
|
|
flavor data
|
| 196 |
|
|
calculated { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL *
|
| 197 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
|
| 198 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV }
|
| 199 |
|
|
description "
|
| 200 |
|
|
The USB clock speed is the PLL1 output."
|
| 201 |
|
|
}
|
| 202 |
|
|
}
|
| 203 |
|
|
|
| 204 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT {
|
| 205 |
|
|
display "Clock-out option"
|
| 206 |
|
|
flavor bool
|
| 207 |
|
|
default_value 0
|
| 208 |
|
|
|
| 209 |
|
|
description "
|
| 210 |
|
|
This option enables clock output and selects clock source
|
| 211 |
|
|
and divider."
|
| 212 |
|
|
|
| 213 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SET {
|
| 214 |
|
|
display "Clock out register setting"
|
| 215 |
|
|
flavor data
|
| 216 |
|
|
calculated { (CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SRC |
|
| 217 |
|
|
((CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_DIV
|
| 218 |
|
|
- (1 && CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT)) << 4) |
|
| 219 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT ? 0x100 : 0x0 ))
|
| 220 |
|
|
}
|
| 221 |
|
|
}
|
| 222 |
|
|
|
| 223 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL {
|
| 224 |
|
|
display "Clock-out source selector"
|
| 225 |
|
|
flavor data
|
| 226 |
|
|
legal_values { "CPU clock" "Main osc." "RC osc." "USB clock" "RTC osc." }
|
| 227 |
|
|
default_value { "CPU clock" }
|
| 228 |
|
|
description "
|
| 229 |
|
|
Select clock out source."
|
| 230 |
|
|
}
|
| 231 |
|
|
|
| 232 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SRC {
|
| 233 |
|
|
display "Clock-out source"
|
| 234 |
|
|
flavor data
|
| 235 |
|
|
legal_values 0 1 2 3 4
|
| 236 |
|
|
calculated { CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "CPU clock" ? 0 :
|
| 237 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "Main osc." ? 1 :
|
| 238 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "RC osc." ? 2 :
|
| 239 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "USB clock" ? 3 :
|
| 240 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "RTC osc." ? 4 :
|
| 241 |
|
|
|
| 242 |
|
|
}
|
| 243 |
|
|
description "
|
| 244 |
|
|
Clock-out source index."
|
| 245 |
|
|
}
|
| 246 |
|
|
|
| 247 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_DIV {
|
| 248 |
|
|
display "Clock-out divider"
|
| 249 |
|
|
flavor data
|
| 250 |
|
|
legal_values 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
|
| 251 |
|
|
default_value { 10 }
|
| 252 |
|
|
}
|
| 253 |
|
|
}
|
| 254 |
|
|
|
| 255 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_PER_CLK {
|
| 256 |
|
|
display "Peripherial clocking"
|
| 257 |
|
|
flavor none
|
| 258 |
|
|
|
| 259 |
|
|
cdl_option CYGHWR_HAL_LPC_RTC_32768HZ {
|
| 260 |
|
|
display "RTC uses 32768 Hz clock"
|
| 261 |
|
|
flavor bool
|
| 262 |
|
|
calculated 1
|
| 263 |
|
|
description "
|
| 264 |
|
|
This option has to be defined for LPC microcontrollers
|
| 265 |
|
|
which RTC clock has no other clocking option than
|
| 266 |
|
|
RTC 32768 Hz oscilator."
|
| 267 |
|
|
}
|
| 268 |
|
|
|
| 269 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK {
|
| 270 |
|
|
display "CAN clock speed"
|
| 271 |
|
|
flavor data
|
| 272 |
|
|
calculated { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED /
|
| 273 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK_DIV }
|
| 274 |
|
|
description "
|
| 275 |
|
|
The CAN clock speed is the CPU clock output divided
|
| 276 |
|
|
by the CAN clock divider."
|
| 277 |
|
|
|
| 278 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK_DIV {
|
| 279 |
|
|
display "CAN clock divider"
|
| 280 |
|
|
flavor data
|
| 281 |
|
|
legal_values { 1 2 4 6 }
|
| 282 |
|
|
default_value { 2 }
|
| 283 |
|
|
description "
|
| 284 |
|
|
This divider selects the peripheral clock for
|
| 285 |
|
|
both CAN channels. The divider divides the CPU
|
| 286 |
|
|
clock to get the clock for the CAN peripherals."
|
| 287 |
|
|
}
|
| 288 |
|
|
}
|
| 289 |
|
|
|
| 290 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK {
|
| 291 |
|
|
display "ADC clock speed"
|
| 292 |
|
|
flavor data
|
| 293 |
|
|
calculated { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED /
|
| 294 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK_DIV }
|
| 295 |
|
|
description "
|
| 296 |
|
|
The ADC clock speed is the CPU clock output divided
|
| 297 |
|
|
by the ADC clock divider."
|
| 298 |
|
|
|
| 299 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK_DIV {
|
| 300 |
|
|
display "ADC clock divider"
|
| 301 |
|
|
flavor data
|
| 302 |
|
|
legal_values { 1 2 4 8 }
|
| 303 |
|
|
default_value { 2 }
|
| 304 |
|
|
description "
|
| 305 |
|
|
This divider selects the peripheral clock for
|
| 306 |
|
|
on-chip ADC. The ADC clock is the input clock
|
| 307 |
|
|
of the ADC peripheral."
|
| 308 |
|
|
}
|
| 309 |
|
|
}
|
| 310 |
|
|
|
| 311 |
|
|
for { set ::channel 0 } { $::channel < 3 } { incr ::channel } {
|
| 312 |
|
|
cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK {
|
| 313 |
|
|
display "I2C channel [set ::channel] clock speed"
|
| 314 |
|
|
flavor data
|
| 315 |
|
|
calculated CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED / \
|
| 316 |
|
|
CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK_DIV
|
| 317 |
|
|
description "
|
| 318 |
|
|
The I2C clock speed is the CPU clock output
|
| 319 |
|
|
divided by the I2C clock divider."
|
| 320 |
|
|
|
| 321 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK_DIV {
|
| 322 |
|
|
display "I2C channel [set ::channel] clock divider"
|
| 323 |
|
|
flavor data
|
| 324 |
|
|
legal_values { 1 2 4 8 }
|
| 325 |
|
|
default_value { 2 }
|
| 326 |
|
|
description "
|
| 327 |
|
|
This divider selects the peripheral clock
|
| 328 |
|
|
for I2C channel [set ::channel]. The divider
|
| 329 |
|
|
divides the CPU clock to get the clock for
|
| 330 |
|
|
the I2C peripheral."
|
| 331 |
|
|
}
|
| 332 |
|
|
}
|
| 333 |
|
|
}
|
| 334 |
|
|
}
|
| 335 |
|
|
}
|
| 336 |
|
|
|
| 337 |
|
|
cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
|
| 338 |
|
|
display "Clock interrupt ISR priority"
|
| 339 |
|
|
flavor data
|
| 340 |
|
|
calculated CYGNUM_HAL_IRQ_PRIORITY_MIN
|
| 341 |
|
|
description "
|
| 342 |
|
|
Set clock ISR priority to lowest priority."
|
| 343 |
|
|
}
|
| 344 |
|
|
|
| 345 |
|
|
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
|
| 346 |
|
|
display "Real-time clock constants"
|
| 347 |
|
|
flavor none
|
| 348 |
|
|
no_define
|
| 349 |
|
|
|
| 350 |
|
|
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
|
| 351 |
|
|
display "Real-time clock numerator"
|
| 352 |
|
|
flavor data
|
| 353 |
|
|
default_value 1000000000
|
| 354 |
|
|
}
|
| 355 |
|
|
|
| 356 |
|
|
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
|
| 357 |
|
|
display "Real-time clock denominator"
|
| 358 |
|
|
flavor data
|
| 359 |
|
|
default_value 100
|
| 360 |
|
|
}
|
| 361 |
|
|
|
| 362 |
|
|
cdl_option CYGNUM_HAL_RTC_PERIOD {
|
| 363 |
|
|
display "Real-time clock period"
|
| 364 |
|
|
flavor data
|
| 365 |
|
|
default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
|
| 366 |
|
|
description "
|
| 367 |
|
|
The period defined here is something of a fake, it is
|
| 368 |
|
|
expressed in terms of a notional 1MHz clock. The value
|
| 369 |
|
|
actually installed in the hardware is calculated from
|
| 370 |
|
|
the current settings of the clock generation hardware."
|
| 371 |
|
|
}
|
| 372 |
|
|
}
|
| 373 |
|
|
|
| 374 |
|
|
cdl_option CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION {
|
| 375 |
|
|
display "Utilize \".lpc17xx_misc\" section for HAL"
|
| 376 |
|
|
flavor bool
|
| 377 |
|
|
default_value { CYG_HAL_STARTUP == "ROM" }
|
| 378 |
|
|
active_if { CYG_HAL_STARTUP == "ROM" }
|
| 379 |
|
|
description "
|
| 380 |
|
|
Kinetis use FLASH location 0x2fc for FLASH Code Read Protection.
|
| 381 |
|
|
This leaves FLASH area below 0x2fc
|
| 382 |
|
|
out of standard linker sections. Special section
|
| 383 |
|
|
\".lpc17xx_misc\" provides linker access to this area.
|
| 384 |
|
|
Setting this option instructs linker to place some HAL
|
| 385 |
|
|
(variant/platform) \"misc.\" functions in this area."
|
| 386 |
|
|
}
|
| 387 |
|
|
|
| 388 |
|
|
cdl_interface CYGINT_HAL_LPC17XX_UART0 {
|
| 389 |
|
|
display "Platform has UART0 serial port"
|
| 390 |
|
|
description "
|
| 391 |
|
|
The platform has a socket on UART0."
|
| 392 |
|
|
}
|
| 393 |
|
|
|
| 394 |
|
|
cdl_interface CYGINT_HAL_LPC17XX_UART1 {
|
| 395 |
|
|
display "Platform has UART1 serial port"
|
| 396 |
|
|
description "
|
| 397 |
|
|
The platform has a socket on UART1."
|
| 398 |
|
|
}
|
| 399 |
|
|
|
| 400 |
|
|
cdl_interface CYGINT_HAL_LPC17XX_UART2 {
|
| 401 |
|
|
display "Platform has UART2 serial port"
|
| 402 |
|
|
description "
|
| 403 |
|
|
The platform has a socket on UART2."
|
| 404 |
|
|
}
|
| 405 |
|
|
|
| 406 |
|
|
cdl_interface CYGINT_HAL_LPC17XX_UART3 {
|
| 407 |
|
|
display "Platform has UART3 serial port"
|
| 408 |
|
|
description "
|
| 409 |
|
|
The platform has a socket on UART3."
|
| 410 |
|
|
}
|
| 411 |
|
|
|
| 412 |
|
|
cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_ENET {
|
| 413 |
|
|
display "LPC 17xx Ethernet check"
|
| 414 |
|
|
flavor bool
|
| 415 |
|
|
no_define
|
| 416 |
|
|
parent CYGPKG_DEVS_ETH_ARM_LPC2XXX
|
| 417 |
|
|
calculated {
|
| 418 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1766") ||
|
| 419 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1758") ||
|
| 420 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1764") ||
|
| 421 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1767") ||
|
| 422 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1768") ||
|
| 423 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1769")
|
| 424 |
|
|
}
|
| 425 |
|
|
requires {
|
| 426 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1766") ||
|
| 427 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1758") ||
|
| 428 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1764") ||
|
| 429 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1767") ||
|
| 430 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1768") ||
|
| 431 |
|
|
(CYGHWR_HAL_CORTEXM_LPC17XX == "1769")
|
| 432 |
|
|
}
|
| 433 |
|
|
description "
|
| 434 |
|
|
Check whether the chip has Ethernet controler."
|
| 435 |
|
|
}
|
| 436 |
|
|
|
| 437 |
|
|
cdl_component CYGPKG_HAL_CORTEXM_LPC17XX_OPTIONS {
|
| 438 |
|
|
display "Build options"
|
| 439 |
|
|
flavor none
|
| 440 |
|
|
description "
|
| 441 |
|
|
Package specific build options including control over
|
| 442 |
|
|
compiler flags used only in building this package."
|
| 443 |
|
|
|
| 444 |
|
|
cdl_option CYGPKG_HAL_CORTEXM_LPC17XX_CFLAGS_ADD {
|
| 445 |
|
|
display "Additional compiler flags"
|
| 446 |
|
|
flavor data
|
| 447 |
|
|
no_define
|
| 448 |
|
|
default_value { "" }
|
| 449 |
|
|
description "
|
| 450 |
|
|
This option modifies the set of compiler flags for
|
| 451 |
|
|
building the LPC17xx variant HAL package. These flags
|
| 452 |
|
|
are used in addition to the set of global flags."
|
| 453 |
|
|
}
|
| 454 |
|
|
|
| 455 |
|
|
cdl_option CYGPKG_HAL_CORTEXM_LPC17XX_CFLAGS_REMOVE {
|
| 456 |
|
|
display "Suppressed compiler flags"
|
| 457 |
|
|
flavor data
|
| 458 |
|
|
no_define
|
| 459 |
|
|
default_value { "" }
|
| 460 |
|
|
description "
|
| 461 |
|
|
This option modifies the set of compiler flags for
|
| 462 |
|
|
building the LPC17xx variant HAL package. These flags
|
| 463 |
|
|
are removed from the set of global flags if present."
|
| 464 |
|
|
}
|
| 465 |
|
|
}
|
| 466 |
|
|
}
|
| 467 |
|
|
|
| 468 |
|
|
# EOF hal_cortexm_lpc17xx.cdl
|
