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##==========================================================================
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##
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## hal_cortexm_stm32.cdl
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##
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## Cortex-M STM32 variant HAL configuration data
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##
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##==========================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 2008, 2011 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##==========================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): nickg
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## Contributors: jld
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## Date: 2008-07-30
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##
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######DESCRIPTIONEND####
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##
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##==========================================================================
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cdl_package CYGPKG_HAL_CORTEXM_STM32 {
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display "Cortex-M3 STM32 Variant"
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parent CYGPKG_HAL_CORTEXM
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hardware
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include_dir cyg/hal
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define_header hal_cortexm_stm32.h
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description "
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This package provides generic support for the ST Cortex-M based STM32
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microcontroller family.
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It is also necessary to select a variant and platform HAL package."
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compile hal_diag.c stm32_misc.c
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implements CYGINT_HAL_DEBUG_GDB_STUBS
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implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
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implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
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implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
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implements CYGINT_PROFILE_HAL_TIMER
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requires { CYGHWR_HAL_CORTEXM == "M3" }
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cdl_option CYGHWR_HAL_CORTEXM_STM32 {
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display "STM32 variant in use"
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flavor data
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default_value {"F103ZE"}
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legal_values {"F103RC" "F103VC" "F103ZC"
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"F103RD" "F103VD" "F103ZD"
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"F103RE" "F103VE" "F103ZE" }
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description "The STM32 has several variants, the main differences
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being in the size of on-chip FLASH and SRAM
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and numbers of some peripherals. This option
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allows the platform HAL to select the specific
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microcontroller fitted."
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}
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cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
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display "CPU priority levels"
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flavor data
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calculated 4
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description "This option defines the number of bits used to
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encode the exception priority levels that this
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variant of the Cortex-M CPU implements."
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}
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cdl_component CYGHWR_HAL_CORTEXM_STM32_CLOCK {
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display "Clock setup calculations"
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default_value 1
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cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE {
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display "PLL input source"
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flavor data
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default_value { "HSE" }
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legal_values { "HSI_HALF" "HSE" "HSE_HALF" }
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}
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cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL {
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display "PLL multiplier"
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flavor data
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default_value 9
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legal_values 2 to 16
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}
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cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV {
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display "HCLK divider"
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flavor data
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default_value 1
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legal_values { 1 2 4 8 16 64 128 256 512 }
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}
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cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV {
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display "PCLK1 divider"
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flavor data
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default_value 2
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legal_values { 1 2 4 8 16 }
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}
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cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV {
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display "PCLK2 divider"
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flavor data
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default_value 1
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legal_values { 1 2 4 8 16 }
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}
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}
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cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
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display "Clock interrupt ISR priority"
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flavor data
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calculated 0xE0
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description "Set clock ISR priority to lowest priority."
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}
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cdl_component CYGNUM_HAL_RTC_CONSTANTS {
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display "Real-time clock constants"
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flavor none
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no_define
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cdl_option CYGNUM_HAL_RTC_NUMERATOR {
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display "Real-time clock numerator"
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flavor data
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default_value 1000000000
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}
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cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
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display "Real-time clock denominator"
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flavor data
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default_value 100
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}
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cdl_option CYGNUM_HAL_RTC_PERIOD {
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display "Real-time clock period"
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flavor data
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default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
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description "The period defined here is something of a fake, it is expressed
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in terms of a notional 1MHz clock. The value actually installed
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in the hardware is calculated from the current settings of the
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clock generation hardware."
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}
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}
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cdl_interface CYGINT_HAL_STM32_UART0 {
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display "Platform has UART0 serial port"
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description "The platform has a socket on UART0."
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}
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cdl_interface CYGINT_HAL_STM32_UART1 {
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display "Platform has UART1 serial port"
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description "The platform has a socket on UART1."
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}
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cdl_interface CYGINT_HAL_STM32_UART2 {
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display "Platform has UART2 serial port"
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description "The platform has a socket on UART2."
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}
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cdl_interface CYGINT_HAL_STM32_UART3 {
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display "Platform has UART3 serial port"
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description "The platform has a socket on UART3."
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}
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cdl_interface CYGINT_HAL_STM32_UART4 {
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display "Platform has UART4 serial port"
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description "The platform has a socket on UART4."
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}
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cdl_option CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER {
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display "Use TIM2 for gprof profiling"
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active_if CYGPKG_PROFILE_GPROF
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flavor bool
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default_value 1
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implements CYGINT_PROFILE_HAL_TIMER
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implements CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED
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description "
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The STM32 variant HAL can provide support for gprof-based
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profiling. This uses timer TIM2 to generate regular interrupts,
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and the interrupt handler records the PC at the time of the
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interrupt. Disable this option if you wish to provide
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an alternative profiling timer implementation."
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}
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cdl_component CYGPKG_HAL_CORTEXM_STM32_OPTIONS {
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display "Build options"
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flavor none
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description "
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Package specific build options including control over
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compiler flags used only in building this package."
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cdl_option CYGPKG_HAL_CORTEXM_STM32_CFLAGS_ADD {
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display "Additional compiler flags"
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flavor data
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no_define
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default_value { "" }
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description "
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This option modifies the set of compiler flags for
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building the STM32 variant HAL package. These flags are used
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in addition to the set of global flags."
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}
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cdl_option CYGPKG_HAL_CORTEXM_STM32_CFLAGS_REMOVE {
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display "Suppressed compiler flags"
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flavor data
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no_define
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default_value { "" }
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description "
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This option modifies the set of compiler flags for
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building the STM32 variant HAL package. These flags are removed from
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the set of global flags if present."
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}
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}
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cdl_option CYGPKG_HAL_CORTEXM_STM32_TESTS {
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display "STM32 tests"
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active_if CYGPKG_KERNEL
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flavor data
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no_define
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calculated { "tests/timers" }
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description "
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This option specifies the set of tests for the STM32 HAL."
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}
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}
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