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skrzyp |
#ifndef CYGONCE_HAL_IMP_INTR_H
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#define CYGONCE_HAL_IMP_INTR_H
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//==========================================================================
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//
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// var_intr.h
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//
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// MB91301 Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): larsi
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// Contributors: larsi
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// Date: 2006-07-14
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// Purpose: MB91301 Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock for variants of the MB91301
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// architecture.
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//
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// Usage:
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// #include <cyg/hal/imp_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/plf_intr.h>
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//--------------------------------------------------------------------------
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// Interrupt vectors.
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#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#define CYGNUM_HAL_INTERRUPT_0 16
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#define CYGNUM_HAL_INTERRUPT_1 17
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#define CYGNUM_HAL_INTERRUPT_2 18
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#define CYGNUM_HAL_INTERRUPT_3 19
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#define CYGNUM_HAL_INTERRUPT_4 20
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#define CYGNUM_HAL_INTERRUPT_5 21
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#define CYGNUM_HAL_INTERRUPT_6 22
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#define CYGNUM_HAL_INTERRUPT_7 23
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#define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER0 24
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#define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER1 25
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#define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER2 26
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#define CYGNUM_HAL_INTERRUPT_UART0_RX 27
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#define CYGNUM_HAL_INTERRUPT_UART1_RX 28
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#define CYGNUM_HAL_INTERRUPT_UART2_RX 29
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#define CYGNUM_HAL_INTERRUPT_UART0_TX 30
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#define CYGNUM_HAL_INTERRUPT_UART1_TX 31
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#define CYGNUM_HAL_INTERRUPT_UART2_TX 32
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#define CYGNUM_HAL_INTERRUPT_DMAC0 33
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#define CYGNUM_HAL_INTERRUPT_DMAC1 34
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#define CYGNUM_HAL_INTERRUPT_DMAC2 35
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#define CYGNUM_HAL_INTERRUPT_DMAC3 36
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#define CYGNUM_HAL_INTERRUPT_DMAC4 37
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#define CYGNUM_HAL_INTERRUPT_AD 38
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#define CYGNUM_HAL_INTERRUPT_PPG0 39
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#define CYGNUM_HAL_INTERRUPT_PPG1 40
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#define CYGNUM_HAL_INTERRUPT_PPG2 41
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#define CYGNUM_HAL_INTERRUPT_PPG3 42
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 43
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#define CYGNUM_HAL_INTERRUPT_UTIMER0 44
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#define CYGNUM_HAL_INTERRUPT_UTIMER1 45
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#define CYGNUM_HAL_INTERRUPT_UTIMER2 46
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#define CYGNUM_HAL_INTERRUPT_TIMEBASE_OVERFLOW 47
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#define CYGNUM_HAL_INTERRUPT_I2C0 48
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#define CYGNUM_HAL_INTERRUPT_I2C1 49
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 50
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 51
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#define CYGNUM_HAL_INTERRUPT_FREERUN_TIMER 52
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#define CYGNUM_HAL_INTERRUPT_ICU0 53
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#define CYGNUM_HAL_INTERRUPT_ICU1 54
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#define CYGNUM_HAL_INTERRUPT_ICU2 55
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#define CYGNUM_HAL_INTERRUPT_ICU3 56
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 57
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 58
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 59
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 60
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 61
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// system reserved #define CYGNUM_HAL_INTERRUPT_ 62
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#define CYGNUM_HAL_INTERRUPT_DELAYED_IRQ 63
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// The interrupt vector used by the RTC, aka tick timer
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_RELOAD_TIMER1
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Interrupt controller access.
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// currently only external interrupts are masked using the external
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// interrupt controller. This means only vectors 16 to 23 are valid.
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// Other interrupts may be masked in the future
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// using the mask mechanism for interrupt levels, if needed.
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#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#define CYG_HAL_FR30_MB91301_ENIR 0x41
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#define CYG_HAL_FR30_MB91301_EIRR 0x40
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#define CYG_HAL_FR30_MB91301_ELVR 0x42
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#define CYG_HAL_FR30_MB91301_ICR00 0x440
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// Array which stores the configured priority levels for the configured
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// interrupts.
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// this will be useful, if we implement masking of non external interrupts
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// externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
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#define HAL_INTERRUPT_MASK( _vector_ ) \
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{ \
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CYG_WORD32 _ilr_; \
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if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) && \
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(_vector_ <= CYGNUM_HAL_INTERRUPT_0)){ \
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HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \
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_ilr_ &= ~(1<<((_vector_)>>4)); \
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HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \
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} \
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/* Handle RTC masking special */ \
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if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC) \
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asm volatile("ldi:8 #0x57, r0;\n" \
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"bandl #0x7, @r0;\n" \
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: : :"r0"); \
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}
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#define HAL_INTERRUPT_UNMASK( _vector_ ) \
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{ \
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CYG_WORD32 _ilr_; \
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if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) && \
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(_vector_ <= CYGNUM_HAL_INTERRUPT_0)){ \
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HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \
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_ilr_ |= (1<<((_vector_)>>4)); \
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HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \
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} \
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/* Handle RTC unmasking special */ \
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if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC) \
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asm volatile("ldi:8 #0x57, r0;\n" \
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"borl #0x8, @r0;\n" \
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: : :"r0"); \
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}
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
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{ \
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CYG_WORD32 _ilr_; \
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if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) && \
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(_vector_ <= CYGNUM_HAL_INTERRUPT_0)){ \
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HAL_READ_UINT8( CYG_HAL_FR30_MB91301_EIRR, _ilr_ ); \
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_ilr_ &= ~(1<<((_vector_)>>4)); \
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HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_EIRR, _ilr_ ); \
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} \
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/* Handle RTC acknowledging special */ \
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if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC) \
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asm volatile("ldi:8 #0x57, r0;\n" \
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"bandl #0xb, @r0;\n" \
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: : :"r0"); \
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}
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
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{ \
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/* subtract 15 from vector */ \
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cyg_uint32 _v_ = _vector_ >> 4; \
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cyg_uint16 _val_ = 0; \
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cyg_uint16 _reg_; \
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\
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if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) && \
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(_vector_ <= CYGNUM_HAL_INTERRUPT_0)){ \
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\
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/* set bits according to requirements */ \
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if( _up_ ) _val_ |= 1; \
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if( !(_level_) ) _val_ |= 2; \
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\
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/* get old ELVR */ \
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HAL_READ_UINT16( CYG_HAL_FR30_MB91301_ELVR, _reg_ ); \
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\
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/* clear old value and set new */ \
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_reg_ &= ~(3 << _v_); \
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_reg_ |= _val_ << _v_; \
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HAL_WRITE_UINT16( CYG_HAL_FR30_MB91301_ELVR, _reg_ ); \
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} \
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}
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
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{ \
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/* subtract 15 from vector */ \
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cyg_uint32 _v_ = _vector_ >> 4; \
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CYG_WORD32 _ilr_; \
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/* HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ICR00 + _vector_, _ilr_ );*/ \
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/* reading before writing is only needed, if UINT8 writing is not */ \
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/* possible to IO 0x440 */ \
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_ilr_ = (_level_); \
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HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ICR00 + _vector_, _ilr_ ); \
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/* for later use: */ \
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/* hal_interrupt_level[_vector_] = _level_; */ \
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}
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#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
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#endif
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//--------------------------------------------------------------------------
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// Clock control registers
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// MB91301 series has 3 built-in timer channels.
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// Timer 2 is used for delay and timer 1 for RTC/*delay*/.
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// Timer 0 and 1 can activate DMA and this feature is propably needed by
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// the application. Timer 0 is free to use by the application.
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#define CYG_HAL_FR30_DLY_TMCSR 0x5e
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#define CYG_HAL_FR30_DLY_TMR 0x5a
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#define CYG_HAL_FR30_DLY_TMRLR 0x58
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#define CYG_HAL_FR30_RTC_TMCSR 0x56
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#define CYG_HAL_FR30_RTC_TMR 0x52
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#define CYG_HAL_FR30_RTC_TMRLR 0x50
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//--------------------------------------------------------------------------
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// Control-C support.
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#if defined(CYGDBG_HAL_FR30_DEBUG_GDB_CTRLC_SUPPORT)
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#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART
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externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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#define HAL_CTRLC_ISR hal_ctrlc_isr
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#endif
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_IMP_INTR_H
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// End of imp_intr.h
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