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//==========================================================================
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//
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// fr500.h
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//
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// HAL misc board support definitions for Fujitsu FR5xx chips
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors: gthomas
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// Date: 2001-09-07
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// Purpose: Platform register definitions
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#ifndef __HAL_FR500_H__
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#define __HAL_FR500_H__ 1
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// SDRAM Controller
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#define _FRV550_SDRAM_CTL 0xFEFF0200 // Control
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#define _FRV550_SDRAM_AMC 0xFEFF0204 // Access mode control
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#define _FRV550_SDRAM_MS 0xFEFF0208 // Mode select
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#define _FRV550_SDRAM_CFG 0xFEFF020C // Configuration
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#define _FRV550_SDRAM_AN 0xFEFF0210 // Address number
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#define _FRV550_SDRAM_STS 0xFEFF0214 // Status
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#define _FRV550_SDRAM_RCN 0xFEFF0218 // Refresh control
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#define _FRV550_SDRAM_ART 0xFEFF021C // Auto-refresh timer
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#define _FRV550_SDRAM_ARS0 0xFEFF0100 // Address #0
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#define _FRV550_SDRAM_ARS1 0xFEFF0104 // Address #1
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#define _FRV550_SDRAM_ARS2 0xFEFF0108 // Address #2
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#define _FRV550_SDRAM_ARS3 0xFEFF010C // Address #3
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#define _FRV550_SDRAM_AMK0 0xFEFF0110 // Address mask #0
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#define _FRV550_SDRAM_AMK1 0xFEFF0114 // Address mask #1
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#define _FRV550_SDRAM_AMK2 0xFEFF0118 // Address mask #2
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#define _FRV550_SDRAM_AMK3 0xFEFF011C // Address mask #3
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// Local bus control
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#define _FRV550_LBUS_CP 0xFEFF1000 // Controller protect
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#define _FRV550_LBUS_GCR 0xFEFF1010 // General configuration
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#define _FRV550_LBUS_EST 0xFEFF1020 // Error status
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#define _FRV550_LBUS_EAD 0xFEFF1028 // Error address
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#define _FRV550_LBUS_MAICR 0xFEFF1030 // Master access interval control
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#define _FRV550_LBUS_EMBR 0xFEFF1040 // External master base
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#define _FRV550_LBUS_EMAM 0xFEFF1048 // External master address mask
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#define _FRV550_LBUS_CR0 0xFEFF1100 // Configuration - space #0
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#define _FRV550_LBUS_CR1 0xFEFF1108 // Configuration - space #1
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#define _FRV550_LBUS_CR2 0xFEFF1110 // Configuration - space #2
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#define _FRV550_LBUS_CR3 0xFEFF1118 // Configuration - space #3
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#define _FRV550_LBUS_CR4 0xFEFF1120 // Configuration - space #4
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#define _FRV550_LBUS_CR5 0xFEFF1128 // Configuration - space #5
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#define _FRV550_LBUS_CR6 0xFEFF1130 // Configuration - space #6
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#define _FRV550_LBUS_CR7 0xFEFF1138 // Configuration - space #7
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#define _FRV550_LBUS_BR0 0xFEFF1C00 // Slave - base address #0
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#define _FRV550_LBUS_BR1 0xFEFF1C08 // Slave - base address #1
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#define _FRV550_LBUS_BR2 0xFEFF1C10 // Slave - base address #2
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#define _FRV550_LBUS_BR3 0xFEFF1C18 // Slave - base address #3
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#define _FRV550_LBUS_BR4 0xFEFF1C20 // Slave - base address #4
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#define _FRV550_LBUS_BR5 0xFEFF1C28 // Slave - base address #5
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#define _FRV550_LBUS_BR6 0xFEFF1C30 // Slave - base address #6
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#define _FRV550_LBUS_BR7 0xFEFF1C38 // Slave - base address #7
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#define _FRV550_LBUS_AM0 0xFEFF1D00 // Slave - address mask #0
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#define _FRV550_LBUS_AM1 0xFEFF1D08 // Slave - address mask #1
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#define _FRV550_LBUS_AM2 0xFEFF1D10 // Slave - address mask #2
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#define _FRV550_LBUS_AM3 0xFEFF1D18 // Slave - address mask #3
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#define _FRV550_LBUS_AM4 0xFEFF1D20 // Slave - address mask #4
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#define _FRV550_LBUS_AM5 0xFEFF1D28 // Slave - address mask #5
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#define _FRV550_LBUS_AM6 0xFEFF1D30 // Slave - address mask #6
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#define _FRV550_LBUS_AM7 0xFEFF1D38 // Slave - address mask #7
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// Reset register
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#define _FRV550_HW_RESET 0xFEFFF500 // Hardware reset
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// Some GPIO magic
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#define _FRV550_GPIO_SIR 0xFEFFF410 // Special input signals
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#define _FRV550_GPIO_SOR 0xFEFFF418 // Special output signals
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#endif // __HAL_FR500_H__
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