| 1 |
786 |
skrzyp |
#ifndef _CYGONCE_PLATFORM_INC_H_
|
| 2 |
|
|
#define _CYGONCE_PLATFORM_INC_H_
|
| 3 |
|
|
// #========================================================================
|
| 4 |
|
|
// #
|
| 5 |
|
|
// # platform.inc
|
| 6 |
|
|
// #
|
| 7 |
|
|
// # Fujitsu platform specific setups (assembler macros)
|
| 8 |
|
|
// #
|
| 9 |
|
|
// #========================================================================
|
| 10 |
|
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
| 11 |
|
|
// -------------------------------------------
|
| 12 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 13 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
| 14 |
|
|
//
|
| 15 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 16 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 17 |
|
|
// Software Foundation; either version 2 or (at your option) any later
|
| 18 |
|
|
// version.
|
| 19 |
|
|
//
|
| 20 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
| 21 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 22 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 23 |
|
|
// for more details.
|
| 24 |
|
|
//
|
| 25 |
|
|
// You should have received a copy of the GNU General Public License
|
| 26 |
|
|
// along with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 27 |
|
|
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 28 |
|
|
//
|
| 29 |
|
|
// As a special exception, if other files instantiate templates or use
|
| 30 |
|
|
// macros or inline functions from this file, or you compile this file
|
| 31 |
|
|
// and link it with other works to produce a work based on this file,
|
| 32 |
|
|
// this file does not by itself cause the resulting work to be covered by
|
| 33 |
|
|
// the GNU General Public License. However the source code for this file
|
| 34 |
|
|
// must still be made available in accordance with section (3) of the GNU
|
| 35 |
|
|
// General Public License v2.
|
| 36 |
|
|
//
|
| 37 |
|
|
// This exception does not invalidate any other reasons why a work based
|
| 38 |
|
|
// on this file might be covered by the GNU General Public License.
|
| 39 |
|
|
// -------------------------------------------
|
| 40 |
|
|
// ####ECOSGPLCOPYRIGHTEND####
|
| 41 |
|
|
// #========================================================================
|
| 42 |
|
|
// ######DESCRIPTIONBEGIN####
|
| 43 |
|
|
// #
|
| 44 |
|
|
// # Author(s): gthomas
|
| 45 |
|
|
// # Contributors: gthomas
|
| 46 |
|
|
// # Date: 2001-09-16
|
| 47 |
|
|
// # Purpose: Fujitsu (FRV400) platform specific setups
|
| 48 |
|
|
// # Description: This file defines various macros used by the generic
|
| 49 |
|
|
// # HAL startup code.
|
| 50 |
|
|
// #
|
| 51 |
|
|
// #####DESCRIPTIONEND####
|
| 52 |
|
|
// #
|
| 53 |
|
|
// #========================================================================
|
| 54 |
|
|
|
| 55 |
|
|
// Display a value in the system LEDs
|
| 56 |
|
|
.macro LED n
|
| 57 |
|
|
sethi #(_FRV400_MB_LEDS>>16),gr15
|
| 58 |
|
|
setlo #(_FRV400_MB_LEDS&0xFFFF),gr15
|
| 59 |
|
|
setlos #\n,gr14
|
| 60 |
|
|
not gr14,gr14
|
| 61 |
|
|
sti gr14,@(gr15,0)
|
| 62 |
|
|
.endm
|
| 63 |
|
|
|
| 64 |
|
|
// Platform initialization - only the necessary bits required to get the
|
| 65 |
|
|
// board started from a cold reset.
|
| 66 |
|
|
.macro platform_init
|
| 67 |
|
|
li 0x7FFF,gr4 // First, a good long spin
|
| 68 |
|
|
05: nop
|
| 69 |
|
|
subi gr4,1,gr4
|
| 70 |
|
|
cmp gr4,gr0,icc0
|
| 71 |
|
|
bne icc0,0,05b
|
| 72 |
|
|
call 10f // position independent way to get @_platform_tab
|
| 73 |
|
|
_platform_tab:
|
| 74 |
|
|
//
|
| 75 |
|
|
// SDRAM setups
|
| 76 |
|
|
//
|
| 77 |
|
|
.long _FRV400_SDRAM_BR0,0x00000000 // SDRAM 0x0XXXXXXX
|
| 78 |
|
|
.long _FRV400_SDRAM_AM0,0x0FF00000
|
| 79 |
|
|
|
| 80 |
|
|
//
|
| 81 |
|
|
// LOCAL bus setups
|
| 82 |
|
|
//
|
| 83 |
|
|
.long _FRV400_LBUS_CR0,0x03010D01 // ROM/FLASH 0xFF000000..0xFFFFFFFF
|
| 84 |
|
|
// 16 bits wide, 13 wait states, 1 idle
|
| 85 |
|
|
|
| 86 |
|
|
.long _FRV400_LBUS_BR1,0x10000000 // PCI bridge 0x10000000..0x100FFFFF
|
| 87 |
|
|
.long _FRV400_LBUS_AM1,0x000FFFFF
|
| 88 |
|
|
.long _FRV400_LBUS_CR1,0x00000000
|
| 89 |
|
|
|
| 90 |
|
|
.long _FRV400_LBUS_BR2,0x20000000 // SRAM, FPGA, PCI 0x20000000..0x2FFFFFFF
|
| 91 |
|
|
.long _FRV400_LBUS_AM2,0x0FFFFFFF
|
| 92 |
|
|
.long _FRV400_LBUS_CR2,0x00000000
|
| 93 |
|
|
|
| 94 |
|
|
.long _FRV400_LBUS_BR3,0x00000000 // SDRAM?
|
| 95 |
|
|
.long _FRV400_LBUS_AM3,0xFFFFFFFF
|
| 96 |
|
|
.long _FRV400_LBUS_CR3,0x00000F07
|
| 97 |
|
|
|
| 98 |
|
|
.long _FRV400_GPIO_SIR,0x000c954f // Routing for Rx0, Rx1, CTS
|
| 99 |
|
|
.long _FRV400_GPIO_SOR,0x00036ab0 // Routing for Tx0, Tx1, RTS, TOUT0, TOUT1
|
| 100 |
|
|
|
| 101 |
|
|
.long _FRV400_SDRAM_CTL,0x05022000 // SDRAM mode/control
|
| 102 |
|
|
.long _FRV400_SDRAM_AN0,0x00010101
|
| 103 |
|
|
.long _FRV400_SDRAM_ART,0x00000820
|
| 104 |
|
|
.long _FRV400_SDRAM_RCN,0x00000000
|
| 105 |
|
|
.long _FRV400_SDRAM_MS, 0x00020200
|
| 106 |
|
|
.long _FRV400_SDRAM_CFG,0x80000000
|
| 107 |
|
|
|
| 108 |
|
|
//? .long _FRV400_CLK_CTRL,0x00000001 // External clock divisor (/2)
|
| 109 |
|
|
|
| 110 |
|
|
//
|
| 111 |
|
|
// PCI controller/bridge
|
| 112 |
|
|
//
|
| 113 |
|
|
.long _FRV400_PCI_SLBUS_CONFIG, 0x000800E2 // This matches the docs
|
| 114 |
|
|
// .long _FRV400_PCI_SLBUS_CONFIG, 0x000000E0 // This matches the samples
|
| 115 |
|
|
.long _FRV400_PCI_ECS0_CONFIG, 0x00000000
|
| 116 |
|
|
.long _FRV400_PCI_ECS1_CONFIG, 0x000003C1
|
| 117 |
|
|
.long _FRV400_PCI_ECS2_CONFIG, 0x000001C1
|
| 118 |
|
|
.long _FRV400_PCI_ECS0_RANGE, 0x00000000
|
| 119 |
|
|
.long _FRV400_PCI_ECS0_ADDR, 0x00000000
|
| 120 |
|
|
.long _FRV400_PCI_ECS1_RANGE, 0x00007FFE
|
| 121 |
|
|
.long _FRV400_PCI_ECS1_ADDR, 0x08108000
|
| 122 |
|
|
.long _FRV400_PCI_ECS2_RANGE, 0x00007FFE
|
| 123 |
|
|
.long _FRV400_PCI_ECS2_ADDR, 0x08100000
|
| 124 |
|
|
.long _FRV400_PCI_PCIIO_RANGE, 0x0001FFFE
|
| 125 |
|
|
.long _FRV400_PCI_PCIIO_ADDR, 0x00120000
|
| 126 |
|
|
.long _FRV400_PCI_PCIMEM_RANGE, 0x0003FFFE
|
| 127 |
|
|
.long _FRV400_PCI_PCIMEM_ADDR, 0x00140000
|
| 128 |
|
|
.long _FRV400_PCI_PCIIO_PCI_ADDR, 0x24000001
|
| 129 |
|
|
.long _FRV400_PCI_PCIMEM_PCI_ADDR, 0x28000000
|
| 130 |
|
|
.long _FRV400_MB_PCI_ARBITER, 0x00000001
|
| 131 |
|
|
.long _FRV400_MB_PCI_ARBITER, 0x00000001
|
| 132 |
|
|
|
| 133 |
|
|
.long _FRV400_PCI_SLBUS_CONFIG, 0x800800E2
|
| 134 |
|
|
// .long _FRV400_PCI_SLBUS_CONFIG, 0x800000E0
|
| 135 |
|
|
.long 0
|
| 136 |
|
|
.long _FRV400_SDRAM_STS
|
| 137 |
|
|
|
| 138 |
|
|
10: movsg lr,gr4 // _platform_tab -> list of initializations
|
| 139 |
|
|
20: ldi @(gr4,0),gr5 // Register
|
| 140 |
|
|
ldi @(gr4,4),gr6 // Value
|
| 141 |
|
|
cmp gr5,gr0,icc0 // End of list?
|
| 142 |
|
|
beq icc0,0,30f
|
| 143 |
|
|
sti gr6,@(gr5,0)
|
| 144 |
|
|
addi gr4,2*4,gr4
|
| 145 |
|
|
bra 20b // Next item
|
| 146 |
|
|
30: ldi @(gr6,0),gr5 // gr6 == _FRV400_SDRAM_STS
|
| 147 |
|
|
cmp gr5,gr0,icc0
|
| 148 |
|
|
bne icc0,0,30b // Wait for SDRAM ready
|
| 149 |
|
|
|
| 150 |
|
|
//
|
| 151 |
|
|
// Note: it is unclear from the documentation if this works at all. There is no
|
| 152 |
|
|
// description of how these registers are searched and what would happen if they
|
| 153 |
|
|
// overlap. If it turns out that they are not allowed to overlap, then this setup
|
| 154 |
|
|
// will have to be restructured.
|
| 155 |
|
|
//
|
| 156 |
|
|
li 0x03F0003D,gr4 // Set 0x03FXXXXX supervisor only, no cache - PCI window (1MB)
|
| 157 |
|
|
movgs gr4,DAMPR0
|
| 158 |
|
|
li 0x000000C9,gr4 // Set 0x0XXXXXXX supervisor only, cache - SDRAM
|
| 159 |
|
|
movgs gr4,DAMPR1
|
| 160 |
|
|
li 0x200000BD,gr4 // Set 0x2XXXXXXX supervisor only, no cache - Motherboard resources
|
| 161 |
|
|
movgs gr4,DAMPR6
|
| 162 |
|
|
li 0x100000BD,gr4 // Set 0x1XXXXXXX supervisor only, no cache - PCI bridge
|
| 163 |
|
|
movgs gr4,DAMPR7
|
| 164 |
|
|
movsg hsr0,gr4
|
| 165 |
|
|
li (1<<25),gr5 // Enable data MMU
|
| 166 |
|
|
or gr4,gr5,gr4
|
| 167 |
|
|
movgs gr4,hsr0
|
| 168 |
|
|
|
| 169 |
|
|
.endm
|
| 170 |
|
|
|
| 171 |
|
|
#endif // _CYGONCE_PLATFORM_INC_H_
|
