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//==========================================================================
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//
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// frv400_misc.c
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//
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// HAL misc board support code for Fujitsu MB93091 ( FR-V 400)
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors: gthomas
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// Date: 2001-09-07
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// Purpose: HAL board support
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// Description: Implementations of HAL board interfaces
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#include <pkgconf/hal.h>
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#include <pkgconf/system.h>
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#include CYGBLD_HAL_PLATFORM_H
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#include <cyg/infra/cyg_type.h> // base types
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/infra/diag.h> // diag_printf() and friends
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#include <cyg/hal/hal_io.h> // IO macros
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#include <cyg/hal/hal_arch.h> // Register state info
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/hal_intr.h> // Interrupt names
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#include <cyg/hal/hal_cache.h>
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#include <cyg/hal/frv400.h> // Hardware definitions
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#include <cyg/hal/hal_if.h> // calling interface API
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#include <pkgconf/io_pci.h>
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#include <cyg/io/pci_hw.h>
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#include <cyg/io/pci.h>
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static cyg_uint32 _period;
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void hal_clock_initialize(cyg_uint32 period)
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{
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_period = period;
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// Set timer #1 to run in terminal count mode for period
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HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL1|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
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HAL_WRITE_UINT8(_FRV400_TCSR1, period & 0xFF);
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HAL_WRITE_UINT8(_FRV400_TCSR1, period >> 8);
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// Configure interrupt
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HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_TIMER1, 1, 1); // Interrupt when TOUT1 is high
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}
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void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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{
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cyg_int16 offset;
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cyg_uint8 _val;
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// Latch & read counter from timer #1
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HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_LATCH|_FRV400_TCTR_RLOHI|_FRV400_TCTR_SEL1);
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HAL_READ_UINT8(_FRV400_TCSR1, _val);
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offset = _val;
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HAL_READ_UINT8(_FRV400_TCSR1, _val);
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offset |= _val << 8; // This will be the number of clocks beyond 0
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period += offset;
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// Reinitialize with adjusted count
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// Set timer #1 to run in terminal count mode for period
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HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL1|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
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HAL_WRITE_UINT8(_FRV400_TCSR1, period & 0xFF);
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HAL_WRITE_UINT8(_FRV400_TCSR1, period >> 8);
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}
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// Read the current value of the clock, returning the number of hardware "ticks"
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// that have occurred (i.e. how far away the current value is from the start)
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void hal_clock_read(cyg_uint32 *pvalue)
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{
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cyg_int16 offset;
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cyg_uint8 _val;
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// Latch & read counter from timer #1
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HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_LATCH|_FRV400_TCTR_RLOHI|_FRV400_TCTR_SEL1);
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HAL_READ_UINT8(_FRV400_TCSR1, _val);
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offset = _val;
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HAL_READ_UINT8(_FRV400_TCSR1, _val);
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offset |= _val << 8;
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// 'offset' is the current timer value
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*pvalue = _period - offset;
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}
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// Delay for some number of useconds.
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// Assumptions:
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// Use timer #2
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// Min granularity is 10us
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#define _MIN_DELAY 10
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void hal_delay_us(int us)
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{
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cyg_uint8 stat;
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int timeout;
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while (us >= _MIN_DELAY) {
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us -= _MIN_DELAY;
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// Set timer #2 to run in terminal count mode for _MIN_DELAY us
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HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL2|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
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HAL_WRITE_UINT8(_FRV400_TCSR2, _MIN_DELAY & 0xFF);
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HAL_WRITE_UINT8(_FRV400_TCSR2, _MIN_DELAY >> 8);
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timeout = 100000;
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// Wait for TOUT to indicate terminal count reached
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do {
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HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_RB|_FRV400_TCTR_RB_NCOUNT|_FRV400_TCTR_RB_CTR2);
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HAL_READ_UINT8(_FRV400_TCSR2, stat);
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if (--timeout == 0) break;
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} while ((stat & _FRV400_TCxSR_TOUT) == 0);
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}
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}
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//
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// Early stage hardware initialization
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// Some initialization has already been done before we get here. For now
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// just set up the interrupt environment.
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long _system_clock; // Calculated clock frequency
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void hal_hardware_init(void)
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{
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cyg_uint32 clk;
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// Set up interrupt controller
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HAL_WRITE_UINT16(_FRV400_IRC_MASK, 0xFFFE); // All masked
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HAL_WRITE_UINT16(_FRV400_IRC_RC, 0xFFFE); // All cleared
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HAL_WRITE_UINT16(_FRV400_IRC_IRL, 0x10); // Clear IRL (interrupt request latch)
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// Onboard FPGA interrupts
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HAL_WRITE_UINT16(_FRV400_FPGA_CONTROL, _FRV400_FPGA_CONTROL_IRQ); // Enable IRQ registers
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HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, // Set up for LAN, PCI INTx
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0x7FFE &
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~(_FRV400_FPGA_IRQ_LAN |
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_FRV400_FPGA_IRQ_INTA |
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_FRV400_FPGA_IRQ_INTB |
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_FRV400_FPGA_IRQ_INTC |
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_FRV400_FPGA_IRQ_INTD)
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);
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HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_LEVELS, // Set up for LAN, PCI INTx
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0x7FFE &
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~(_FRV400_FPGA_IRQ_LAN |
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_FRV400_FPGA_IRQ_INTA |
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_FRV400_FPGA_IRQ_INTB |
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_FRV400_FPGA_IRQ_INTC |
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_FRV400_FPGA_IRQ_INTD)
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);
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HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 0); // Level, low
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// Set up system clock
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HAL_READ_UINT32(_FRV400_MB_CLKSW, clk);
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_system_clock = (((clk&0xFF) * 125 * 2) / 240) * 1000000;
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// Set scalers to achieve 1us resolution in timer
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HAL_WRITE_UINT8(_FRV400_TPRV, _system_clock / (1000*1000));
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HAL_WRITE_UINT8(_FRV400_TCKSL0, 0x80);
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HAL_WRITE_UINT8(_FRV400_TCKSL1, 0x80);
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HAL_WRITE_UINT8(_FRV400_TCKSL2, 0x80);
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hal_if_init();
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// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
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hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
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_frv400_pci_init();
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}
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//
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// Interrupt control
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//
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void hal_interrupt_mask(int vector)
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{
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cyg_uint16 _mask;
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_LAN:
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HAL_READ_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
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_mask |= _FRV400_FPGA_IRQ_LAN;
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HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
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break;
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}
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HAL_READ_UINT16(_FRV400_IRC_MASK, _mask);
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_mask |= (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
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HAL_WRITE_UINT16(_FRV400_IRC_MASK, _mask);
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}
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void hal_interrupt_unmask(int vector)
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{
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cyg_uint16 _mask;
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_LAN:
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HAL_READ_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
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_mask &= ~_FRV400_FPGA_IRQ_LAN;
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HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
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break;
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}
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HAL_READ_UINT16(_FRV400_IRC_MASK, _mask);
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_mask &= ~(1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
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HAL_WRITE_UINT16(_FRV400_IRC_MASK, _mask);
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}
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void hal_interrupt_acknowledge(int vector)
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{
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cyg_uint16 _mask;
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_LAN:
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HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_REQUEST, // Clear LAN interrupt
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0x7FFE & ~_FRV400_FPGA_IRQ_LAN);
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break;
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}
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_mask = (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
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HAL_WRITE_UINT16(_FRV400_IRC_RC, _mask);
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HAL_WRITE_UINT16(_FRV400_IRC_IRL, 0x10); // Clears IRL latch
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}
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//
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// Configure an interrupt
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// level - boolean (0=> edge, 1=>level)
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// up - edge: (0=>falling edge, 1=>rising edge)
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// level: (0=>low, 1=>high)
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//
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void hal_interrupt_configure(int vector, int level, int up)
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{
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cyg_uint16 _irr, _tmr, _trig;
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if (level) {
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if (up) {
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_trig = 0; // level, high
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} else {
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_trig = 1; // level, low
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}
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} else {
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if (up) {
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_trig = 2; // edge, rising
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} else {
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_trig = 3; // edge, falling
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}
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}
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279 |
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switch (vector) {
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case CYGNUM_HAL_INTERRUPT_TIMER0:
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HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
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_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
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HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
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HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
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_tmr = (_tmr & 0xFFFC) | (_trig<<0);
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HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
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break;
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case CYGNUM_HAL_INTERRUPT_TIMER1:
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HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
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_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
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HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
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HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
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_tmr = (_tmr & 0xFFF3) | (_trig<<2);
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HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
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break;
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case CYGNUM_HAL_INTERRUPT_TIMER2:
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HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
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_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
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HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
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HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
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_tmr = (_tmr & 0xFFCF) | (_trig<<4);
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HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
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break;
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case CYGNUM_HAL_INTERRUPT_DMA0:
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HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
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_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
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307 |
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HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
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308 |
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HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
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309 |
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_tmr = (_tmr & 0xFCFF) | (_trig<<8);
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310 |
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HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
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311 |
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break;
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312 |
|
|
case CYGNUM_HAL_INTERRUPT_DMA1:
|
313 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
314 |
|
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
315 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
316 |
|
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
317 |
|
|
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
|
318 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
319 |
|
|
break;
|
320 |
|
|
case CYGNUM_HAL_INTERRUPT_DMA2:
|
321 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
322 |
|
|
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
|
323 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
324 |
|
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
325 |
|
|
_tmr = (_tmr & 0xCFFF) | (_trig<<12);
|
326 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
327 |
|
|
break;
|
328 |
|
|
case CYGNUM_HAL_INTERRUPT_DMA3:
|
329 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
330 |
|
|
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
|
331 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
332 |
|
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
333 |
|
|
_tmr = (_tmr & 0x3FFF) | (_trig<<14);
|
334 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
335 |
|
|
break;
|
336 |
|
|
case CYGNUM_HAL_INTERRUPT_UART0:
|
337 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR6, _irr);
|
338 |
|
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
339 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR6, _irr);
|
340 |
|
|
HAL_READ_UINT16(_FRV400_IRC_ITM1, _tmr);
|
341 |
|
|
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
|
342 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM1, _tmr);
|
343 |
|
|
break;
|
344 |
|
|
case CYGNUM_HAL_INTERRUPT_UART1:
|
345 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR6, _irr);
|
346 |
|
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
347 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR6, _irr);
|
348 |
|
|
HAL_READ_UINT16(_FRV400_IRC_ITM1, _tmr);
|
349 |
|
|
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
|
350 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM1, _tmr);
|
351 |
|
|
break;
|
352 |
|
|
case CYGNUM_HAL_INTERRUPT_EXT0:
|
353 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
354 |
|
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
355 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
356 |
|
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
357 |
|
|
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
|
358 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
359 |
|
|
break;
|
360 |
|
|
case CYGNUM_HAL_INTERRUPT_EXT1:
|
361 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
362 |
|
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
363 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
364 |
|
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
365 |
|
|
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
|
366 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
367 |
|
|
break;
|
368 |
|
|
case CYGNUM_HAL_INTERRUPT_EXT2:
|
369 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
370 |
|
|
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
|
371 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
372 |
|
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
373 |
|
|
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
|
374 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
375 |
|
|
break;
|
376 |
|
|
case CYGNUM_HAL_INTERRUPT_EXT3:
|
377 |
|
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
378 |
|
|
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
|
379 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
380 |
|
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
381 |
|
|
_tmr = (_tmr & 0xFF3F) | (_trig<<6);
|
382 |
|
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
383 |
|
|
break;
|
384 |
|
|
default:
|
385 |
|
|
; // Nothing to do
|
386 |
|
|
};
|
387 |
|
|
}
|
388 |
|
|
|
389 |
|
|
void hal_interrupt_set_level(int vector, int level)
|
390 |
|
|
{
|
391 |
|
|
// UNIMPLEMENTED(__FUNCTION__);
|
392 |
|
|
}
|
393 |
|
|
|
394 |
|
|
// PCI support
|
395 |
|
|
|
396 |
|
|
externC void
|
397 |
|
|
_frv400_pci_init(void)
|
398 |
|
|
{
|
399 |
|
|
static int _init = 0;
|
400 |
|
|
cyg_uint8 next_bus;
|
401 |
|
|
cyg_uint32 cmd_state;
|
402 |
|
|
|
403 |
|
|
if (_init) return;
|
404 |
|
|
_init = 1;
|
405 |
|
|
|
406 |
|
|
// Enable controller - most of the basic configuration
|
407 |
|
|
// was set up at boot time in "platform.inc"
|
408 |
|
|
|
409 |
|
|
// Setup for bus mastering
|
410 |
|
|
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
411 |
|
|
CYG_PCI_CFG_COMMAND, cmd_state);
|
412 |
|
|
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
|
413 |
|
|
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
414 |
|
|
CYG_PCI_CFG_COMMAND,
|
415 |
|
|
CYG_PCI_CFG_COMMAND_MEMORY |
|
416 |
|
|
CYG_PCI_CFG_COMMAND_MASTER |
|
417 |
|
|
CYG_PCI_CFG_COMMAND_PARITY |
|
418 |
|
|
CYG_PCI_CFG_COMMAND_SERR);
|
419 |
|
|
|
420 |
|
|
// Setup latency timer field
|
421 |
|
|
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
422 |
|
|
CYG_PCI_CFG_LATENCY_TIMER, 32);
|
423 |
|
|
|
424 |
|
|
// Configure PCI bus.
|
425 |
|
|
next_bus = 1;
|
426 |
|
|
cyg_pci_configure_bus(0, &next_bus);
|
427 |
|
|
}
|
428 |
|
|
|
429 |
|
|
}
|
430 |
|
|
|
431 |
|
|
externC void
|
432 |
|
|
_frv400_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
|
433 |
|
|
{
|
434 |
|
|
cyg_uint8 req;
|
435 |
|
|
cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);
|
436 |
|
|
|
437 |
|
|
if (dev == CYG_PCI_MIN_DEV) {
|
438 |
|
|
// On board LAN
|
439 |
|
|
*vec = CYGNUM_HAL_INTERRUPT_LAN;
|
440 |
|
|
*valid = true;
|
441 |
|
|
} else {
|
442 |
|
|
HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req);
|
443 |
|
|
if (0 != req) {
|
444 |
|
|
CYG_ADDRWORD __translation[4] = {
|
445 |
|
|
CYGNUM_HAL_INTERRUPT_PCIINTC, /* INTC# */
|
446 |
|
|
CYGNUM_HAL_INTERRUPT_PCIINTB, /* INTB# */
|
447 |
|
|
CYGNUM_HAL_INTERRUPT_PCIINTA, /* INTA# */
|
448 |
|
|
CYGNUM_HAL_INTERRUPT_PCIINTD}; /* INTD# */
|
449 |
|
|
|
450 |
|
|
/* The PCI lines from the different slots are wired like this */
|
451 |
|
|
/* on the PCI backplane: */
|
452 |
|
|
/* pin6A pin7B pin7A pin8B */
|
453 |
|
|
/* I/O Slot 1 INTA# INTB# INTC# INTD# */
|
454 |
|
|
/* I/O Slot 2 INTD# INTA# INTB# INTC# */
|
455 |
|
|
/* I/O Slot 3 INTC# INTD# INTA# INTB# */
|
456 |
|
|
/* */
|
457 |
|
|
/* (From PCI Development Backplane, 3.2.2 Interrupts) */
|
458 |
|
|
/* */
|
459 |
|
|
/* Devsel signals are wired to, resulting in device IDs: */
|
460 |
|
|
/* I/O Slot 1 AD30 / dev 19 [(8+1)&3 = 1] */
|
461 |
|
|
/* I/O Slot 2 AD29 / dev 18 [(7+1)&3 = 0] */
|
462 |
|
|
/* I/O Slot 3 AD28 / dev 17 [(6+1)&3 = 3] */
|
463 |
|
|
|
464 |
|
|
*vec = __translation[((req+dev)&3)];
|
465 |
|
|
*valid = true;
|
466 |
|
|
} else {
|
467 |
|
|
/* Device will not generate interrupt requests. */
|
468 |
|
|
*valid = false;
|
469 |
|
|
}
|
470 |
|
|
diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec);
|
471 |
|
|
}
|
472 |
|
|
}
|
473 |
|
|
|
474 |
|
|
// PCI configuration space access
|
475 |
|
|
#define _EXT_ENABLE 0x80000000 // Could be 0x80000000
|
476 |
|
|
|
477 |
|
|
static __inline__ cyg_uint32
|
478 |
|
|
_cfg_addr(int bus, int devfn, int offset)
|
479 |
|
|
{
|
480 |
|
|
return _EXT_ENABLE | (bus << 22) | (devfn << 8) | (offset << 0);
|
481 |
|
|
}
|
482 |
|
|
|
483 |
|
|
externC cyg_uint8
|
484 |
|
|
_frv400_pci_cfg_read_uint8(int bus, int devfn, int offset)
|
485 |
|
|
{
|
486 |
|
|
cyg_uint32 cfg_addr, addr, status;
|
487 |
|
|
cyg_uint8 cfg_val = (cyg_uint8)0xFF;
|
488 |
|
|
|
489 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
490 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
491 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
492 |
|
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
493 |
|
|
// PCI bridge
|
494 |
|
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x03);
|
495 |
|
|
} else {
|
496 |
|
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x03);
|
497 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
498 |
|
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x03);
|
499 |
|
|
}
|
500 |
|
|
HAL_READ_UINT8(addr, cfg_val);
|
501 |
|
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
502 |
|
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
503 |
|
|
// Cycle failed - clean up and get out
|
504 |
|
|
cfg_val = (cyg_uint8)0xFF;
|
505 |
|
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
506 |
|
|
}
|
507 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
508 |
|
|
diag_printf("%x\n", cfg_val);
|
509 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
510 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
511 |
|
|
return cfg_val;
|
512 |
|
|
}
|
513 |
|
|
|
514 |
|
|
externC cyg_uint16
|
515 |
|
|
_frv400_pci_cfg_read_uint16(int bus, int devfn, int offset)
|
516 |
|
|
{
|
517 |
|
|
cyg_uint32 cfg_addr, addr, status;
|
518 |
|
|
cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;
|
519 |
|
|
|
520 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
521 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
522 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
523 |
|
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
524 |
|
|
// PCI bridge
|
525 |
|
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x02);
|
526 |
|
|
} else {
|
527 |
|
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
|
528 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
529 |
|
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
|
530 |
|
|
}
|
531 |
|
|
HAL_READ_UINT16(addr, cfg_val);
|
532 |
|
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
533 |
|
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
534 |
|
|
// Cycle failed - clean up and get out
|
535 |
|
|
cfg_val = (cyg_uint16)0xFFFF;
|
536 |
|
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
537 |
|
|
}
|
538 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
539 |
|
|
diag_printf("%x\n", cfg_val);
|
540 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
541 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
542 |
|
|
return cfg_val;
|
543 |
|
|
}
|
544 |
|
|
|
545 |
|
|
externC cyg_uint32
|
546 |
|
|
_frv400_pci_cfg_read_uint32(int bus, int devfn, int offset)
|
547 |
|
|
{
|
548 |
|
|
cyg_uint32 cfg_addr, addr, status;
|
549 |
|
|
cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
|
550 |
|
|
|
551 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
552 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
553 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
554 |
|
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
555 |
|
|
// PCI bridge
|
556 |
|
|
addr = _FRV400_PCI_CONFIG + (offset << 1);
|
557 |
|
|
} else {
|
558 |
|
|
cfg_addr = _cfg_addr(bus, devfn, offset);
|
559 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
560 |
|
|
addr = _FRV400_PCI_CONFIG_DATA;
|
561 |
|
|
}
|
562 |
|
|
HAL_READ_UINT32(addr, cfg_val);
|
563 |
|
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
564 |
|
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
565 |
|
|
// Cycle failed - clean up and get out
|
566 |
|
|
cfg_val = (cyg_uint32)0xFFFFFFFF;
|
567 |
|
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
568 |
|
|
}
|
569 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
570 |
|
|
diag_printf("%x\n", cfg_val);
|
571 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
572 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
573 |
|
|
return cfg_val;
|
574 |
|
|
}
|
575 |
|
|
|
576 |
|
|
externC void
|
577 |
|
|
_frv400_pci_cfg_write_uint8(int bus, int devfn, int offset, cyg_uint8 cfg_val)
|
578 |
|
|
{
|
579 |
|
|
cyg_uint32 cfg_addr, addr, status;
|
580 |
|
|
|
581 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
582 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
583 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
584 |
|
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
585 |
|
|
// PCI bridge
|
586 |
|
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x03);
|
587 |
|
|
} else {
|
588 |
|
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x03);
|
589 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
590 |
|
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x03);
|
591 |
|
|
}
|
592 |
|
|
HAL_WRITE_UINT8(addr, cfg_val);
|
593 |
|
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
594 |
|
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
595 |
|
|
// Cycle failed - clean up and get out
|
596 |
|
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
597 |
|
|
}
|
598 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
599 |
|
|
}
|
600 |
|
|
|
601 |
|
|
externC void
|
602 |
|
|
_frv400_pci_cfg_write_uint16(int bus, int devfn, int offset, cyg_uint16 cfg_val)
|
603 |
|
|
{
|
604 |
|
|
cyg_uint32 cfg_addr, addr, status;
|
605 |
|
|
|
606 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
607 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
608 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
609 |
|
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
610 |
|
|
// PCI bridge
|
611 |
|
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x02);
|
612 |
|
|
} else {
|
613 |
|
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
|
614 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
615 |
|
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
|
616 |
|
|
}
|
617 |
|
|
HAL_WRITE_UINT16(addr, cfg_val);
|
618 |
|
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
619 |
|
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
620 |
|
|
// Cycle failed - clean up and get out
|
621 |
|
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
622 |
|
|
}
|
623 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
624 |
|
|
}
|
625 |
|
|
|
626 |
|
|
externC void
|
627 |
|
|
_frv400_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
|
628 |
|
|
{
|
629 |
|
|
cyg_uint32 cfg_addr, addr, status;
|
630 |
|
|
|
631 |
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
632 |
|
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
633 |
|
|
#endif // CYGPKG_IO_PCI_DEBUG
|
634 |
|
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
635 |
|
|
// PCI bridge
|
636 |
|
|
addr = _FRV400_PCI_CONFIG + (offset << 1);
|
637 |
|
|
} else {
|
638 |
|
|
cfg_addr = _cfg_addr(bus, devfn, offset);
|
639 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
640 |
|
|
addr = _FRV400_PCI_CONFIG_DATA;
|
641 |
|
|
}
|
642 |
|
|
HAL_WRITE_UINT32(addr, cfg_val);
|
643 |
|
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
644 |
|
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
645 |
|
|
// Cycle failed - clean up and get out
|
646 |
|
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
647 |
|
|
}
|
648 |
|
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
649 |
|
|
}
|
650 |
|
|
|
651 |
|
|
/*------------------------------------------------------------------------*/
|
652 |
|
|
// EOF frv400_misc.c
|